TECHNICAL PROGRAM

Tuesday, April 11, 8:00 a.m., Imperial Ballroom

SYMPOSIUM OPENING:

Jon E. Klema, Symposium General Chair
William R. Tonti, Technical Program Chair

Keynote:
Silicon Technology Directions in the New Millenium
—Tak H. Ning, IBM Thomas J. Watson Research Center, Yorktown Heights, NY

Although its performance and density are fast approaching saturation, scaled bulk CMOS will remain the platform for evolving silicon technology into several application-specific directions. Besides logic and memory, there will be emphases on low power, on EEPROM, RF, and analog, and integration of these functions on the same chip or package. The opportunities and challenges will be discussed.

DIELECTRICS (Session 1)

Co-Chairs: Ernest Wu, IBM MicroElectronics and
Robin Degraeve, IMEC

1.1 EXPERIMENTAL EVIDENCE FOR VOLTAGE DRIVEN BREAKDOWN MODELS IN ULTRATHIN GATE OXIDES—P.E. Nicollian, W.R. Hunter, and J.C. Hu, Texas Instruments, Inc., Dallas, TX

We have performed an experiment proving that the widely accepted Efield TDDB model is a physically incorrect description of breakdown in ultra-thin gate oxides. Although interface traps are the dominant SILC mechanism below 5V stress, we confirm that breakdown remains limited by bulk trap generation and is voltage-driven.

1.2 TUNNELING CURRENT CHARACTERISTICS AND OXIDE BREAKDOWN IN P+POLY-SILICON PFET CAPACITORS—J. McKenna and E.Y. Wu, IBM Microelectronics Division, Essex Junction, VT

It was found that measured tunneling currents in lightly doped P+ poly-silicon gate are much higher and result in much shorter times-to-breakdown as compared with heavily doped P+ poly-silicon. Our results strongly suggest that oxide breakdown is energy- and fluence- driven rather than time- and field driven as commonly accepted.

1.3 FIELD ACCELERATION FOR OXIDE BREAKDOWN - CAN AN ACCURATE ANODE HOLE INJECTION MODEL RESOLVE THE E VS. 1/E CONTROVERSY?—M.A. Alam, J. Bude and A. Ghetti, Lucent Technologies, Murray Hill, NJ

We show that an anode hole injection model can resolve the controversies involving oxide reliability projection including E vs. 1/E field acceleration, the polarity gap, and the thickness dependence of field acceleration. The most accurate extrapolations can be made by placing accelerated breakdown data on a voltage versus ln(tBD) curve whose shape is universal.

1.4 ANODE HOLE INJECTION VERSUS HYDROGEN RELEASE: THE MECHANISM FOR GATE OXIDE BREAKDOWN—J.Wu, E. Rosenbaum, University of Illinois, Urbana, IL, B. MacDonald, AMD, Sunnyvale, CA, E. Li, University of Illinois, Urbana, IL, J. Tao, B. Tracy, and P. Fang, AMD, Sunnyvale, CA

The gate oxide reliability of deuterium annealed MOS devices is similar to that of hydrogen annealed devices while the hot carrier lifetime is over one order of magnitude larger. This finding sheds doubt on a gate oxide breakdown model that purports that a necessary step is release of interfacial hydrogen by tunneling electrons.

1.5 TEMPERATURE DEPENDENCE OF SOFT BREAKDOWN AND WEAROUT IN SUB 3nm SiO2 FILMS—J.S. Suehle and E. Vogel, NIST, Gaithersburg, MD, B. Wang and J.B. Bernstein, University of Maryland, College Park, MD

The temperature dependence of breakdown for sub-3 nm SiO2 films was studied. The results indicate that both soft and hard breakdown modes exhibit the same thermal acceleration. The thermal activation energy is observed to decrease for higher gate voltages which may explain the observation of increased temperature acceleration for ultra-thin films.

1.6 STUDY OF THE TEMPERATURE AND VOLTAGE ACCELERATION BEHAVIOR OF SOFT BREAKDOWN AND HARD BREAKDOWN IN ULTRA-THIN SiO2 GATE DIELECTRICS—T. Pomp, H. Wurzer*, M. Kerber, Infineon Technologies, Muenchen, Germany, and I. Eisele, Universitaet der Bundeswehr Muenchen, Neubiberg, Germany *Infineon Technologies, Dresden,Germany

It is shown that soft breakdown (SBD) has significantly different temperature and voltage acceleration behavior than does hard breakdown (HBD). These properties influence reliability characterization of ultra-thin SiO2 gate dielectrics. A mix-up of times to SBD and HBD during TDDB testing can result in erroneous conclusions.

1.7 QUASI-REAKDOWN IN ULTRA-THIN SiO2 FILMS : OCCURRENCE CHARACTERIZATION AND RELIABILITY ASSESSMENT METHODOLOGY—S. Bruyere, E. Vincent, STMicrolectronics, Crolles, France and G. Ghibaudo, LPCS, ENSERG, Grenoble, France

The area, electric field, and temperature dependencies of quasi-breakdown and breakdown are investigated. We demonstrate that the physical defects related to the quasi-breakdown phenomenon are different from those related to breakdown. We introduce the concept that breakdown and quasi-breakdown are competing mechanisms.

Tuesday, April 11, 2:00 p.m., Parallel Sessions 2A_2B & 2C_2D

DIELECTRICS II (Session 2A, Imperial Ballroom)
( in parallel with 2C_2D and followed by 2B)

Co-Chairs: Ernest Wu, IBM MicroElectronics and
Bonnie E. Weir, IMEC

2A.1 EVIDENCE FOR RECOMBINATION AT OXIDE DEFECTS AND NEW SILC MODEL—D. Ielmini, A.S. Spinelli*, A.L. Lacaita, Politecnico di Milano, Milano, Italy, and G. Ghidini, STMicroelectronics, Agrate Brianza, Italy *Università dell'Insubria, Como, Italy

A detailed experimental study of SILC dependencies on time, stress fluence, and polysilicon doping shows that electron-hole recombination at bulk oxide defects plays a primary role in low-field SILC. A numerical model based on this novel mechanism successfully reproduces leakage phenomena for oxide thicknesses ranging from 2.8 to 8.2 nm.

2A.2 EXPERIMENTAL ANALYSIS OF GATE OXIDE DEGRADATION _EXISTENCE OF NEUTRAL TRAP PRECURSOR, SINGLE AND MULTIPLE TRAP-ASSISTED TUNNELING FOR SILC MECHANISM_ —R.Yamada, J.Yugami, and M. Ohkura, Hitachi, Ltd., Kokubunji, Tokyo

We have analyzed gate oxide degradation and conclude that neutral traps are generated when hot holes attack the trap precursors. These neutral traps induce an excess leakage current, the so-called SILC. The conduction mechanism of SILC changes from single trap-assisted tunneling (TAT) to multiple-TAT as the neutral trap density increases in thick (> 6 nm) oxides.

2A.3 TEMPERATURE EFFECT ON THE RELIABILITY OF ZrO2 GATE DIELECTRIC DEPOSITED DIRECTLY ON SILICON—W.-J. Qi, R. Nieh, B.H. Lee, L. Kang, Y. Jeon, K. Onishi, S. Gopalan, and J.C. Lee, University of Texas, Austin, TX

The effect of temperature on the reliability of ZrO2 films is investigated. At 150 °C, an operating voltage of -1.95V yields an extrapolated 10 year lifetime. No enhanced trap generation is observed at elevated temperatures. ZrO2 exhibits a lower activation energy than does thermal oxide which indicates an improved temperature accelerated dielectric breakdown.

HOT CARRIERS (Session 2B, Imperial Ballroom)
(following 2A and in parallel with 2C_2D)

Co-Chairs: Ronald C. Lacoe, The Aerospace Corporation
Giuseppe La Rosa, IBM MicroElectronics

2B.1 CHANNEL-WIDTH DEPENDENT HOT-CARRIER DEGRADATION OF THIN-GATE pMOSTs— Y.-H. Lee, K. Wu, T. Linton, N. Mielke, S. Hu, and B. Wallace, Intel Corp., Santa Clara, CA

Channel width dependent pMOST hot-carrier degradation has been investigated in a 0.25 µm CMOS technology. Two distinct trapping mechanisms were observed in the narrow (electron trapping) and wide (hole trapping) devices. Simulations indicate that the electric field difference between the STI edge and channel area is responsible for these results.

2B.2 THE ROLE OF THE SPACER OXIDE IN DETERMINING WORST-CASE HOT-CARRIER STRESS CONDITIONS FOR NMOS DEVICES—E.E. King, R.C. Lacoe, The Aerospace Corp., Los Angeles, CA and J. Wang-Ratkovic, AMD, Sunnyvale, CA

Experimental data and a model are presented that explain the contribution of the LDD series resistance increase to the cross over in worst-case bias condition (from maximum substrate current to maximum gate voltage) for NMOS LDD transistors. The dependence of this effect to channel length and temperature are also described.

2B.3 GENERATION OF HOT CARRIERS BY SECONDARY IMPACT IONIZATION IN DEEP SUBMICRON DEVICES: MODEL AND LIGHT EMISSION CHARACTERIZATION—B. Marchand, D. Blachier*, G. Ghibaudo, C. Leroux, F. Balestra, and G. Reimbold*, LPCS-ENSERG, Grenoble, France *LETI-CEA, Grenoble, France

A simple and accurate analytical model of the gate current due to the secondary impact ionization in deep submicron MOS devices is given, taking the substrate bias and the temperature influences into account. In addition, for the first time the related light emission spectrum and photon origin are presented.

2B.4 ANALYSIS OF HOT-CARRIER-INDUCED DEGRADATION IN MOSFET BY GATE-TO-DRAIN AND GATE-TO-SUBSTRATE CAPACITANCE MEASUREMENT—C. Hsu, M. Lau, and Y.T. Yeow, The University of Queensland, Brisbane, Australia, and Z.Q. Yao, Quality Semiconductors Australia, Sydney, Australia

This paper describes and demonstrates the use of gate-to-drain capacitance measurements at below liquid nitrogen temperature as a tool to characterize the hot carrier induced charge centers. In addition, a new method based on gate-to-substrate capacitance is proposed to extract the spatial distribution of fixed oxide charges.

2B.5 HOT CARRIER INDUCED DEGRADATION IN DEEP SUBMICRON MOSFETs AT 100 °C—E. Li, E. Rosenbaum, and L.F. Register, University of Illinois at Urbana-Champaign, Urbana, IL, and J. Tao, and P. Fang, AMD, Sunnyvale, CA

For deep submicron n- and p-MOSFETs, Vg=Vd is demonstrated to be the worst-case hot-carrier stress condition. Degradation is more severe at 100 °C than at room temperature, even at stress voltages greater than 2.5V. The effect of the channel length on the temperature dependence of the substrate current is examined.

2B.6 EARLY STAGE HOT CARRIER DEGRADATION OF STATE-OF-THE-ART LDD n-MOSFETs—S.K. Manhas, M.M. De Souza, De Montfort University, Leicester, U.K., A.S. Oates, S.S. Chetlur, Lucent Technologies, Orlando, FL, and E.M. Sankara Narayanan, De Montfort University, Leicester, U.K.

Detailed hot carrier degradation experiments beginning as early as 10 µs in submicron n-channel LDD MOSFETs reveal a new early two-stage series resistance degradation process, which deviates from the power law behavior. Detailed quantitative analysis suggests this LDD induced-damage saturates within 10 seconds, far earlier than reported in the literature.

MEMS (Session 2C, Regency Room in parallel with 2A_2B)

Co-Chairs: William M. Miller, Sandia National Laboratories
Sam Kayali, Jet Propulsion Laboratory

2C.1 RELIABILITY CHARACTERIZATION OF THERMAL MICRO-STRUCTURES IMPLEMENTED ON 0.8 MICRON CMOS CHIPS—L. Y. Sheng, C. De Tandt, W. Ranson, and R. Vounckx, The University of Brussels, Brussels, Belgium

This paper discusses the reliability characterization of thermal micro-structures implemented on industrial 0.8 µm CMOS chips. Various failure mechanisms are identified and evaluated under high temperature operations. The results can be used to optimize the design of thermally-based microsensors on CMOS chips.

2C.2 RELIABILITY STUDIES OF BENT-BEAM ELECTRO-

THERMAL ACTUATORS—L. Que, J.-S. Park, M.-H. Li, Y.B. Gianchandani, University of Wisconsin, Madison, WI
This paper reports on the first lifetime studies of bent beam electro-thermal microactuators that are being used to drive safing and arming micromechanisms. Lifetimes are linked to actuation conditions and dimensional parameters, suggesting an inverse correlation between lifetime and beam stress. Some devices are stable for >30 million actuation cycles.

2C.3 NONTACTILE RELIABILITY TESTING OF A MICRO OPTICAL ATTENUATOR—C. Rembe, H. Aschemann, S. aus der Wiesche, E.P. Hofer, University of Ulm, Ulm, Germany, and H. Debeda, J. Mohe, and U. Wallrabe, Institute of Microstructure Technology, Karlsruhe, Germany

The reliability investigations presented in this paper have been performed on a micro optoelectromechanical actuator developed for switching and attenuation of light propagation in optical fibers. It is demonstrated that high speed cine-photomicrography together with model based evaluation of the image sequences is a powerful diagnostic tool for reliability testing of dynamic processes in MEMS.

2C.4 MEMS RELIABILITY IN A SHOCK ENVIRONMENT — D.M. Tanner, K.S. Helgesen, J.A. Walraven, J.J. Clement, L.W. Irwin, F.A. Brown, and D.L.Gregory, Sandia National Laboratories, Albuquerque, NM

A surface-micromachined MEMS device, consisting of an electrostatic comb-drive actuator driving a single gear, has been tested in an extreme shock environment along three axes. The microengines survived stress levels 20 times higher than those expected in actual use, showing them to be extremely robust.

2C.5 MEMS RELIABILITY IN A VIBRATION ENVIRONMENT — D.M. Tanner, K.S. Helgesen, J.A. Walraven, J.J. Clement, L.W. Irwin, F.A. Brown, and D.L.Gregory, Sandia National Laboratories, Albuquerque, NM

A surface-micromachined MEMS device, consisting of an electrostatic comb-drive actuator driving a single gear, has been tested using three modes of extreme white noise vibration. The microengines survived stress levels four times higher than those expected in actual use, showing them to be extremely robust.

2C.6 EFFECT OF W COATING ON MICROENGINE PERFORMANCE—S. S. Mani, J. G. Fleming, J. A. Walraven, J. J. Sniegowski, M.P. de Boer , L.W. Irwin, D.M. Tanner, D.A. LaVan, J. Jakubczak, and W.M. Miller, Sandia National Laboratories, Albuquerque, NM

A process was used to selectively coat MEMS devices with tungsten (W) using chemical vapor deposition (CVD) techniques. This coating is very conformal, having excellent step coverage, and is extremely uniform. Tungsten coated MEMS microengines tested for reliability show improved wear characteristics with longer lifetimes than polysilicon microengines.

DEVICE & PROCESS I (Session 2D, Regency Ballroom)
(following 2C & in parallel with 2A_2B)

Co-Chairs: E. Ajith Amerasekera, Texas Instruments, Inc.
Klaus F. Schuegraf, Conexant Systems

2D.1 NEUTRON-INDUCED BORON FISSION AS A MAJOR SOURCE OF SOFT ERRORS IN DEEP SUBMICRON SRAM DEVICES—R.C. Baumann and E.B. Smith, Texas Instruments, Dallas, TX

Reports the impact of cosmic neutron induced 10B fissions in production logic devices. Using a specially designed cold neutron source to probe soft-error events caused by 10B fissions in deep-submicron SRAM devices fabricated with and without borophosphosilicate glass establishes both the presence and magnitude of these soft-error events.

2D.2 MULTI PARAMETER METHOD FOR YIELD ANALYSIS AND RELIABILITY ASSESSMENT—Y. Mitnick, B. Lisenker, U. Sasson, Intel, Haifa, Israel, and R. Miller, Intel, Chandler, AZ

Introduces a new criteria for product margin and reliability risk assessment using a 0.25 µm CMOS microprocessor technology, based on standby current, fmax and XY die location. The criteria provide the rule for segregating units into groups with differerent margins with respect to parametric variations and stresses. Data analysis at Sort permits prediction of final test fall-out for high-risk groups with > 16% probability.

2D.3 CMOSFET CHARACTERISTICS INDUCED BY MOISTURE DIFFUSION FROM INTER-LAYER DIELECTRIC IN 0.23 µm DRAM TECHNOLOGY WITH SHALLOW TRENCH ISOLATION—S.K. Park, M.-S. Suh, J.Y. Kim, G.-H. Yoon, Hyundai Microelectronics Co. Ltd., Cheongju-si, Korea

Investigates the impact of moisture diffusion from ILD layer in 0.23 µm DRAM on CMOSFET characteristics. The nMOSFET shows an anomalous short-channel hump, while the CMOSFET shows decreased short-channel margin. This study investigates the use of different barrier films to suppress these effects.

Tuesday, April 11, 6:30 — 9:30 p.m.

SYMPOSIUM RECEPTION

The Tech Museum of Innovation

The Tech Museum of Innovation which is located within short walking distance directly across Plaza de Cesar Chavez from the hotel. Attendees will long remember designing their own roller coaster and test driving it using 3-D simulation software, or maneuvering a remotely-operated vehicle through a 7700 gallon water-filled tank. Galleries include Communication: Global Connections, Innovation: Silicon Valley and Beyond, Exploration: New Frontiers, and Life Tech: The Human Machine. A light buffet will also be provided for Symposium attendees and their guests.

Wednesday, April 12, 8:15 a.m., Parallel Session 3A &3B_3C

DEVICE & PROCESS II (Sess. 3A, Imperial Ballroom)

Co-Chairs: E. Ajith Amerasekera, Texas Instruments, Inc.
Klaus F. Schuegraf, Conexant Systems

3A.1 ONE TIME PROGRAMMABLE DRIFT ANTIFUSE CELL RELIABILITY—P. Candelier, N. Villani, and J.-P. Schoellkopf, STMicroelectronics, Crolles, France

An innovative non-volatile memory cell compatible with standard CMOS process and based on tunnel oxide breakdown is presented. Both device architecture and design are limiting non-selected cells oxide stress to reach the 10-year lifetime criteria. Broken-down oxide read current stability under bias and temperature is also shown.

3A.2 HOT-CARRIER RELIABILITY OF LATERAL DMOS TRANSISTORS—V. O'Donovan, S. Whiston, and A. Deignan, Analog Devices, Limerick, Ireland

Investigates degradation induced by hot electrons in lateral DMOS transistors. Illustrates limitation of existing CMOS/BiCMOS stressing techniques and models. Simulation results support the validity of modified LDMOS stressing techniques. Experimental results determine a hot-electron safe-operating-area for reliable LDnMOS and LDpMOS operation.

3A.3 HIGH PERFORMANCE DEEP-SUBMICRON nMOSFETs BY NITROGEN IMPLANTATION AND IN-SITU HF CLEAN—J.H. Chen, T.F. Lei, National Chiao Tung University, Hsinchu, Taiwan, C.L. Chen, T.S. Chao, National Nano Device Laboratory, Hsinchu, Taiwan, W.Y. Wen, and K.T. Chen, Winbon Electronics Corp., Hsinchu, Taiwan

Significant improvement of nMOSFETs results from using nitrogen implantation and in-situ HF vapor clean in oxide processing. The interface becomes smoother with less Arsenic incorporation in the channel region, thereby improving device performance and reliability.

3A.4 ROLE OF H2 ANNEAL IN THIN OXIDE FOR MULTI-METAL-LAYER CMOS PROCESS—Y.-H. Lee, R. Nachman, and K. Seshan, Intel Corp., Santa Clara, CA

Investigates the impact of H2 in the final annealing cycle of a 5-layer CMOS process and its effect on device behavior using Al/Ti metallization technology. Bias-temperature and hot-carrier data show little difference for changes in H2 dilution. Differences are reported for devices with varying degrees of metal coverage.

3A.5 ANALYSIS OF EVOLUTION TO AND BEYOND QUASI-BREAKDOWN IN ULTRA-THIN OXIDE AND OXYNITRIDE—M. Okandan, J.S. Fonash, The Penn. State Univ., University Park, PA, B. Maiti, H.H. Tseng, and P. Tobin, Motorola, Austin, TX

Presents the wearout, quasi-breakdown and annealing behavior of 30Å ultrathin oxide and oxynitride films. Shows distinctive differences between devices subject to quasi-breakdown and full breakdown. Demonstrates the impact of thermal annealing on these devices as well as the ramifications for next generation CMOS technologies.

3A6 A NEW DATA RETENTION MECHANISM AFTER ENDURANCE STRESS ON FLASH MEMORY—H. Kameyama, UL Media Ltd., Tokyo, Japan, Y.Okuyama, S. Kamohara, K. Kubota, H. Kume, M. Kato, A. Nozoe, H. Uchida, M. Hidaka, Hitachi Ltd., Tokyo, Japan, and K, Ogura, UL Media Ltd., Tokyo, Japan

Data retention after endurance cycling in FLASH memory is explained by combining two retention models. One model for temperatures greater than 150 °C indicates the inherent retention characteristics are ruled by the thermal emission model. Another model for temperatures between 85 °C and 125 °C indicates that retention is determined by hopping conduction through trap-assisted B-mode SILC currents.

3A.7 ANALYSIS OF DETRAP CURRENT DUE TO OXIDE TRAPS TO IMPROVE FLASH MEMORY RETENTION—R. Yamada, Y. Mori, Y. Okuyama, J. Yugami, T. Nishimoto, and H. Kume, Hitachi Ltd., Tokyo, Japan

Gate oxide detrapping currents are measured to improve flash memory retention. These detrapping currents can be divided into two categories. One is due to direct tunneling to the silicon substrate from deep oxide traps, while the other is due to emission into the SiO2 conduction band from shallower oxide traps. The deeper traps are generated at the SiSiO2 interface by hot electrons during gate negative FN stress and the shallower taps are generated at Poly/SiO2 interface by hot holes.

3A.8 BIAS TEMPERATURE DEGRADATION OF pMOSFETs: MECHANISM AND ITS SUPPRESSION—M. Makabe, T. Kubota, and T. Kitano, NEC Corp., Sagamihara, Kanagawa, Japan

The bias-temperature mechanism and its suppression are analyzed in pMOSFETs. Degradation is found to be due to trapped holes produced by impact ionization of electrons injected from the gate electrode. This degradation can be suppressed by doping the gate oxide with boron and by reducing the electric-field strength between the drain and the gate electrodes.

PACKAGING (Sessions 3B, Regency Ballroom)
(in parallel with 3A and followed by 3C)

Co-Chairs: Thomas M. Moore, Texas Instruments, Inc.
S. Sidharth, Advanced Micro Devices

3B.1 LIFETIME PREDICTION OF IGBT MODULES FOR TRACTION APPLICATIONS—M. Ciappa and W. Fichtner, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland

Bond wire lift-off caused by thermal fatigue is one of the dominant failure mechanisms of high power Insulator Gate Bipolar Transistor multichip modules used in traction applications (railway). A model is proposed which predicts the lifetime of devices submitted to severe cyclic loads encountered in current converters of railway systems. It assumes linear accumulation of the thermal cycle fatigue damage and takes into account bondwire redundancy in the multichip module.

3B.2 FAILURE ANALYSIS & STRESS SIMULATION IN SMALL CHIP MULTICHIP BGAs—T.D. Moore, Analog Devices, Limerick, Ireland, and J.L. Jarvis, University of Limerick, Limerick, Ireland

Although many studies have been published on stress-related failures in flip chip joints and BGA solder ball joints, little has been published on structural weaknesses within flip chip BGAs. Structural failures within small multichip PBGAs are examined with details of the failure modes which occur in practice. These failure modes are then associated with stresses determined by FEA sinulation. The failure analysis methods used to reveal the failures are also reviewed.

3B.3 SHORT AND LONG-TERM STABILITY PROBLEMS OF HALL PLATES IN PLASTIC PACKAGES—D. Manic and R.S. Popovic, Swiss Federal Institute of Technology, Lausanne, Switzerland

Stability of silicon Hall plate sensitivity (in SOP and TSSOP packages) is studied. A parametric shift is observed when reflow soldering, temperature cycling or humidity testing are performed which is a reliability concern for Hall devices. Moreover, this shift is not stable over time and is correlated to a similar shift in package-induced stress.

3B.4 IMPROVED RELIABILITY PREDICTION THROUGH REDUCED-STRESS TEMPERATURE CYCLING—A.R. Cory, LSI Logic, Fort Collins, CO

With the Coffin-Manson equation as a model, reliably packaged devices are shown to be unreasonably sensitive to commonly accepted temperature cycling criteria. For example, an unlikely product failure mechanism in Condition C temperature cycling masks a common field failure mechanism. A case is presented for replacing conventional stress criteria with conditions designed to detect meaningful failure mechanisms.

COMPOUND SEMICONDUCTORS (Sess. 3C, Regency Ballroom) (following 3B and in parallel with 3A)

Co-Chairs: Fausto Fantini, University of Modena
J.J. Liou, University of Central Florida

3C.1 TRENDS IN SiGe BiCMOS PROCESS INTEGRATION—J. Dunn, D. Harame, S. St. Onge, A. Joseph, N. Feilchenfeld, K. Watson, S. Subbanna, G. Freeman, S.H. Voldman, and R. Johnson, IBM MicroElectronics

A new base-after-gate integration scheme has been developed for a 0.24 µm SiGe BiCMOS. The details of the approach which decouple the Heterojunction Bipolar Transistor from the CMOS thermal cycles while maintaining device performance are discussed. The reliability aspects associated with using SiGe for applications with high collector-base voltage with high emitter current are explored. Finally, the ESD characteristics of the SiGe BiCMOS technology elements are summarized.

3C.2 PULSED MEASUREMENTS AND CIRCUIT MODELING OF A NEW BREAKDOWN MECHANISM OF MESFETs AND HEMTS—E. Zanoni, G. Meneghesso, D. Buttari, M. Maretto, and G. Giovanni, Università di Padova, Padova, Italy

The on-state breakdown characteristics of HMETs were measured in a non-destructive way by using the transmission line pulsing technique. Based on the experimental observations, we developed a new model, which is suitable for SPICE simulation to predict the on-state breakdown of HMETs.

3C.3 BIAS AND TEMPERATURE STRESS RELIABILITY OF

InGaP/GaAs HBTs—A.A. Rezazadeh, S.A. Bashar, H. Sheng, F.A. Amin, King's College, London, UK, L. Cattani, Universita di Parma, Parma, Italy, and J.J. Liou, University of Central Florida, Orlando, FL
The reliability of InGaP/GaAs HBTs with different base metal contact systems under current and temperature stress is studied in this paper. We further report the effects of different base dopants and isolation implantation ions on the stability of HBT dc current gain.

3C.4 BREAKDOWN AND DEGRADATION ISSUES AND THE CHOICE OF A SAFE LOAD LINE FOR POWER HFET OPERATION—D. Dieci, R. Menozzi*, T. Tomasi, G. Sozzi*, C. Lanzieri**, and C. Canali, University of Modena, Modena, Italy *Università di Parma, Parma Italy **Alenia Marconi Systems, Roma, Italy

This work shows experimental data of hot electron degradation of power AlGaAs/GaAs HFETs. Based on the data, general indications on the bias point dependence of the device degradation, the choice of a safe load line for RF applications, and the breakdown voltage are presented.

3C.5 RELIABILITY OF OPTICAL FIBER BRAGG GRATING SENSORS AT ELEVATED TEMPERATURE—U. Sennhauser, A. Frank, P. Mauron, and P.M. Nellen, EMPA, Dubendorf, Switzerland

Reliability of fibers and Bragg gratings at elevated temperature up to 250 °C are modeled and their parameters are determined. Stress corrosion and grating decay are investigated for two commercially available Bragg grating types, and their temperature dependence on the operating conditions are analyzed.

Wednesday, April 12, 2:00 p.m., Parallel Session 4A & 4B

ELECTROSTATIC DISCHARGE
(Sess. 4A, Imperial Ballroom)

Co-Chairs: Charvaka Duvvury, Texas Instruments Inc.
Robert J. Gauthier, IBM

4A.1 (ESREF INVITED) HBM AND TLP ESD ROBUSTNESS IN SMART POWER PROTECTION STRUCTURES—G. Meneghesso, L. Volpato, A. Buson, S. Santirosi*, E. Novarini*, C. Contiero*, E. Zanoni, Università di Padova, Padova, Italy *STMicroelectronics, Milano, Italy

In this paper we will present data concerning the ESD robustness of smart power protection structures (BCD technology) for input-output circuits. A comparison between the robustness of p-body and p-well based structures and a study of the influence of layout parameters on the ESD robustness will be given. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will also be presented.

4A.2 ANALYSIS OF OXIDE BREAKDOWN MECHANISM OCCURRING DURING ESD PULSES—C. Leroux, P. Andreucci, and G. Reimbold, LETI-CEA, Grenoble, France

The oxide tolerance and failure modes under ESD-like short duration high current density pulses are investigated by taking into account the three effects of charge to breakdown, thermal breakdown, and current crowding effects. Due to current crowding, F-N model and the 1/E model cannot be used to predict the failure threshold of thin oxide under ESD.

4A.3 MICROANALYSIS OF VLSI INTERCONNECT FAILURE MODES UNDER SHORT-PULSE STRESS CONDITIONS—K. Banerjee, D.-Y. Kim, Stanford University, Stanford, CA, A. Amerasekera, Texas Instruments, Inc., Dallas, TX, C. Hu, University of California, Berkeley, CA, S.S. Wong and K.E. Goodson, Stanford University, Stanford, CA

This work presents a detailed microanalysis of interconnect failure mechanisms under short-pulse stress conditions arising during peak current and ESD events. A thermo-mechanical model is formulated for the open circuit failure mode and direct evidence of latent interconnect damage is reported. Suitable design guidelines are proposed to avoid this latent damage.

4A.4 TRANSMISSION LINE MODEL TESTING OF TOP-GATE AMORPHOUS SILICON THIN-FILM TRANSISTORS—N. Tosic, F.G. Kuper*, and T. Mouthaan, University of Twente, The Netherlands *also Philips Semiconductors, Nijmegen, The Netherlands

In this paper, Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (µ-Si:H TFT). Above ESD failure threshold voltage of degradation, either deterioration of electrical characteristics sets in or voltage dielectric breakdown occurs. Simulations were used to confirm the deterioration process which was experimentally found to be due to creation of positive interface charges.

4A.5 PROCESS AND LAYOUT DEPENDENT SUBSTRATE RESISTANCE MODELING FOR DEEP SUB-MICRON ESD PROTECTION DEVICES—X.Y. Zhang, K. Banerjee, Stanford University, Stanford, CA, A. Amerasekera, Texas Instruments Inc., Dallas, TX, Z. Yu, and R.W. Dutton, Stanford University, Stanford, CA

A new methodology for analyzing and predicting the impact of layout and process variations on the effective substrate resistance of deep sub-micro ESD devices is demonstrated using quasi mixed-mode approach. The substrate resistance which is important for ESD design, simulated by this method shows good agreement with experimental data.

4A.6 SIMULATION AND EXPERIMENTAL STUDY OF TEMPERATURE DISTRIBUTION DURING ESD STRESS IN SMART-POWER TECHNOLOGY ESD PROTECTION STRUCTURES—K. Esmark, C. Fürböck*, H. Gossner, G. Groos, M. Litzenberger*, D. Pogany*, R. Zelsacher**, M. Stecher, and E. Gornik*, Infineon Technologies, Munich, Germany *Vienna University of Technology, Vienna, Austria **Infineon Technologies, Villach, Austria

Electro-thermal simulation and laser-interferometry thermal mapping are performed to study temperature distribution in smart power technology electrostatic discharge (ESD) protection npn transistors. Simulations utilizing improved model calibration predict two separate hot spots due to vertical and lateral current paths in the base region. The location of hot spots, their temperature evolution, and dependence on stress level agree well with experiments.

4A.7 ELECTROSTATIC DISCHARGE AND HIGH CURRENT PULSE CHARACTERIZATION OF EPITAXIAL BASE SILICON-GERMANIUM HETEROJUNCTION BIPOLARE TRANSISTORS—S.H. VoIdman, P. Juliano*, R. Johnson, N. Schmidt, A. Joseph, S. Furkay, E. Rosenbaum*, J. Dunn, D. Harame, IBM MicroElectronics, Essex Junction, VT and B. Meyersor, IBM Watson Research, Yorktown Heights, NY *University of Illinois at Champaign-Urbana, IL

ESD robustness of SiGe HBT devices are investigated for the first time. High current characterization using transmission line pulse methods and Wunch-Bell power-to-failure curve analysis on the epitaxial graded-Ge base devices show higher failure current levels compared to Si homojunction BJT devices and this is supported by the relatively higher failure thresholds from HBM stress data.

INTERCONNECTS (Session 4B, Regency Ballroom)

Co-Chairs: J. Joseph Clement, Sandia National Laboratories
James R. Lloyd, JPL

4B.1 THE ROLE OF COPPER IN ELECTROMIGRATION: PROPERLY ACCOUNTING FOR A Cu-VACANCY BINDING ENERGY—M.J. Tammaro, University of Rhode Island, Kingston, RI

The precise role of copper in extending electromigration lifetimes in Al-Cu interconnects is still not well understood. A model based on microscopic diffusion kinetics is proposed that reproduces all of the relevant features of experiments. A novel analysis based on rate equations for atomic pair probabilities is developed.

4B.2 ELECTROMIGRATION LIFETIME ENHANCEMENT FOR LIFETIMES WITH MULTIPLE BRANCHES—M.J. Dion, Intersil Corp., Melbourne, Fl.

With clock or power supply interconnect "trees", there is often a very high current "trunk" feeding current to multiple branches. This work demonstrates increased trunk lifetime with increasing number of branches, which terminate at via plugs. Comparative Black's model parameters are developed and failure analysis is described. Implications for electromigration design rules are discussed.

4B.3 EFFECT OF Ti INSERTION BETWEEN Cu AND TiN LAYERS ON ELECTROMIGRATION RELIABILITY IN Cu/(Ti)/TiN/Ti LAYERED DAMASCENE INTERCONNECTS—K. Abe, S. Tokitoh, S.C. Chen, J. Kanamori, and H. Onoda, OKI Electric Industry Co., Ltd., Tokyo, Japan

It is important to control the Cu/barrier interface, since it can be the dominant diffusion path for electromigration. This work demonstrates superior electromigration performance can be achieved by inserting a thin Ti layer between Cu and the TiN barrier layer. This improvement is associated with Cu-Ti compound formation, not only at the Cu/barrier interface, but also in the Cu grain boundary.

4B.4 TDDB IMPROVEMENT IN Cu METALLIZATION UNDER BIAS STRESS—J. Noguchi, N. Ohashi, J. Yasuda, T. Jimbo, H. Yamaguchi, N. Owada, K. Takeda, and K. Hinode, Hitachi, Ltd., Tokyo, Japan

Time-dependent dielectric breakdown (TDDB) between Cu interconnects depends strongly on the surface condition of the Cu interconnect and the surrounding dielectrics. An NH3-plasma treatment prior to cappSiN deposition improves TDDB lifetime. This is shown to reduce CuO and to introduce a nitridation layer on the Cu surface, which prevents Cu-silicide formation at the interface.

4B.5 CONDUCTION PROCESSES IN Cu/LOW-k INTERCONNECTION—G. Bersuker, V. Blaschke, S. Choi, and D. Wick, SEMATECH, Austin, TX

Electrical characterization of leakage currents in damascene Cu/low-k structures was performed. Ionic conduction due to contamination inherent to the dielectric was found to be the leading cause of intrinsic intra-metal line leakage at low temperatures, while at elevated temperatures a contribution from electron current was detected. Dielectric and barrier layer parameters that control the conduction process were evaluated.

4B.6 LEAKAGE AND BREAKDOWN RELIABILITY ISSUES ASSOCIATED WITH LOW-k DIELECTRICS IN A DUAL-DAMASCENE Cu PROCESS— R.Tsu, J. McPherson, and R. McKee, Texas Instruments, Inc., Dallas, TX

Leakage and breakdown characteristics of low-k dielectrics are becoming critically important reliability issues for interconnects scaled to 0.18 µm and beyond. TDDB is a significant concern for breakdown strengths of < 2 MV/cm. Cu out-diffusion through the barrier confinement and moisture absorption are shown to greatly exacerbate the low-k TDDB issue.

4B.7 QUANTITATIVE PROJECTIONS OF RELIABILITY AND PERFORMANCE FOR LOW-k/Cu INTERCONNECT SYSTEMS—K. Banerjee, Stanford Univ., Stanford, CA, A. Mehrotra, Univ. of Illinois, Urbana-Champaign, IL, W.R. Hunter, Texas Instruments, Dallas, TX, K.C. Saraswat, S.S. Wong, Stanford Univ., Stanford, CA

A methodology for quantitative analysis of the role of electromigration and performance in determining optimal interconnect design is presented. This methodology is applied to various low-k/Cu interconnect systems. It is demonstrated that electromigration design limits for signal lines are automatically satisfied, when the interconnect performance is optimized.

4B.8 EXPERIMENTAL DATA AND STATISTICAL MODELS FOR BIMODAL EM FAILURES—A.H. Fischer, Infineon Technologies, München, Germany, A. Abel, Technical University Dresden, Dresden, Germany, M. Lepper, and A.E. Zitzelsberger, Infineon Technologies, München, Germany

Electromigration (EM) failure times are usually fit by asignal log-normal distribution. But, in some cases relevant deviations are observed. We discuss two types of non log-normal distributions, observed on via-line structures. They can be modeled by two types of bimodal distributions, each composed of two log-normal distributions. Both models consider different failure mechanisms within the sample. We will present experimental data sets coinciding with either model. The physical failure analysis confirms the model assumptions and supports the bimodal distribution concept.

Wednesday, April 12, 7:00-8:00 p.m., Ballroom Pre-function Area

BANQUET RECEPTION

Wednesday, April 12, 8:00 p.m., Regency Ballroom

SYMPOSIUM BANQUET

A no-host reception prior to the Banquet will run from 7:00 p.m. to 8:00 p.m. in the Ballroom foyer. Awards for 1999 IRPS Best and Outstanding Papers will be presented immediately following dinner. Registered attendees for the Symposium will receive one ticket for admission to the banquet. Additional tickets may be purchased at the Registration Desk for $25.

Thursday, April 13, 8:15 a.m, Imperial Ballroom

PROCESS INDUCED DAMAGE (Session 5)

Co-Chairs: Terence B. Hook, IBM Microelectronics
Paul E. Nicollian, Texas Instruments Inc.

5.1 A MODEL FOR EVALUATING CUMULATIVE OXIDE DAMAGE FROM MULTIPLE PLASMA PROCESSES—K. Noguchi, A. Matsumoto, and N. Oda, NEC Corp., Sagamihara, Kanagawa, Japan

A model for evaluating cumulative oxide damage caused by multiple plasma processes is proposed. By considering a sub-linear dependence of the charging current on the antenna ratio, damage of a device with various antenna configurations is estimated. A modified antenna rule is proposed, and a realistic design guideline is obtained.

5.2 ON-CHIP PROBES FOR SILICON DEFECTIVITY RANKING AND MAPPING—A. Zanchi, F. Zappa, M. Ghioni, Politecnico di Milano, Milano, Italy, and A.P. Morrison, University College Cork, Cork, Ireland

On-wafer probes capable of localizing lattice defects in silicon are described. These probes are based on single-photon avalanche diodes that sense the defect-induced thermal generation of single carriers within the junction. These probes give suitable figures of merit for ranking the overall defectivity and mapping the spatial variation.

5.3 DETECTION OF THIN OXIDE (3.5 nm) DIELECTRIC DEGRADATION DUE TO CHARGING DAMAGE BY RAPID-RAMP BREAKDOWN—T.B. Hook, D. Harmon, IBM MicroElectronics, Essex Junction, VT, and C. Lin, Infineon Microelectronics, Hopewell Junction, NY

For thin dielectrics (<4.0 nm) it is difficult to detect charging damage, the traditional techniques of Fowler-Nordheim or hot-carrier stressing no longer being adequately sensitive, and leakage measurements being confounded by tunneling current and also requiring very high resolution. In this paper we propose rapid ramp breakdown as a practical and quantitative method of characterizing the impact of charging damage.

5.4 CHARGE PUMPING TECHNIQUE FOR THE EVALUATION OF PLASMA INDUCED EDGE DAMAGE IN SHALLOW S/D EXTENSION THIN GATE OXIDE nMOSFETs—S.S. Chung, S. J. Chen, H. L. Kao, S. J. Luo, National Chiao Tung University, Taiwan, R.O.C., and H.C. Lin, Nano Device Lab., Taiwan, R.O.C.

Plasma etching of polysilicon during the gate definition induces the so-called plasma edge damage at the edge of the gate. This damage has been verified on test patterns with various shapes and areas, and is shown to exacerbate the device degradation after hot-electron stress. Results from a charge-pumping analysis show that interface traps are the dominant mechanism of the degradation in drain current from the plasma-induced edge damage. Application of this techique to antenna effect studies is demonstrated.

OXIDE PANEL (Imperial Ballroom)

Is technology scaling limited by oxide reliability?

Panel:

  • Joe McPherson, Texas Instruments
  • David Dumin, Clemson University
  • Chenming Hu, UC Berkeley
  • Eric Vogel, NIST
  • John Suehle, NIST
  • William Abadeer, IBM MicroElectronics
  • Bonnie Weir, Lucent Technologies
  • Robin Degraeve, IMEC
  • Scott A. Hareland, Intel Corporation

Moderators:

  • William R. Tonti, IBM MicroElectronics
  • Tony Oates, Lucent Bell Labs

Thursday, April 13, 2:00 p.m., Imperial Ballroom

FAILURE ANALYSIS (Session 6)

Co-Chairs: Daniel Barton, Sandia National Laboratories
Jacob Phang, National University of Singapore

6.1 QUANTITATIVE THERMAL PROBING OF DEVICES AT SUB-100 nm RESOLUTION—L. Shi, O. Kwon, G. Wu, A. Majumdar, University of California, Berkeley, CA

The paper reports the use of a micromachined scanning thermal probe for quantitatively probing semiconductor devices with sub-100 nm spatial resolution. The thermal design of the probe was optimized to improve accuracy in temperature measurement and spatial resolution. Temperature distributions on different submicron and subsurface VLSI via structures were measured.

6.2 ELECTRICAL PROBING OF DEEP SUB-MICRON ICS USING SCANNING PROBES—K. Krieg, R. Qi, Micron Force Instruments, D. Thomson and G. Bridges, University of Manitoba, Canada and Micron Force Instruments

A contact probing system is presented that fits on a standard probe-station and utilizes a conductive atomic force microscope tip to rapidly measure the surface topography and acquire real-time high-frequency signals from features as small as 0.18 µm. The probe achieves a bandwidth greater than 3 GHz.

6.3 A STUDY OF IMPLANT-INDUCED THIN OXIDE FILM EXPANSION DURING DRY PHOTORESIST ETCHING,—K. P. Lin, K.M. Ching, K.-S. Huang, and S.-L. Hsu, Taiwan Semiconductor Manufacturing Company Ltd., Taiwan

Bubble-like protrusion defects were found in source and drain areas after stripping the implant mask photoresist. Stress voiding from vacancies created by these defects beside metal interconnections can cause a severe reliability issue. This case study focuses on the identification of the root cause behind the formation of the protrusions. Methods to prevent void formation are also discussed.

6.4 RELIABILITY ASSESSMENT BY DEFECT BASED TESTING—B. Lisenker and Y. Mitnick, Intel, Haifa, Israel

This paper introduces a new fault model that represents deep-sub-micron CMOS ULSI circuits in standby mode as a single effective MOSFET. It is shown that normal units can be separated from defective ones by means of measuring ISB current versus VCC. Product data shows that 0.25 µm process creates defects that have four types of behavior. A strong correlation between rejected devices and early failure rate is demonstrated.

6.5 LOCALIZING POWER TO GROUND SHORTS IN A CHIPS-FIRST MCM BY SCANNING SQUID MICROSCOPY — E. Vanderlinde, M.E. Cheney, E.B. McDaniel, and K.L. Skinner, Microelectronics Research Laboratory, Columbia, MD, L.A. Knauss, B.M. Frazier, and H.M. Christend, Neocera, Inc., Beltsville, MD

A novel technique called scanning SQUID microscopy was used to locate power-to-ground shorts in a copper/polyimide chips-first MCM. Other F/A techniques were unsuccessful in locating the shorts, but the magnetic current imaging quickly found the defects. Mechanical cross-sections through the part showed shorted metal from a process defect.

6.6 SINGLE CONTACT OPTICAL BEAM INDUCED CURRENTS (SCOBIC) - A NEW FAILURE ANALYSIS TECHNIQUE—J.M. Chin, J.C.H. Phang, D.S.H. Chan, National University of Singapore, and C.E. Soh, AMD, Singapore

The Single Contact Optical Beam Induced Currents (SCOBIC) is a new failure analysis technique. By connecting the substrate or power pins of an integrated circuit to the amplifier, many junctions can be imaged. In contrast, in the OBIC technique, only the junction directly connected to the current amplifier is imaged.