TUTORIAL PROGRAM

Chair: Edward I. Cole, Jr. Sandia National Laboratories

Vice Chair: Thomas M. Moore, Texas Instruments

The 2000 IRPS Tutorials Program offers attendees the opportunity for focused instruction in core topics as well as emerging areas of interest in reliability physics. For those who are new to the field of reliability, the Tutorials Program provides an excellent background and preparation for the symposium by learning from the experts. Experienced engineers benefit from hearing of new developments, exchanging technical viewpoints, and broadening of their technical skills.

Core topics for 2000 include gate oxide reliability, hot carrier fundamentals, and product reliability qualification. In response to last year's survey feedback, a set of 4 tutorials dealing with different reliability aspects of Cu metallizaiton and low dielectric constant materials is a major theme for this year. In addition to these topics, focused ion beam basics and developments, design for safety-critical applications, challenges in packaging and assembly, and wet etches for failure analysis are available for participants.

The Tutorial Program is a great value for IRPS attendees and far more economical than bringing experts to your location. With you registration you will receive a copy of the Tutorial Notes which includes the abstracts and viewgraphs of all the offered courses (over 20 hours of reference material!). To facilitate meeting room planning your are encouraged to register early and indicate your intended attendance choices on the registration card.

Monday April 10, 2000

Topic 1. Thin Gate Oxide Reliability: Past and Present Trends in Characterization, Physical Modeling, and Assessment - J.S. Suehle and E.M. Vogel, NIST, Gaithersburg, MD (8:00 a.m. - 11:30 a.m., Imperial Ballroom)

The reliability of gate oxides has become a critical concern as oxide thickness is scaled below 3 nm in advanced technologies. It has been proposed that the fundamental limit to further device scaling is the intrinsic reliability of the gate dielectric. An overview of past and present thin oxide reliability characterization techniques and wear-out physics will be presented. A special emphasis will be placed on issues relating to the characterizing and understanding of breakdown in current technology ultra-thin gate oxides where excessive tunneling currents and soft breakdown complicate reliability assessment.

Topic 2. Low-Dielectric Constant Materials for Cu Interconnects - K. Taylor, Texas Instruments, Dallas TX (8:00 a.m. - 9:30 a.m., Regency Ballroom I)

The demands of lower power consumption, faster speed, and reduced crosstalk continue to pressure semiconductor companies to replace SiO₂ with a low-dielectric-constant material as the intermetal dielectric. An overview is given of low-dielectric-constant materials and several ways of being incorporated into copper-based metallization schemes. This will include various methods of deposition as well as subsequent physical and electrical characterization. This course would be suitable for technologists who have limited experience in working with low-dielectric-constant materials but have strong traditional backgrounds in CVD/SOG/PVD dielectric and metallization technology.

Topic 3. Reliability Considerations for Cu Metallization Systems for ULSI Circuits, T.D. Sullivan and A.K. Stamper, IBM Microelectronics, Essex Junction, VT (10:00 a.m. - 11:30 a.m., Regency Ballroom I)

The drive toward smaller, faster microelectronics chips is requiring use of Cu and low-K dielectrics in place of present Al/SiO₂ wiring systems in order to reduce RC signal delay. Cu addresses the resistive component of this delay. Besides having 30% lower resistivity and a higher elastic modulus compared to Al, Cu is a relatively low-cost replacement. But Cu behaves differently from Al in several ways. Cu is not self-passivating like Al, and has been found to diffuse through oxide. Diffusion barriers must therefore be used around Cu lines to protect active devices from Cu poisoning. Because Cu oxidizes easily, wiring and bond pads must be protected from air during high-temperature testing. Cu adhesion to SiO₂ appears to be poorer and Cu interfacial diffusion higher, allowing for significant electrochemical migration and a different dependence of electromigration lifetime on linewidth than that seen with Al. For electromigration and stress voiding, Cu is generally more robust than Al. However, fabrication details can substantially modulate this behavior if not carefully controlled. Introduction of low-K dielectrics, anticipated to address the capacitive component of signal delay, will present additional challenges for both integration and reliability, because most low-K materials have lower mechanical strength, lower thermal conductivity, and are more permeable than SiO₂.

Topic 4. HOT CARRIER RELIABILITY FUNDAMENTALS IN LOGIC AND MEMORY TECHNOLOGY- P. Fang, AMD, Sunnyvale, CA (8:00 a.m. - 9:30 a.m., Crystal Room)

The fundamentals of the hot carrier effects for both logic and flash memory technologies will be reviewed and discussed in this tutorial. The temperature effects for low sub-1.5 Vcc operation and different gate oxide nitridation and D2 anneals on hot carrier reliability will be presented. The DC-AC hot carrier lifetime projection methodology and the criteria evolution are also highlighted. The basic flash memory operation configurations and respective reliability concerns will be introduced.

Topic 5. ASIC Design for Safety-Critical Applications-T. Ambler, University of Texas Austin, Austin Texas (10:00 a.m. - 11:30 a.m., Crystal Room)

The requirement for highly reliable integrated circuits in safety-critical applications is increasing. The transportation industry, for example, uses increasing amounts of electronic control in life-critical situations, the nuclear industry uses electronics in reactor protection systems. This presentation will discuss the problems and some of the solutions to the difficulties posed in attaining verifiably high reliability in modern integrated circuit design.

Topic 6. Focused Ion Beam Technology and Applications to Microelectronics - M.T. Abramo, IBM Microelectronics, Burlington, VT and A.N. Campbell, Sandia National Laboratories, Albuquerque, NM (8:00 a.m. - 11:30 a.m., Regency Ballroom II)

During the past decade, focused ion beam (FIB) systems have become indispensable tools in the arsenal of analytical techniques available to failure analysts and IC designers. FIB systems are similar to scanning electron microscopes (SEM) in that a charged particle beam is generated, raster-scanned, and used for high resolution imaging. In addition, the use of massive Ga ions permits the FIB system to be used for both material removal (milling) and deposition, enabling applications such as precision cross sectioning and chip repair. This tutorial will explore the fundamentals of FIB system operation, describe a wide range of applications, and discuss FIB approaches for chip repair and failure analysis from the back side of the chip. The effects of FIB exposure on transistor parameters and the reliability of FIB-modified ICs will also be discussed.

Topic 7. Wet Etches for Silicon Semiconductor Failure Analysis - T.W. Lee, Varian, Tempe, AZ (1:30 p.m. - 3:00 p.m., Regency Ballroom II)

Wet etches are required in FA for the selective removal, delineation by decoration or differential etching and identification of damage or defects in layers of various materials. Many etch recipes have been formulated to address specific manufacturing tasks. This tutorial contains the results of a literature search on etches such as Dash, Sirtl, Wright and 25 others. Classical and named wet etches are described according to general type and applicability to FA with a ternary diagram, 3-D surface, and spreadsheets. The work of the original researchers is identified in an extensive list of references.

Topic 8. Analytical Challenges in Packaging and Assembly _ G. Samuelson, R. Dias, D. Goyal, S. Tandon, Intel, Chandler, AZ, T.M. Moore, C. Hartfield, Texas Instruments, Dallas, TX (3:30 p.m. - 5:00 p.m., Regency Ballroom II)

The challenges in assembly analytical tool/technique development are in the areas of nondestructive imaging, board level fault isolation and materials property measurement. This tutorial will deal with tools/techniques in each of these major areas. The pros and cons of state of the art analytical capabilities will be discussed along with likely future directions. Finally, major obstacles to evolution of existing technologies will be highlighted urging industry participation to engage multiple industry/academic partners for development of breakthrough technology roadmaps.

Topic 9. ANALYSIS OF Cu WITH VARIOUS LOW K DIELECTRIC MATERIALS TO DETERMINE A VIABLE Cu-LOW K DIELECTRIC CANDIDATE FOR ADVANCED INTERCONNECT TECHNOLOGY _ S.U. Kim, Consultant, Rio Rancho, NM (1:30 p.m. - 3:00 p.m., Regency Ballroom I)

This tutorial focuses on analysis and characterization techniques to determine the new failure mechanisms for the Cu-low k system. It includes inter- and intra-Cu line to line leakage current using a new test structure design, thermal stability and B-T (bias-temperature) stress methodology, identification of Cu damascene process induced defect, root cause analysis techniques, high frequency (GHZ) dependent dielectric degradation such as fatigue, hysteresis, and polarization, and carrier conduction and failure mechanisms. The tutorial material is based on the work performed at SEMATECH and UT, Austin on Cu with various low k dielectric combinations to determine a viable Cu-low k dielectric candidate for advanced ULSI interconnect technology. Data on Cu-low k process induced defects, impact of such defect on thermal stability and B-T stress failure, and new carrier conduction failure mechanisms will be presented and discussed.

Topic 10. Thermal Deformation and Interfacial Adhesion in Area-Array Packages for Cu/Low-k Chips - P. S. Ho, University of Texas (3:30 p.m. - 5:00 p.m., Regency Ballroom I)

This presentation will first discuss the thermal deformation behavior in high-density area-array packages with an underfilled flip-chip configuration. The effect of replacing Al oxide interconnects with Cu low k interconnects on packaging reliability will be discussed, emphasizing the difference in thermomechanical properties between oxide and low k materials. Interfacial adhesion has emerged to become a critical concern for packaging reliability. The measurement of adhesion and its impact on reliability will be discussed.

Topic 11. PRODUCT RELIABILITY ASSESSMENT AND QUALIFICATION METHODOLOGIES: CURRENT PRACTICES AND FUTURE TRENDS - N.E. Lycoudes, Motorola Semiconductor Products Sector, Chandler, AZ (1:30 p.m. - 5:00 p.m., Imperial Ballroom)

Product Reliability Assessment and Qualification methodologies such as Stress Test Driven, Process Based etc. are reviewed with respect to their current usage and a brief historical perspective is given. New industry proposals such as Application Specific, Use Condition Based, Knowledge Based, Innovation Process Based, Virtual Qualification etc. are reviewed and related to current practices. It is emphasized that in all cases the objective of Reliability Assessment and Qualification is the identification and estimation of the probability of occurrence of potential failure mechanisms during the life of the product under normal use conditions. An existing challenge is restated that NO PRODUCT QUALIFICATION IS NEEDED if the product potential failure mechanisms and their probabilities of occurrence are known. Examples of such cases will be given. The evolution of alternative Reliability Assessment and Qualification methodologies (future trends) are examined within the framework of industry current practices and new proposals.