Overhead projectors will be available in the meeting rooms. Please note that the workshops will be held on Monday evening after the tutorials. Please register for the workshop of your choice either on-line , use the form below, or alternately when you register at the conference. Topics and sign-up forms are listed below. For further information on the workshop program contact either Arthur Rawers or Marsha Abramo. 

Workshop 1: New Packages Technologies 

Advanced semiconductor packaging solutions continue to evolve and to satisfy the variety of reliability and performance requirements, new materials are developed and traditional materials are pushed to performance limits. Come and discuss the challenges you are facing in this complex field. Topics sure to be addressed are delamination and cracking, inter-level dielectric performance issues, solder joint reliability assessment strategies, thermal performance of materials, new material applications, etc. 

Workshop 2: Focused Ion Beam 

The FIB workshop brings together FIB practitioners to share their experience and those who are new to the field and want to become familiar with the diverse aspects of FIB techniques. 

Topics to be discussed include, but are not limited to, the challenges of high aspect ratio contact hole preparation and filling, back side device processing, the challenge of coping with metal fill patterns, design for repairability, is there reliability in FIB micro surgery?, CAD layout overlay, repair site navigation on deep submicron ICs. 

Workshop 3: Standards for Product Qualification 

This workshop will discuss the practices for product Qualification and address the related topic of product reliability screening tests. There are a variety of qualification methods, specifications and requirements that exist in our industry today. Which are the best ones? Which methods are more effective than others.? How does product reliability assessment differ from qualification testing? Come here what others have to say or come and express your opinion about your favorite tests. 

Workshop 4: Dielectrics 

Planning and execution for dielectric reliability data requires a discipline to ensure timely and meaningful information. It is a labor and time intensive effort in which, perhaps, one gets only one chance to make it work, and there is never enough time. This workshop will concentrate on these issues as they relate to: processing conditions, model for voltage (or field) and temperature, area dependence, process/device layout sensitivities (area vs perimeter, etc.), and DC vs transient conditions. Discussions will address topics like planning for dielectric data acquisition, advice on methods to analyze the data for maximum information, and how to handle potential conclusions based on available data. 

Workshop 5: Hot Carriers 

Hot Carrier (HC) reliability requirements are starting to become a limiting factor for the development of deep submicron technologies (< 0.25 nm). Global HC reliability rules, extensively used in the past, are starting to impact the performance/reliability tradeoffs to not acceptable levels . It is becoming more and more important to carefully quantify the link between DC HC studies and circuit reliability/performance requirements. This workshop will focus on possible methodologies to quantify circuit level reliability at very early stage in the technology development cycle. The main discussion will be on existing software tools to allow HC reliability by design, their limits and future developments to satisfy the needs of both reliability and circuit design. New stress/test methodologies to optimize and calibrate the reliability projections by simulation will be also covered. 

Workshop 6: ESD/Latchup for High Performance CMOS 

ESD continues to be a major reliability threat as technologies advance further into the deep submicron regime and IC designs get more complex. This workshop will address the latest concerns for ESD including: 1) core damage, 2) new latchup issues and the tradeoff with ESD, 3) new packaging and processes, 4) building-in ESD reliability, 5) mixed voltage circuits, 6) Charged Device Model, 7) oxide reliability and charge trapping, 8) simulation and modeling efforts to solve ESD, 8) ESD testing standards, and 9) any other topics of interest to the audience. 

Workshop 7: Failure Analysis 

This highly popular workshop will focus on recent developments in the field of failure analysis. A discussion of techniques orientated at the analysis of current and next generation processes will focus on methods of fault localization and isolation. The challenges of flip chip and back-side techniques could also be addressed. Its all up to those who attend and the discussions that evolve. Attendees are encouraged to prepare questions and presentation material on those issues that they would like to discuss in detail. 

The Wafer Level Reliability workshop will discuss the status and accomplishments of various WLR standards and the progress of investigations being performed by committees. The recent work of JEDEC Committee on WLR, JC14.2 will be summarized as well as related WRL activities in our industry. Attendee's are encouraged to bring to the workshop their recent experiences and any related questions regarding test techniques, methods or standards. The workshop draws together a mixed group ranging from expert to novice which provides for an excellent exchange of various topics related to WLR. 

Workshop 9: Interconnects/Copper/Low-K 

Do you know how to answer your metallization reliability questions? What about the new Cu-base systems that are right around the corner? These are changing times with new materials, challenges and questions. At a time where development cycle time and performance dominate process development, knowing the right test and what to do with the results is crucial. Please join a group of development and production engineers like yourself and share your views on testing Al or Cu-based systems. Because of the importance of Low-K dielectrics on Cu based systems, the performance effects of this material has been added to the discussion list. Topics will include, but are not limited to Electromigaiton, Stress Voiding, Defect Detection and Control, Corrosion, Low-K material performance, etc. 

Workshop 10: MEMS 

MEMs reliability today is where semiconductor reliability was before we had activation energy concepts and accelerated life procedures using elevated temperatures. Another year has passed and we have new developments and more empirical data. What have we learned? Are our models coming closer to explaining intrinsic characteristics or are we still in the phenomenological theory phase of our understanding? Come and discuss what you have experienced this past year with your colleagues. Listen to what others have to say about their recent work and discuss what's been going on in the laboratory or what you have been reading in publications.