Michael J. Dion received the B.S. in electrical engineering with high honors from the University of Florida (1980) and joined Harris Semiconductor, Melbourne, FL., as a reliability engineer. During his time at Harris he has held various reliability engineering and supervisory positions and received the M.S. in electrical engineering (1988) from the University of FL. Starting in 1987 he was involved in wafer-level reliability methodology development and has been active with the JEDEC 14.2 Committee on Wafer-Level Reliability. In 1990 he was assigned by Harris to SEMATECH as a reliability physicist and accepted his current role as JEDEC 14.2 Chair in 1992. Upon return to Harris in 1993 he focused on process reliability and process control assurance. Since 1997 he has specialized on metal process reliability characterization. In 1999 he joined Intersil Corp. with continued focus on metal process reliability characterization.