submitted by Andrew J Spencer (andrew.j.spencer@marconi.com)
on Tuesday, April 17, 2001 at 05:54:23
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For Workshop 4

 I am particularly interested in the application of failure 
analysis techniques on 3-5 semiconductor devices including 
GaAs and InP. Some fundemental siliocn techniques can be
difficult to apply, such as Jet Etch where GaAs may be 
dissolved from the scribeline edges where exposed to decap 
acids. Gold metallization can be difficult to remove without
damage to the semiconductor. 
Any solutions? Also, is photoemission a meaningful technique
for GaAs or InP where normal reverse biassed junctions might
emit infrared light?