Overhead projectors will be available in the meeting rooms. Please note that the workshops will be held on Wednesday evening.

Workshop 1: FIB User's Group
Facilitator: Fred Stevie, Lucent (stevie@agere.com )   

The FIB workshop brings together FIB practitioners to share their experience and those who are new to the field and want to become familiar with the diverse aspects of FIB techniques. Topics to be discussed may include, but are not limited to, the challenges of design for reparability, sample preparation, FIB damage, copper challenges,voltage contrast, CAD layout overlay and repair site navigation on deep submicron ICs. Come and participate in discovering how the FIB is enhancing analysis time. Bring any questions, concerns, successes and challenges! 

Workshop 2: Dielectric Reliability  

What does the data mean? Planning and execution for dielectric reliability data requires a discipline to ensure timely and meaningful information. It is a labor and time intensive effort in which perhaps,one gets only one chance to make it work and there is never enough time. This workshop will concentrate on these issues as they relate to processing conditions, model for voltage (or field) and temperature, area dependence, process/device layout sensitivities (area vs perim-eter, etc.), and DC vs transient conditions. The workshop will address how to plan for dielectric data with the existing constraints, and how to analyze the data for maximum information, and what conclusions or actions you should take based on it. 

Workshop 3: Hot Carriers 
Facilitator: Ronald C. Lacoe, AERO, Org (Ronald.C.Lacoe@aero.org )  

Hot carriers reliability requirements continue to be an issue of concern as we embark on sub 0.15 µm geometries. Careful quantifi-cation of the link between DC HC studies and circuit reliability/performance is critical. The workshop will present possible methodologies to quantify circuit level reliability at very early stage in the technology development cycle. Attendees are encouraged to bring to discussion issues such as software tools to allow HC reliability by design, their limits and future developments to satisfy the need of both reliability and circuit design. 

Workshop 4: Failure Analysis 
Facilitator: Matt Thayer, AMD (matthew.thayer@amd.com )  

This workshop will focus on recent failure analysis technique developments and analysis. A discussion of techniques oriented at the analysis of current and next generation processes will focus on methods of fault localization and isolation. Analysis techniques suitable for fault localization through the substrate have become vital to the industry with the increasing use of multi-level metal processes and flip-chip packaging. Yield analysis techniques, tools and enhancements are adding to the Failure Analysis success and fault isolation. Feel free to bring questions, concerns and new ideas. 

Workshop 5: Interconnects/Copper/Low-K 
Facilitator: Jim Lloyd, IBM, Watson   

With the on set of speed and reliability within submicron technology this topic is becoming more popular. The times have changed and new materials and challenges are occurring. At a time where cycle time and performance dominate process development, knowing the right test and what to do with the results is crucial. Join this group in a discussion of development and production testing Al or Cu based systems and its integration with Low K dielectrics. Topics to discuss will include, but not be limited to electromigration, stress voiding, defect detection and control, corrosion, low-K material performance etc.  

Workshop 6: MEMS 
Facilitator: Susanne Arney, Lucent (arney@lucent.com )  

MEMS reliability continues to be a challenge as new developments and more empirical data availability continue. This workshop will be a great opportunity to share with your colleagues the recent advances in MEMS and how the MEMS growth is shaping.  

Workshop 7: Package  
Facilitator: Tom Moore, Texas Instruments (moore@ti.com )  
Facilitator: Jack McCullen, Intel Corporation (jack.t.mccullen@intel.com )  

Semiconductor packaging is being pushed to limits in terms of I/O and thermal requirements while keeping the size small. This poses a great challenge to the reliability engineers. This workshop will present an opportunity to look into what is all out there for various packages and what different packages and materials are available to meet the needs of high speed, miniaturized applications.  

Even though most manufacturing is automated, ESD damage to the devices can still plague the development of a product. With reducing voltage requirements, but multiple power supplies for ever needing mixed signal semiconductor devices, latch-up can be major concern. The workshop will focus on issues reliability and design engineers face in order to get a robust product out to customers. 

Workshop 9: Cooling Microelectronics 
Facilitator: Paul Boudreaux, Laboratory for Physical Sciences      (boudreau@eng.umd.edu)  
Facilitator: Donald Tilton, Isothermal Systems Research      (dtilton@spraycool.com )  
Facilitator: John W. Peeples, KryoTech (johnp@kryotech.com )  

Since the advent of VLSI microelectronics, there has been a steady demand for higher and higher performance with a concomitant heat load. This has placed an increasing burden on the thermal capabilities of microelectronic systems. New technological breakthroughs have greatly alleviated this thermal bottleneck and some of the liquid based cooling schemes will be described. They often have unique characteristics to add to the thermal design and control of microelectronics. A new thermal management paradigm is possible that greatly enhances the reliability while reducing the overall system size and weight. One of these is a liquid phase change technology allows the designer to minimize the maximum temperatures in a system while simultaneously eliminating most of the temperature gradients across components. Some example applications, which illustrate the remarkable characteristics of these technologies, along with many technical details will be discussed.