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VIRTUAL SYMPOSIUM |
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PRODUCT RELIABILITY I - Session 3D
COMPOUND SEMICONDUCTOR II Session 4A
DEVICE & PROCESS Session 4B
PRODUCT RELIABILITY II - Session 4C
INTERCONNECTS - Session 4D
PROCESS INDUCED DAMAGE - Session 5
PANEL DISCUSSION - PRODUCT QUALIFICATION IN THE 21ST CENTURY
SPECIAL TOPIC:
GERMICIAL IRRADATION
DIELECTRICS II - Session 6
3D.1 Soft Error Rate Mitigation Techniques for Modern Microcircuits
pdf of visuals, pdf of paper & 3D.1 Questions and Answers
3D.2 SER Reliability of 1TRAM Designs
pdf of visuals, pdf of paper & 3D.2 Questions and Answers
4A.1 Reliability Test of MESFETs in Presence of Hot Electrons
pdf of visuals, pdf of paper & 4A.1 Questions and Answers
4A.2 Innovative Nitride Passivation on Pseudomorphic GaAS HEMTs and Its Impact
on Device Performance
pdf of visuals, pdf of paper &4A.2 Questions and Answers
4A.3 Evolution of DC and RF Degradation Induced by High-Temperature Accelerated
Lifetest of Pseudomorphic GaAs and InGaAs/InAlAs/InP HEMT MMICs
pdf of visuals, pdf of paper &4A.3 Questions and Answers
4B.1 Impact of Negative Bias Temperature Instability on Digital Circuit Reliability
pdf of visuals, pdf of paper & 4B.1 Questions and Answers
4B.2 Leakage Current and Reliability Evaluation of Ultra- thin Re- oxidized Nitride and
Comparison with Silicon Dioxides
pdf of visuals, pdf of paper & 4B.2 Questions and Answers
4B.3 Extending the Reliability Scaling Limit of Gate Dielectrics through Remote
Plasma Nitridation of N2-O-Grown Oxides and NO RTA Treatment
pdf of visuals, pdf of paper & 4B.3 Questions and Answers
4B.4 N- FET HCI Reliability Improvement by Nitrogen Interstitialization and its
Mechanism
pdf of visuals, pdf of paper & 4B.4 Questions and Answers
4B.5 Mechanism of Device Degradation under AC stress in Low- Temperature
Polycrystalline Silicon TFTs
pdf of visuals, pdf of paper & 4B.4 Questions and Answers
4C.1 Evaluation of STI Degradation Causing DRAM Standby Current Failure in Burn- in
Mode Operation Using a Carrier Injection Method
pdf of visuals, pdf of paper & 4C.1 Questions and Answers
4C.2 Charge Trapping Induced DRAM Data Retention Time Degradation under Wafer-
Level Burn- in Stress
pdf of visuals, pdf of paper & 4C.2 Questions and Answers
4C.3 A Technique to Predict Gate Oxide Reliability Using Fast On- Line Ramped QBD
Testing
pdf of visuals, pdf of paper & 4C.3 Questions and Answers
4D.1 (Invited) Investigation of Via- Dominated Multi- Modal Electromigration Failure
Distributions in Dual Damascene Cu Interconnects With a Discussion of the
Statistical Implications
pdf of visuals, pdf of paper & 4D.1 Questions and Answers
4D.2 Pseudo- Breakdown Events Induced by Biased- Thermal- Stressing of Intra- Level
Cu Interconnects - Reliability & Performance Impact
pdf of visuals, pdf of paper & 4D.2 Questions and Answers
4D.3 Stress- Induced Voiding Under Vias Connected To Wide Cu Metal Leads
pdf of visuals, pdf of paper & 4D.3 Questions and Answers
4D.4 Electromigration Study of Cu/ low k Dual- damascene Interconnects
pdf of visuals, pdf of paper & 4D.4 Questions and Answers
4D.5 Electromigration of Cu and Al Using Wafer Level Isothermal Technique
pdf of visuals, pdf of paper & 4D.5 Questions and Answers
4D.6 Modeling and Analysis of Via Hot Spots and Implications for ULSI Interconnect
Reliability
pdf of visuals, pdf of paper & 4D.6 Questions and Answers
5.1 (Invited) Use of EEPROM- based Sensors in Investigating Physical Mechanisms
Responsible for Charging Damage
pdf of visuals, pdf of paper & 5.1 Questions and Answers
5.2 Influence of Plasma Edge Damage on Erase Characteristics of NOR Flash
EEPROM using Channel Erase Method
pdf of visuals, pdf of paper & 5.2 Questions and Answers
5.3 Enhanced Plasma Charging Damage due to AC Charging Effect
pdf of visuals, pdf of paper & 5.3 Questions and Answers
5.4 The Influence of IMD Bake Process on Buried Channel PMOS Hot Carrier
Reliability of Advanced DRAM
pdf of visuals, pdf of paper & 5.4 Questions and Answers
5.5 Impact Of Focused Ion Beam Assisted Front End Processing On n- MOSFET
Degradation
pdf of visuals, pdf of paper & 5.5 Questions and Answers
Introduction of Panel Moderator: Bernie Pietrucha
ST.1 (Invited) The Effects of Total Ionizing Dose Irradiation on CMOS Technology and
the use of Design Techniques to Mitigate Total Dose Effects
pdf of visuals, pdf of abstract & ST.1 Questions and Answers
ST.2 (Invited) Effects of E- Beam Mail Sanitizing Process on Commercial Electronics
pdf of visuals, pdf of abstracts & ST.2 Questions and Answers
ST.3 (Invited) Filter Optimazation for X- Ray Inspection of Surface- Mounted IC’s
6.1 Imaging Breakdown Spots in SiO2 Films and MOS Devices with a Conductive
Atomic Force Microscope
pdf of visuals, pdf of paper & 6.1 Questions and Answers
6.2 Analysis of Exponential Decay Transient Current in MOS Capacitors
pdf of visuals, pdf of paper & 6.2 Questions and Answers
6.3 Modeling of Substrate Related Extrinsic Oxide Failure Distributions
pdf of visuals, pdf of paper & 6.3 Questions and Answers
6.4 Soft Breakdown Enhanced Hysteresis Effects in Ultra- Thin Oxide SOI nMOSFETs
pdf of visuals, pdf of paper & 6.4 Questions and Answers
6.5 Time- dependent Dielectric Breakdown in Poly- Si CVD HfO2 Gate Stack
pdf of visuals, pdf of paper & 6.5 Questions and Answers