Notes

Slide Show

Outline

1	High Performance Logic Technology and Reliability Challenges Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration
2	Outline Logic Technology Evolution 90 nm Logic Technology Future Scaling Challenges
3	CPU Transistor Count Trend
4	CPU MHz Trend
5	Feature Size Trend
6	Feature Size Trend
7	CPU Power Trend
8	Logic Technology Evolution
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10	Key 90 nm Process Features High Speed, Low Power Transistors 1.2 nm gate oxide 50 nm gate length Strained silicon technology Faster, Denser Interconnects 7 copper layers New low-k dielectric Lower Chip Cost 1.0 mm² SRAM memory cell size 300 mm wafers
11	90 nm Generation Transistor
12	90 nm Generation Gate Oxide
13	1.2 nm Gate Oxide Reliability
14	Strained Silicon Transistors
15	Transistor Performance Trend
16	90 nm Generation Interconnects
17	90 nm Generation Interconnects
18	Cu + CDO Interconnects
19	Void-Free Required for Electromigration
20	Electromigration Enabling
21	Electromigration Improvement
22	6-T SRAM Cell
23	Intel SRAM Cell Size Trend
24	52 Mbit SRAM on 90 nm Process
25	Same Process for Logic and SRAM
26	52 Mbit SRAM Chips on 300 mm Wafer
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28	Planar CMOS Transistor Scaling
29	Transistor I_OFF Leakage Trend
30	Fully Depleted Transistors
31	Fully Depleted Transistors
32	Transistor I_GATE Leakage Trend
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34	Early Problems with High-K Dielectrics
35	Interconnect Delay
36	Narrow Line Width Resistivity Increase
37	Electromigration Requirements
38	Fragile Low-k Dielectric Materials
39	Summary
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