Tuesday, April 1, 8:00 a.m. Landmark AB
Opening & Keynote Addresses
TECHNOLOGY AND RELIABILITY CHALLENGES IN FOUNDRY BUSINESS— Shang-yi Chiang Ph.D., Sr. VP, Head, R & D Group, TSMC
TECHNOLOGY AND RELIABILITY CHALLENGES AT INTEGRATED DEVICE MANUFACTURERS— Mark Bohr, Intel Senior Fellow, Tech. & Mfg Group, Dir., Process Architecture & Integration
Tuesday, April 1, 10:30 a.m. Landmark AB
Circuits (1.)
1.1 EFFECT OF GATE OXIDE BREAKDOWN ON RF DEVICE AND CIRCUIT PERFORMANCE—H. Yang, J.S. Yuan, and E. Xiao, University of Central Florida, Orlando, FL
The degradation of S-parameters and cut-off frequency of 0.16 µm NMOS devices due to gate oxide breakdown (BD) are examined. The influence of nMOSFET BD on the performance of a low noise amplifier (LNA) is studied using the measured device S-parameters. There is a nonzero probability that the circuit continues to work. An equivalent circuit model for MOSFETs after gate oxide breakdown is proposed.
1.2 ON THE DEGRADATION OF P-MOSFETS IN ANALOG AND RF CIRCUIT UNDER INHOMOGENEOUS NEGATIVE BIAS TEMPERATURE STRESS—C. Schlünder, R. Brederlow, Infineon, München, Germany, B. Ankele, Infineon Technologies, Villach, Austria, A. Lill, Infineon, München, Germany, K. Goser, University of Dortmund, Dortmund, Germany, and R. Thewes, Infineon, München, Germany
The effect of inhomogeneous negative bias temperature stress applied to p-MOS transistors under analog and RF CMOS operating conditions is investigated. Experimental data of a 0.18 µm process are presented, an analytical model is derived, and lifetime prediction issues are considered and compared to the homogeneous case.
1.3 MODELING AND EXPERIMENTAL VERIFICATION OF THE EFFECT OF GATE OXIDE BREAKDOWN ON CMOS INVERTERS—R. Rodríguez, Universitat Autònoma de Barcelona, Bellaterra, Spain, J.H. Stathis, and B.P. Linder, IBM, Yorktown Heights, NY
The effect of oxide breakdown (BD) on the performance of CMOS inverters has been investigated. The results show that BD can affect the inverter performance in a different way depending on the stress polarity applied to the inverter input. In all the cases, the oxide breakdown conduction has been modeled as gate-to-diffusion leakage with a power law formula of the type I= KVp which was previously found to describe the breakdown in capacitor structures.
1.4 BEHAVIOR OF NBTI UNDER AC DYNAMIC CIRCUIT CONDITIONS—W. Abadeer and W. Ellis, IBM Micro-electronics, Essex Junction, VT
The NBTI mechanism was investigated for 5nm gate oxide under conditions of circuit operation in the frequency range of 2MHz to 20MHz and device "ON" duty factor in the range of 30% to 70%. The increase in magnitude of threshold voltage and decrease in device current under AC operation are generally lower than that of DC operation by 3X or higher. The time power function dependency of the degradation at sufficient stress times, are lower than of DC operation. These results indicate that more emphasis need to be placed on dynamic behavior of NBTI for scaled CMOS technologies.
Tuesday, April 1, 1:35 p.m. Landmark AB
High K Dielectrics (2A)
2A.1 (Invited) STRESS POLARITY DEPENDENCE OF DEGRADATION AND BREAKDOWN OF SiO2/HIGH-K STACKS—R. Degraeve, T. Kauerauf+, A. Kerber*, E. Cartier*, B. Govoreanu+, Ph. Roussel, L. Pantisano, P. Blomme+, B. Kaczer, G. Groeseneken+ IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; +IMEC and KU Leuven, *ISMT affiliated to IMEC
Major efforts are presently done to replace SiO2 by high-k gate dielectrics and promising results have been obtained with SiO2/high-k double stacks. In this paper, we summarize our reliability study on two material systems: SiO2/Al2O3 and SiO2/ZrO2. We show that degradation in these stacks can be viewed as a competitive degradation of the constitutive layers. A consistent reliability prediction can only be made if the conduction mechanism through both layers and the carrier energy are taken into account.
2A.2 ACCURATE RELIABILITY EVALUATION OF NON-UNIFORM ULTRATHIN OXYNITRIDE AND HIGH-K LAYERS—P. Roussel, R. Degraeve, A. Kerber, L. Pantisano, and G. Groeseneken, IMEC, Leuven, Belgium
We present a methodology to separate the tBD-spread caused by wafer non-uniformity from the inherent spread generated by the physical breakdown mechanism. The method relies on the area scaling effect and is particularly useful for the correct reliability evaluation of ultra-thin SiO2 and high-k dielectrics.
2A.3 NOVEL DIELECTRIC BREAKDOWN MODEL OF Hf-SILICATE WITH HIGH TEMPERATURE ANNEALING—T. Yamaguchi, T. Ino, H. Satake, and N. Fukushima, Toshiba Corp., Yokohama, Japan
The influences of the unavoidable high temperature annealing in MIS fabrication process on the reliability characteristics of high-k gate dielectrics are well investigated. Especially the Qbd distributions drastically degraded after high temperature annealing in Hf-silicate dielectrics. We propose a novel dielectric breakdown model of high-k gate dielectrics, which induced the poor Qbd distributions.
2A.4 CHARACTERIZATION OF THE VT INSTABILITY IN SiO2/HfO2 GATE DIELECTRICS—A. Kerber, Infineon Technologies AG, Leuven, Belgium, E. Cartier, SEMATECH assignee at IMEC, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H.E. Maes, U. Schwalke, IMEC, Leuven, Belgium
Threshold voltage (VT) stability is a key reliability challenge for future CMOS technologies using alternative gate dielectrics. In this paper it is shown that conventional SiO2 / HfO2 dual layer stacks with poly Si gate electrodes suffer from a strong VT instability. Using conventional and time-resolved (pulsed) measurement techniques, it is demonstrated that the VT instability is caused by charging / discharging of pre-existing defects in the HfO2 layer. The observed charging instability makes an assessment of dielectric reliability and a lifetime prediction for SiO2 / HfO2 dual layer gate stacks, based on defect generation, rather problematic.
2A.5 DYNAMIC RELIABILITY CHARACTERISTICS OF ULTRA-THIN HfO2—Y.H. Kim, K. Onishi, C.S. Kang, R. Choi, H.-J. Cho, S. Krishnan, A. Shahriar, J.C. Lee, University of Texas, Austin, TX
Larger lifetime of HfO2 under dynamic AC stressing has been observed in comparison to constant voltage stress. Higher frequency, lower duty cycle and thicker dielectrics result in larger lifetime enhancement. Stress-induced leakage current and hysteresis degradation were also found to be less severe under AC stress. The improved reliability under AC stress is believed to be due to less charge trapping compared to DC stressing.
Tuesday, April 1, 4:05 p.m. Landmark AB
Ser (2B)
2B.1 (Invited) NEUTRON-INDUCED LATCHUP IN SRAMS AT GROUND LEVEL—Paul E. Dodd, Marty R. Shaneyfelt, James R. Schwank, and Gerald L. Hash, Sandia National Laboratories, Albuquerque, NM
Neutron-induced single-event latchup has been studied in SRAMs manufactured by several different vendors. These SRAMs span different cell designs (six-transistor and four-transistor cells), technology generations (0.25 µm to 0.14 µm) and power supplies (5 V to 1.5 V). While some technologies appear to be latchup-free in neutron environments, others have neutron-induced latchup failure-in-time (FIT) rates as high as 300 FIT/Mbit at room temperature and maximum rated voltage. Latchup FIT rates increase dramatically with temperature. The observed latchup rates can lead to very high failure rates in systems with large amounts of memory, and can't be circumvented using error correction.
2B.2 MEASURING THE WIDTH OF TRANSIENT PULSES INDUCED BY IONISING RADIATION—M. Nicolaidis and R. Perez, iRoC Technologies, Grenoble, France
This work presents a technique for measuring accurately the width of transient pulses induced by ionizing radiation in combinatorial logic cells. The approach allows qualifying the cells of a cell library and create pulse width files. In combination with an even driven transient fault simulation tool at gate level, like ROBAN, the pulse width files can be used to qualify the SET FIT level of complex ICs.
2B.3 A SYSTEMATIC APPROACH TO SER ESTIMATION AND SOLUTIONS—H.T. Nguyen and Y. Yagil, Intel Corp., Chandler, AZ
This paper describes a method for estimating Soft Error Rate (SER) and a systematic approach to identifying SER solutions. A high performance processor is used as the framework for discussions. Users can follow the proposed method to assess their SER status. One major finding is that latches/flip flops and combinational logic contribute significantly to the overall chip Failure-In-Time (FIT) rate. Also discuss are potential SER techniques.
2B.4 CONTRIBUTION OF DEVICE SIMULATION TO SER UNDERSTANDING—J-M. Palau, CEM2, Université Montpellier II, France, M-C. Calvet, EADS-LV, Les Mureaux, France, P.E. Dodd, F.W. Sexton, Sandia National Labs, Albuquerque, NM, and P. Roche, STMicroelectronics, Crolles, France
A summary of recent works and new developments on device simulation of particle-induced upsets in SRAM memories is presented. Upsets are supposed due to the ionizing recoil products of nuclear reactions with atmospheric neutrons. The goal being to give properties helpful for soft error rate (SER) predictive calculations, the probabilistic aspect of the problem is considered.
Tuesday, April 1, 1:35 p.m. Landmark C
Latch-Up (2C)
2C.1 (Invited) Latchup in CMOS—W.H. Morris, Silicon Engineering, Austin, TX
Latchup is a failure mode in CMOS circuits that results in either soft failures with a loss of data or logic state, or in extreme cases, a destructive hard failure and permanent loss of the circuit. As isolation widths shrink, device structures become ever more susceptible to both failure modes, unless steps are taken to improve latchup robustness. The rapid proliferation of multiple power supply voltages and system-on-chip designs also exacerbate the problem. Prevention of both transient and destructive failures is of utmost importance in advanced CMOS designs. CMOS technologies have largely converged on p- bulk substrates. Reducing the CMOS power supply voltage is a potential solution for hard latchup failures, but not soft ones. This paper presents characterizations of latchup obtained by process and device modeling. Introducing a low resistance shunt layer by ion implantation is shown to be the most effective method for preventing all types of latchup failures.
2C.2 A NEW I/O SIGNAL LATCHUP PHENOMENON IN VOLTAGE TOLERANCE ESD PROTECTION CIRCUITS WITH PCI APPLICATION—J. Salcedo-Suner, R. Cline, C. Duvvury, A. Cadena-Hernandez and L. Ting, Texas Instruments, Dallas, TX
We report for the first time a new type of unexpected latchup phenomenon that can occur in deep submicron technologies with the required implementation of voltage tolerant ESD protection circuits. In contrast to the well known standard latchup, this new latchup, dubbed as Signal Latchup, becomes evident only through interaction from neighboring I/O pins. The issues involved with this latchup effect and the subsequent trade-off with ESD are presented in detail.
2C.3 NEW OBSERVANCE AND ANALYSIS OF VARIOUS GUARD-RING STRUCTURES ON LATCH-UP HARDNESS BY BACKSIDE PHOTO EMISSION IMAGE—S. Liao, C. Niou, W.T.K. Chien, A. Guo, W. Dong, and C.Huang, SMIC, Shanghai, China
In this paper, the influence of different guard-ring structures on latch-up susceptibility has been studied on four standard test structures fabricated on standard twin well CMOS process. The test structures include the non-, single, double, and multi-double guard-ring. Based on hold I-V characteristics test results, the latch-up hardness of P+ guard-ring structure is much greater than that of the N+ guard-ring. Because the shunting resistances of N-Well and P-Well are significantly reduced by multi-double guard-rings, the latch-up immunities of the multi-double guard-ring structures are better than those of double guard-ring structures.
2C.4 TRANSMISSION LINE PULSE PICOSECOND IMAGING CIRCUIT ANALYSIS (TLP-PICA) METHODOLOGY FOR EVALUATION OF ELECTROSTATIC DISCHARGE AND LATCHUP—A. Weger, S.H. Voldman*, F. Stellari, P. Song, P. Sanda**, and M. McManus, IBM T.J. Watson Research Center, Yorktown Heights, NY *IBM Microlectronics, Essex Junction, VT **IBM Server Division, Poughkeepsie, NY
A high current pulsed picosecond imaging circuit analysis (PICA) tool is developed for the analysis of semiconductor devices, circuits and full chips for evaluation of ESD, latchup, hot e and reliability. This TLP - PICA method allows for both terminal, spatial, and pico-second time domain analysis of ESD and latchup phenomenon.
2C.5 A DEVICE LEVEL NEGATIVE FEEDBACK IN THE EMITTER LINE OF SCR-STRUCTURES AS A METHOD TO REALIZE LATCH-UP FREE ESD PROTECTION—A. Concannon, V.A. Vashchenko, M.T. Beek, and P. Hopper, National Semiconductor, Santa Clara, CA
A new approach to control the holding voltage of thyristor ESD protection structures by negative feedback in the emitter is presented. The clamp voltage is tuned to exceed the power supply, thus eliminating the mechanism for latch-up. This is demonstrated using cascoded-triggered LVTSCR for 5.5V tolerant I/Os in 0.18µm CMOS.
Tuesday, April 1, 4:05 p.m. Landmark C
Late News Papers (2D)
2D.1 A 90 nm CMOS TECHNOLOGY WITH MODULAR QUADRUPLE GATE OXIDES FOR ADVANCED SOC APPLICATIONS—M. R. Mirabedini, V. P. Gopinath, A. Kamath, M. Y. Lee, W. J. Hsia, V. Hornback*, Y. Le*, A. Badowski*, B. Baylis*, E. Li, S. Prasad, O. Kobozeva, J. Haywood*, W. Catabay*, W. C. Yeh, LSI Logic Corporation, Milpitas, CA *LSI Logic, Gresham, OR
This paper describes a 90 nm technology with modular quadruple gate oxides (16, 28, 50, 64 Å) on the same chip, which allows integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Volts for different circuit applications. The proposed modular gate oxide process with pre-gate nitrogen implant was shown to be superior to conventional grow-etch-grow approach in terms of gate leakage current, integrity and interface quality of the multiple gate oxides. A high current drive of 1020/390 µA/µm was demonstrated for N/P channel core transistors.
2D.2 DETAILED INVESTIGATION OF THE TRANSIENT LOCAL TUNNELING IN GATE OXIDES—M. F. Beug, R. Ferretti, and K. R. Hofmann, University of Hannover, Hannover, Germany
A detailed investigation of the local transient tunneling currents due to substrate- and gate-near traps generated by Fowler-Nordheim stress in nitrided oxide MOS structures has been performed. We demonstrate that for the correct interpretation of these transient SILC currents it is essential to include the effects of the substrate and poly-Si capacitances. This is leading to gate voltage dependent weighting factors which relate the measured current transients to the local trap tunnel currents near to the substrate and the gate. By a combination of these measurements with transient capacitance measurements it is posssible to separately determine currents and thus densities of traps generated close to the substrate and to the gate.
2D.3 ABNORMAL GATE OXIDE THICKENING AT ACTIVE EDGE WITH SIN-LINERED SHALLOW TRENCH ISOLATION—Kong-Soo Lee, Jae-Jong Han, Seung-Mok Shin, Ki-Hyun Hwang, Seok-Woo Nam, Hyeon-Deok Lee, and Chang-Lyong Song, Samsung Electronics Co. LTD., Yongin-City, Korea
Abnormal gate oxide thickening at active edge (GOTAE) has been investigated in dynamic random access memories (DRAMs) with SiN-linered shallow trench isolation (STI). 1% of gaseous HCl, which is added during dry oxidation, plays a major role in inducing abnormal GOTAE by the mechanical interaction with thin SiN layer in STI. Other structural parameters such as thickness of trench sidewall oxide, liner SiN and sacrificial oxide are believed to influence the amount of oxide thickening. In order to avoid abnormal GOTAE, wet oxidation is introduced and turns out to be effective to suppress it. Electrical properties which change is susceptible to the extent of GOTAE are also presented in this paper.
2D.4 USING THE TEMPERATURE COEFFICIENT OF THE RESISTANCE (TCR) AS EARLY RELIABILITY INDICATOR FOR STRESSVOIDING RISKS IN COPPER INTERCONNECTS—A. von Glasow, A.H. Fischer, and G. Steinlesberger, Infineon Technologies, Munich, Germany
This work shows, that TCR measurements are well suited to reveal differences in the medium grain size in copper lines of different geometry. In addition, it will be demonstrated with split investigations that samples which are affected by stressvoids can easily be distinguished from "good" samples by their distinct smaller TCR value. Hence, there is an enormous potential to use the TCR as an early reliability indicator by introducing fast TCR measurements as a quick check during process development, qualification and wafer level monitoring.
2D.5 A STUDY IN FLIP-CHIP UBM/BUMP RELIABILITY WITH EFFECTS OF SN-PB SOLDER—J.D. Wu, P.J. Zheng, C.W. Lee, S.C. Hung and J.J. Lee, Advanced Semiconductor Engineering, Inc., Kaohsiung, Taiwan
This paper aims to investigate the electromigration phenomenon of under bump metallurgy (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). Various current densities and ambient temperatures are applied to study their impacts on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures.
Wednesday, April 2, 8:00 a.m. Landmark AB
Interconnects (3A)
3A.1 LINE DEPLETION ELECTROMIGRATION CHARACTERISTICS OF Cu INTERCONNECTS—B. Li and T.D. Sullivan, IBM Microelectronics, Essex Jct., VT
Specific details of fabrication process and geometry of Cu interconnects result in different electromigration fail modes. This paper presents the impact of line/via layout, fabrication process and liner robustness on EM redundancy behavior for line depletion mode of Cu interconnects. Considerations on product design improvements are discussed based on the experimental results.
3A.2 THE INFLUENCE OF THE SiN-CAP PROCESS ON THE ELECTROMIGRATION AND STRESSVOIDING PERFORMANCE OF DUAL DAMASCENE COPPER INTERCONNECTS—A. von Glasow, A.H. Fischer, M. Hommel, A. Zitzelsberger, A. Hausmann*, H.-P. Sperlich*, D. Bunel, P. Raffin, C. Robin, ALTIS Semiconductors, Essonnes, France, O. Heitzsch*, J. Kriz*, and G. Friese*, Infineon Technologies, München, Germany *Infineon Technologies, Dresden, Germany
Comprehensive studies were done to investigate the EM and SV performance dependent on the pre-treatment and deposition technique of the SiN cap layer, respectively. The investigations revealed a remarkable trade-off between EM and SV performance depending primarily on the pre-treatment. On the one hand an aggressive pre-treatment yield improved Cu-SiN-interface properties and hence higher electromigration lifetimes. On the other hand these pre-cleans were found to cause higher SV susceptability because of microstructural damages introduced into the bulk metal.
3A.3 ELECTROMIGRATION IMPROVEMENT WITH CVD TIN(Si) BARRIER IN COPPER DUAL DAMASCENE STRUCTURES—A. Vijayendran, G.B. Alers, P. Gillespie*, L. Chen*, H. Cox*, K. Lam*, R. Augur*, K. Shannon, K. Pfeifer*, and M. Danek, Novellus Systems, San Jose, CA *Sematech, Austin, TX
Integration of CVD barriers into a dual damascene copper process flow must avoid copper on the side-walls of vias causing poor barrier/dielectric adhesion during the high temperature CVD process. An alternate pre-clean method removes the risk of copper on the sidewall and gives improved process margin for reliability of CVD barriers.
3A.4 STRESS-INDUCED VOIDING AND ITS GEOMETRY DEPENDENCY CHARACTERIZATION—K.Y.Y. Doong, R.C.J. Wang, S.C. Lin, L.J. Hung, S.Y. Lee, C.C. Chiu, D.H. Su, K.L. Young, K. Wu, and Y.K. Peng, TSMC, Hsin-Chu, Taiwan
Stress induced voiding (SIV) is explored in the aspect of design attribute and geometry parameters. Two kinds of test structures were used to evaluate resistance change to the impact of reliability and understand SIV mechanism. Thus, a reliability-robustness guideline on the consideration of geometry configuration can be derived.
3A.5 ON THE USE OF HIGHLY ACCELERATED ELECTROMIGRATION TESTS (SWEAT) ON COPPER—A. Zitzelsberger, R. Bauer, J. von Hagen, S. Penka, A. Pietsch, and W. Walter, Infineon Technologies AG, München Germany
SWEAT applied to via line test structures with a wide range of stress conditions were applied to determine the acceleration limits and the kinetics. A good correlation to standard iso-current tests on Package Level is found. The SWEAT sensitivity on geometrical test structure variations and the impact of extreme acceleration on different types of failure modes will be discussed.
Wednesday, April 2, 10:55 a.m. Landmark AB
BEOL Dielectrics (3B)
3B.1 LEAKAGE, BREAKDOWN, AND TDDB CHARACTERISTICS OF POROUS LOW-K SILICA-BASED INTERCONNECT MATERIALS—E.T. Ogawa, J. Kim, G.S. Haase, H.C. Mogul, and J.W. McPherson, Texas Instruments, Dallas, TX
The reliability physics of low-k interconnect dielectrics is of great interest. Leakage, breakdown and TDDB data are presented for fluorinated silica, carbon-doped silica, and porous carbon-doped silica. While the breakdown strength and TDDB values tend to degrade with the degree of porosity, the failure kinetics (physics) are similar.
3B.2 THE EFFECT OF LOW-K ILD ON THE ELECTROMIGRATION RELIABILITY OF Cu INTERCONNECTS WITH DIFFERENT LINE LENGTHS—C.S. Hau-Riege, A.P. Marathe, and V. Pham, AMD, Sunnyvale, CA
Three key electromigration parameters (MTF, n, and sigma) have been characterized as a function of line length for low-k and Si02-based material. While trends are similar for both materials, the low-k material has a lower MTF for a given jL, thereby leading to poorer short-line performance.
Wednesday, April 2, 8:00 a.m. Landmark C
Transistors (3C)
3C.1 EVIDENCE FOR HYDROGEN-RELATED DEFECTS DURING NBTI STRESS IN P-MOSFETS—V. Huard, Philips Semiconductors, Crolles, France, F. Monsieur, G. Ribes, and S.Bruyere, STMicroelectronics, Crolles, France
This work gives an insight of the degradation mechanisms during NBTI stress on ultrathin oxides by the generation of interface traps and oxide defects. Their generation is linked to the release of hydrogen species at the interface according to the hydrogen release model. Though, only hot holes can be trapped as provided by the anode hole injection phenomenon.
3C.2 NEGATIVE BIAS TEMPERATURE INSTABILITY OF pMOSFETs WITH ULTRA-THIN SiON GATE DIELECTRICS—S. Tsujikawa, T. Mine, K. Watanabe, Y. Shimamoto, R. Tsuchiya, K. Ohnishi, T. Onai, J. Yugami, and S. Kimura, Hitachi, Ltd., Tokyo, Japan
In order to predict the reliability of near future CMOS, we studied negative bias temperature instability (NBTI) of pMOSFETs with ultra-thin SiON gate dielectrics, such as basic mechanism, dependence on gate dielectric thickness, effect of nitrogen in gate dielectrics, and feasibility of SiON gate dielectrics with a high nitrogen concentration.
3C.3 COLLAPSE OF MOSFET DRAIN CURRENT AFTER SOFT BREAKDOWN AND ITS DEPENDENCE ON THE TRANSISTOR ASPECT RATIO W/L—A. Cester, S. Cimino, A. Paccagnella, University di Padova, Padova, Italy, G. Ghidini, STMicroelectronics, Agrate Brianza, Italy, and G. Guegan, CEA-LETI, Grenoble, France
We studied the Soft-Breakdown impact on the MOSFET characteristics: Ids and gm dramatically drop in transistors with small W/L after Soft-Breakdown. The Ids and gm collapse is due to the formation of an oxide defective region around the Soft- Breakdown spot, whose area is much larger than the Soft-Breakdown conductive path.
3C.4 DYNAMIC NBTI OF PMOS TRANSISTORS AND ITS IMPACT ON MOSFET LIFELINE—G. Chen, K.Y. Chuah, M.F. Li, D.S.H. Chan, C.H. Ang, J.Z. Zheng, Y. Jin, National University of Singapore, Singapore, and D.L. Kwong, University of Texas, Austin, TX
Dynamic NBTI is demonstrated for p-MOSFETs with ultrathin gate oxides. Interface traps generated during negative gate bias stress are passivated under the positive gate bias. Due to this effect, the p-MOSFET lifetime under the operation in a CMOS inverter circuit is prolonged significantly. A physical model is suggested to explain the DNBTI. This finding has significant impact on future scaling of CMOS devices.
3C.5 AN IMPROVED INTERFACE CHARACTERIZATION TECHNIQUE FOR A FULL-RANGE PROFILING OF OXIDE DAMAGE IN ULTRA-THIN GATE OXIDE CMOS DEVICES— S.-J. Chen+*, T.-C. Lin, D.-K. Lo*, J.-J. Yang**, S.S. Chung*, T.-Y. Kao, R.-Y. Shiue, C.-J. Wang, Y.-K. Peng, TSMC, Hsinchu, Taiwan *National Chiao Tung University, Taiwan **Chang Gung University, Taiwan
In this paper, an improved gate-diode technique has been developed for the interface characterization on both n- and p-MOSFET's with gate oxide in the direct tunneling regime. This method has been demonstrated successfully for measuring oxide damage in all of the channel, space-charge (or junction), and drain extension regions in 20Å ultra-thin gate oxide devices. As an application of the present method, the lateral profile of localized oxide damage due to Negative Bias Temperature Instability (NBTI) or Hot Carrier (HC) effect has been demonstrated. It provides us an understanding of the correlation between the device degradation and various stress-induced oxide damage in CMOS devices.
3C.6 EVALUATION OF THE POSITIVE BIASED TEMPERATURE STRESS STABILITY IN HfSiON GATE DIELECTRICS—A. Shanware, M.R. Visokay, J.J. Chambers, A.L.P. Rotondaro, H. Bu, M.J. Bevan, R. Khamankar, S. Aur, P.E. Nicollian, J.W. McPherson, and L. Colombo, Texas Instruments, Dallas, TX
Results are reported for biased temperature stress measurements made on transistors with HfSiON gate dielectric films.This paper reports that NMOS devices, made with HfSiON as the gate dielectric are stable and that transistors can be operated at power supply voltage of 1.2V and at 105°C for 10 years without substantial degradation of either the threshold voltage or the drive current.
3C.7 COMPETING HOT CARRIER DEGRADATION MECHANISMS IN LATERAL N-TYPE DMOS TRANSISTORS—P. Moens, AMI, Pocatello, ID, G. Van den bosch, and G. Groeseneken, IMEC, Oudenaarde, Belgium
Two competing hot carrier degradation mechanisms that are observed in lateral nDMOS transistors, could unambiguously be identified by using electrical stress data, Charge Pumping and TCAD. A first mechanism is attributed to a decreased electron mobility due to Dit formation, the second mechanism is due to hot-hole injection and trapping in the drift region.
Wednesday, April 2, 8:00 a.m. Landmark D
Esd (3D)
3D.1 (Invited) ESD CHALLENGES IN MAGNETIC RECORDING: PAST, PRESENT AND FUTURE—A. Wallash, Maxtor Corporation, Milpitas, CA
Over the past decade, the magnetic recording industry has been forced to understand and solve many critical ESD problems. As the dimensions of the giant magnetoresistive (GMR) readback transducer have been scaled down to increase storage capacity, has become increasingly important to understand and solve ESD issures in hard disk drives. This technical presentation will review the many ESD-related challenges that face magnetic recording devices and processes and discuss their solutions. Special attention will be paid to field emission-induced electrical breakdown problems across sub-micron gaps and insulators. New magnetic recording devices that have a CDM failure voltage of less than 1 V will be reviewed to show how important controlling ESD will be to the future success of magnetic recording.
3D.2 IMPACT OF TECHNOLOGY SCALING ON THE HIGH CURRENT BEHAVIOR OF RF CMOS TECHNOLOGY—G. Boselli, V. Reddy, and C. Duvvury, Texas Instruments Dallas, TX
In this paper the impact of the starting material resistivity on the ESD, Latch-up and BVii sensitivity will be investigated for a sub-0.1µm fully silicided CMOS technology for low power and RF applications. The mechanisms through which a substrate spreading resistance increase enhances the uniformity of the ESD current in nMOS protection methods will be investigated in detail.
3D.3 INTERNAL BEHAVIOR OF BCD ESD PROTECTION DEVICES UNDER VERY-FAST TLP STRESS—M. Blaho, D. Pogany, E. Gornik, Institute for Solid State Electronics TU Vienna, Austria, H. Wolf, H. Gieser, Fraunhofer Institute, Freiburg, Germany, L. Zullino, E. Morena, R. Stella, and A. Andreini, STMicroelectronics, Cornaredo, Italy
Internal thermal and carrier density distributions during a 10ns very-fast TLP high current stress are investigated in BCD technology ESD protection npn transistors using backside laser interferometric mapping technique. The results on devices with and without sinker having width variations are correlated with electrical characterization, device simulation and failure analysis.
3D.4 MOVING CURRENT FILAMENTS IN ESD PROTECTION DEVICES AND THEIR RELATION TO ELECTRICAL CHARACTERISTICS—D. Pogany, S. Bychikhin, E. Gornik, Institute for Solid State Electronics TU Vienna, Austria, M. Denison, N. Jensen, Infineon Technologies, Munich, Germany, G. Groos, University of Armed Forces, Neuibiberg, Germany, and M. Stecher, Infineon Technologies, Munich, Germany
Dynamics and "travelling" modes of persistent moving current filaments in electrostatic discharge (ESD) protection devices during high current stress are investigated using backside interferometric thermal mapping methods. The modes of the filament passage over the device width are related to the time evolution of voltage waveform and to IV characteristics.
3D.5 MODELING OF TEMPERATURE DEPENDENT CONTACT RESISTANCE FOR ANALYSIS OF ESD RELIABILITY—K.-H. Oh, J.-H. Chun, K. Banerjee, UC Santa Barbara, Santa Barbara, CA, C. Duvvury, and R.W. Dutton, Texas Instruments, Dallas, TX
A physically based model has been formulated to comprehend the temperature dependent contact resistance model. The new model can generate silicided contact resistance values at high temperatures and it is capable of predicting high current behavior of silicided deep submicron devices, which has significant implications for failure analysis of advanced silicided devices. Using the model, it has been demonstrated how current localization is affected by temperature rise, which is helpful for predicting ESD reliability.
3D.6 DYNAMIC SUBSTRATE RESISTANCE SNAPBACK TRIGGERING OF ESD PROTECTION DEVICES—V. Vassilev, G. Groeseneken, M. Steyaert, and H. Maes, IMEC, Leuven, Belgium
A novel approach to design self-triggered ESD protection structures is presented. As a result, the base resistance of the parasitic BJT is increased, which in turns leads to faster and uniform snapback triggering. MEDICI simulations, in combination with TLP and EMMI characterization are performed to study in detail the structure operation.
3D.7 INCREASING THE ESD PROTECTION CAPABILITY OF OVER-VOLTAGE NMOS STRUCTURES BY COMB-BALLASTING REGION DESIGN—V.A. Vashchenko, A. Concannon, M.T. Beek, and P. Hopper, NSC, Santa Clara, CA
A new topological design solution that significantly increases robustness of snapback ESD protection NMOS structures for over-voltage applications is detailed and based on TCAD and experimental results generated in a 0.25µm CMOS process. The solution is based on the implementation of a spatially periodic drain n+ ballasting region thus forming a comb-like design. This structure is designed to eliminate the device degradation seen during HBM testing due to non-uniform snapback device turn-off of the structures thus limiting the current filamentation that is not predicted by TLP behavior.
3D.8 THE FAILURE MECHANISM OF THE HIGH VOLTAGE TOLERANCE IO BUFFER—J.-H. Lee, J.R. Shih, Y.H. Wu, J.J. Wang, K. Wu, and T.C. Ong, TSMC, Hsin-Chu, Taiwan, ROC
Although the primary ESD protection device for +ESD/Vss zapping of the high voltage tolerance (HVT) IO buffer is the stacked nMOSFET (ST NMOS), we found that ESD performance of a single ST NMOS device is much robust than the HVT IO.
Wednesday, April 2, 2:00 p.m. Landmark AB
BEOL Dielectrics (4A)
4A.1 (Invited) LEAKAGE BEHAVIOR AND RELIABILITY ASSESSMENT OF TANTALUM OXIDE DIELECTRIC MIM CAPACITORS—T. Remmel, R. Ramprasad, J. Walls, Motorola, Tempe, AZ
Reliability assessment was used extensively during the development of a low leakage tantalum oxide MIM (metal-insulator-metal) capacitor targeted for a Cu-based wireless integrated circuit platform. Leakage of the MIM capacitor as a function of process conditions and lifetime behavior under both DC and AC stressing is presented.
4A.2 A PHYSICAL MODEL OF TIME-DEPENDENT DIELECTRIC BREAKDOWN IN COPPER METALLIZATION—W. Wu, University of Central Florida, Orlando, FL, X. Duan, AVANEX Corporation, Richardson, TX, and J.S. Yuan, University of Central Florida, Orlando, FL
In this paper, a physical model of copper interconnect dielectric breakdown is presented. This model gives us a clear physical picture of TDDB in copper/dielectric/copper structures. The general continuity equation about Cu+ diffusion and drift is obtained. An analytical solution about TDDB lifetime is derived which can fit the experimental data very well at different electric fields and temperatures with only a few physical parameters. TDDB lifetime is proportional to the exponential of electric filed under acceleration condition, which is consistent with "E" model. However, under normal operation electric field, 0.2MV/cm, "E" model underestimates about 40% of the lifetime compare to the accuracy model.
4A.3 Cu ION MIGRATION PHENOMENA AND ITS INFLUENCE ON TDDB LIFETIME IN Cu METALLIZATION—J. Noguchi, N. Miura, M. Kubo, T.I. Tamaru, H. Yamaguchi, T. Hamada, K. Makabe, R. Tsuneda, and K. Takeda, Hitachi, Ltd., Tokyo, Japan
Time-dependent dielectric breakdown (TDDB) of sub-half micron Cu interconnects was investigated with regard to the waiting time between Cu-CMP and barrier dielectric deposition. Breakdown voltage and TDDB lifetime between adjacent Cu wires degraded abruptly as the waiting time in the air passed near 5 days. This is due to Cu ion migration phenomena on the CMP-surface. The degradation can be improved by keeping in N2-box or adopting post-cleaning. In addition, TDDB degradation can be seen on any Cu barrier dielectrics in this experiment.
4A.4 RELIABILITY AND ELECTRIC PROPERTIES FOR PECVD A-SiNx:H FILMS WITH AN OPTICAL BAND-GAP FROM 2.5 TO 5.38 eV—M.H.W.M. van Delden and P.J. van der Wel, Philips, Nijmegen, The Netherlands
The electric properties for PECVD a-SiNx:H films with optical bandgaps from 2.5 to 5.38 eV are reviewed in terms of changes occuring at the chemical and physical level and are linked to reliability models. It is suggested that the key is the complex process of the metastability of the Si-DB.
Wednesday, April 2, 4:05 p.m. Landmark AB
Device & Process (4B)
4B.1 HSG STORAGE CAPACITOR DIELECTRIC RELIABILITY OF 0.13 µm EMBEDDED DRAM CMOS TECHNOLOGY—S. Bruyère, D. Jacques, D. Roy, and C. Boccaccio, STMicroelectronics, Crolles, France
DRAM capacitance enhancement can be obtained through an area increase using Hemispherical_grained silicon and an ON stack modification. We will demonstrate that the oxidation step suppression enable to find a good candidate in term of capacitance, leakage current and reliability. Moreover, the different failure modes that could become critical are deeply investigated on HSG capacitors.
4B.2 A NEW PROCESS DAMAGE DURING THE ETCHING OF SMALL-CONTACT ON LONG FLOATING CONDUCTOR LAYER—J. Choi, D. Park, H. Moon, S. Lee, H. Ko, K. Yang, and W. Lee, Samsung Electronics Co., Yongin, Korea
We observed a new plasma process-induced damage during the contact etching on long poly-silicon resistors. When the resistor is larger than 200 Kohm, plasma charging forms a Si-O layer in the contact area resulting in a failure of circuit operation. An antenna rule on the conductor layer is required to prevent the process damage.
4B.3 NMOS PREDOPE ENHANCED OFF-STATE LEAKAGE CURRENT—K.Y. Lim, J. Lee, and E. Quek, Chartered Semiconductor Mfg. Ltd., Singapore
The paper discussed NMOS predope enhanced off-state leakage current related to STI oxide thinning for 0.13µm technology. High predope implant dose may cause the appearance of NMOS Ioff outliers as well as severe subthreshold hump. The subthreshold hump is related parasitic transistor formed due to STI oxide thinning. By optimising predope implant condition, the Ioff outlier problem can be suppressed.
4B.4 1/F NOISE DEGRADATION CAUSED BY FOWLER-NORDHEIM TUNNELING STRESS IN MOSFETS—M. Toita, S. Sugawa, A. Teramoto, Tohoku University, Sendai, Japan, T. Akaboshi, H. Imai, Asahi Kasei Microsystems, Nobeoka, Japan, and T. Ohmi, Tohoku University, Sendai, Japan
1/f noise level in MOSFETs was increased by F-N stress application. In PMOS, 1/f noise magnitude increases in short period of time, where as in NMOS the noise gradually changes along with stress time. We clarified that the relationship between process induced plasma damage and the 1/f noise.
Wednesday, April 2, 1:35 p.m. Landmark C
Compound Semiconductors (4C)
4C.1 (Invited) SEMICONDUCTOR RELIABILITY FROM A FABLESS COMPANY PERSPECTIVE—T.M. Kole, Sirenza Microdevices, Sunnyvale, CA
This paper will focus on three topics involving some of the key technical aspects necessary for a successful reliability program. The first issue is correlating junction temperatures between the foundry and the fabless company. The second issue is gauging wafer process sensitivities with respect to standard packaging. The third issue involves tracking changes to the wafer process over time, the effects of the changes, and communication of changes between the fabless company and the wafer foundry. Lastly, a list of specific reliability information commonly requested by fabless companies is presented.
4C.2 Current collapse induced IN AlGaN/GaN HEMTs by SHORT-TERM DC BIAS STRESS—J.A. Mittereder, S.C. Binari, P.B. Klein, J.A. Roussos, D.S. Katzer, D.F. Storm, D.D. Koleske, A.E. Wickenden, and R.L. Henry, Naval Research Lab, Washington, DC
GaN HEMTs grown by MOCVD and by MBE were subjected to short term bias-stress. A current collapse effect was found to be induced in some (but not all) of the devices after stress, apparently caused by the generation of trapping centers.
4C.3 BIAS ACCELERATION MODEL OF DRAIN RESISTANCE DEGRADATION IN INP-BASED HEMTS—Y.K. Fukai, S. Sugitani, T. Enoki, H. Kitabayashi, T. Makimura, Y. Yamane, and M. Muraguchi, NTT Corp., Kanagawa, Japan
Dependence of Rd increase on gate-drain bias will be presented in order to understand the electric field effect of Rd increase. The lifetime to failure of over 1x107 hours at 100°C has been achieved by reducing surface contamination. And reduction of the drain bias will be key for higher reliability of ICs.
4C.4 RELIABILITY CHARACTERISTICS OF P-HEMT RESULTING FROM ELECTRON INTERACTION WITH INTERFACE STATES UNDER THE GATE—S. Mil'shtein, C. Gil, UMASS, Lowell, MA, P. Ersland, M/A-COM, Lowell, MA, and S. Somisetty, UMASS, Lowell, MA
Depleted mode p-HEMT devices were subjected to 3-terminal hot-electron stress, with gate voltage close to the pinch-off and drain voltage slightly below breakdown. Simulation of the bias applied during the stress test results in an electric field profile suggesting the presence of very hot electrons. We compare in current study the results of 2 and 3 terminal test.
Wednesday, April 2, 3:15 p.m. Landmark C
SiGe (4D)
4D.1 (Invited) SiGe HBT PERFORMANCE AND RELIABILITY TRENDS THROUGH FT OF 350 GHz—G. Freeman, J.-S. Rieh, B. Jagannathan, Z. Yang, F. Guarin, A. Joseph, D. Ahlgren, IBM Microelectronics, Hopewell Junction NY
We discuss the SiGe HBT structural changes required for very high performance. The increase in collector concentration, affecting current density and avalanche current, appears to be the most fundamental concern for reliability. By narrowing the emitter, we find that SiGe HBTs may be made reliable to ever increasing performance levels.
4D.2 AVALANCHE CURRENT INDUCED HOT CARRIER DEGRADATION IN 200GHZ SiGe HETEROJUNCTION BIPOLAR TRANSISTORS—Z. Yang, F. Guarin, E. Hostetter, and G. Freeman, IBM Microelectronics, Hopewell Junction, NY
Advanced SiGe HBTs have been investigated under accelerated avalanche stress conditions. The DC degradation of the base current is shown to correlate with the injected charge total and corresponding energy. The base current dependence on avalanche charges and applied voltage is shown, and a model used to predict the parameter degradation within a typical switching application. The impact of this degradation mechanism to fT has also been studied.
4D.3 CHARACTERIZATION OF LIGHT EMISSION FROM SiGe HETEROJUNCTION BIPOLAR TRANSISTOR FOR PHOTON EMISSION MICROSCOPY APPLICATIONS—S. Polonsky, IBM, Yorktown Heights, NY, A. Talalaevskii, SUNY, Stony Brook, NY, and M. McManus, IBM, Yorktown Heights, NY
Light emission from SiGe HBT was characterized for photon emission microscopy applications. Radiative recombination dominates in saturation and non-saturation regimes while hot electron radiation dominates in avalanche and is suppressed at large collector currents due to base widening.
4D.4 THE INFLUENCE OF PROCESS AND DESIGN of subcollectors ON THE ESD ROBUSTNESS OF ESD STRUCTURES AND SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS IN A BICMOS SiGe TECHNOLOGY—S.H. Voldman, L. Lanzerotti, IBM Microelectronics, Essex Junction, VT, B. Ronan, Princeton University, Princeton, NJ, S. St. Onge and J. Dunn, IBM Microelectronics, Essex Junction, VT,
The influence of sub-collector and well on HBM and TLP ESD robustness on SiGe HBT devices, passive derivatives, and novel CMOS/BiCMOS ESD structures is evaluated. An ESD/um rolloff effect, discovery of an lateral collector resistor ballasting, as well as structural /process optimization will be discussed.
4D.5 INVESTIGATION OF ESD DEVICES IN 0.18-µm SiGe BiCMOS PROCESS—S.-S. Chen, T.-Y. Chen, T.-H. Tang, S.-C. Huang, T.-L. Hsu, H.-C. Tseng, J.-K. Chen, United Microelectronics, Hsin-Chu, Taiwan, ROC, and C.-H. Chou, Providence University, Taiwan
This paper investigates the characteristics of ESD devices in 0.18-µm silicon-germanium (SiGe) BiCMOS process including SiGe heterojunction bipolar transistor (HBT), gate-grounded N/PMOS transistors, P-N junction diode in SiGe HBT, P+/N-Well diode, and BiCMOS Deep-Trench (DT) diode. According to this paper, open base configuration in the SiGe HBT has lower trigger voltage and higher ESD efficiency than the gate-grounded N/PMOS. In addition, this paper propose a novel BiCMOS low-leakage DT diode string with controllable blocking voltage for RF-ESD protection designs.
Wednesday, April 2, 2:00 p.m. Landmark D
Product Reliability (4E)
4E.1 DRAM RELIABILITY CHARACTERIZATION BY USING DYNAMIC OPERATION STRESS IN WAFER BURN-IN MODE—I.-G. Kim, S.-K. Choi, J.-H. Choi, and J.-S. Park, University of Tokyo, Tokyo, Japan
Circuit to apply DOS (dynamic operation stress) to DRAM cell in wafer burn in (WBI) mode is successfully implemented and contributes to characterize the reliability of DRAM in wafer level. We verify that the DOS during burn-in(BI) test deteriorates data retention time microscopically, which is mainly attributed to DOS-induced HC(hot carrier) degradation of DRAM cell. In addition, the characterization result of DRAM reliability by DOS-applying method in WBI mode is a good agreement with that by dynamic operation in package burn-in (PBI) mode.
4E.2 CHALLENGES OF TESTING HIGH-VOLUME, LOW-COST 8-BIT MICROCONTROLLERS—M. Stout, K. Tumin, C. Vargas, and B. Gotchall, Motorola, Austin, TX
This paper compares the development and effectiveness of scan-based vs. functional testing using two microcontroller studies. This design-for-test methodology has been shown to reliably produce high quality products. This approach also provides a diagnostic failure analysis methodology that can greatly improve detection of Quality/Reliability failures.
4E.3 CORRELATION OF THE VT DRIFT IN A-SI:H TFT TO THE OPTICALLY OBSERVED FLICKER INCREASE IN AMLCD—C.-C. Huang, J.H. Constable, SUNY, Binghamton, NY, B. Yost, and R.G. Greene, Rainbow Displays, Inc., Endicott, NY
The observed development of flicker with time in AMLCD panels has been correlated to the threshold voltage shift of the thin film transistors (TFTs) used in panels. The effect of a threshold voltage shift on the panel flicker was calculated using a flicker model developed here. One set of AMLCD panels used for the flicker characterization employed top gate TFTs while a second set employed bottom gate TFTs.
4E.4 RELIABILITY QUALIFICATION OF A SMART POWER TECHNOLOGY FOR HIGH TEMPERATURE APPLICATION BASED ON PHYSICS-OF-FAILURE AND RISK & OPPORTUNITY ASSESSMENT—A. Preussger, W. Kanert, Infineon Technologies, Munich, Germany, and W. Gerling, Munich, Germany
As quality requirements in the semiconductor industry increase and costs and time to market put ever more stringent constraints on the development of new technologies and products, more proactive action is needed in the qualification of semiconductor devices. The risk & opportunity assessment is presented as a procedure for qualification of semiconductors that is based on the physics-of-failure concept and the relation of product requirements and the properties of the product and its constituing elements. The applicability of this procedure is illustrated using an example from technology qualification.
4E.5 PRODUCT LEVEL VERIFICATION OF GATE OXIDE RELIABILITY PROJECTIONS USING DRAM CHIPS—R.-P. Vollertsen, K. Nierle, Infineon Technlogies AG, Muenchen, Germany, E.Y. Wu, IBM, Essex Junction, VT, and S. Wen, Infineon Technlogies AG, Muenchen, Germany
Gate oxide reliability of DRAM product is usually predicted from test structures. In order to understand the relevance of these predictions, a verification stress between test structure and product was performed. Long-term stress data of packaged test structures shows consistent behavior with a 1/Vg-model, which could explain the product stress results.
4E.6 INVESTIGATION OF WAFER LEVEL BURN-IN TO SoC MEMORY: 1TRAM—Y.L. Pan, S.H. Chen, C.H. Lu, and J.J. Wang, TSMC, Hsin-Chu, Taiwan
This paper intends as an investigation of Wafer Level Burn-In (WLBI) on retention time of 1TRAM by using a simple and practical gate oxide stress method. We find that the WLBI stress time doesn't influence the degradation of 1TRAM retention time when we continue to increase WLBI stress time. The WLBI shows that the electrical field will cause the electrons trapped in the gate oxide in the initial stage of the total stress time. Then the baking effect of the high temperature environment will recover the damage of the gate oxide like an annealing that decreases the degradation of the retention time in later half time. In this study, modeling of gate oxide reliability is used to predict the stress time for WLBI. In order to make sure whether WLBI mode is successfully implemented or not, the WLBI method will be compared with traditional Package Level Burn-In (PLBI). By using WLBI method, the gate oxide defect of 1TRAM cell array can be screened in wafer level testing and it can also be successfully applied to other memory products.
4E.7 PRACTICAL WLRC METHODOLOGY & APPLICATIONS IN A WAFER FOUNDRY—W.T.K. Chien, S. Chiang, S. Tseng, C.H.J. Huang, K. Yang, W. Wang, and J. Zhou, SMIC, Shanghai, China
As the product life cycle shrinks, the qualification needs to be completed in a much shorter time. This makes WLR an important tool so results can be obtained in much shorter times. The two key issues for WLR are to guarantee the same failure mechanisms to the conventional package-level reliability (PLR) and to maintain statistically acceptable correlation. We report the correlation of WLR and PLR tests and depict WLR Control (WLRC) methodology to ensure in-line reliability/ process stability and to assist new technologies development.
Thursday, April 3, 8:00 a.m. Landmark AB
Gate Dielectric (5A)
5A.1 GROWTH AND SCALING OF OXIDE CONDUCTION AFTER BREAKDOWN—B.P. Linder, J.H. Stathis, D.J. Frank, IBM, Yorktown Heights, NY, S. Lombardo, CNR-IMETEM, Catania, Italy, and A. Vayshenker, IBM, Hopewell Jct., NY
Hard breakdown (HBD) is shown to be a gradual process with the gate current increasing at a predictable rate, exponentially dependent on the instantaneous stress voltage. The scaling of the HBD growth rate with device area, substrate doping, oxide thickness, and channel length are explored.
5A.2 A PHENOMENOLOGICAL THEORY OF CORRELATED MULTIPLE SOFT-BREAKDOWN EVENTS—M.A. Alam, Agere Systems, Berkeley Heights, NJ
The operating lifetimes of Silicon ICs improve geometrically if the gate oxides can survive multiple softbreakdown. However, the precise degree of improvement depends sensitively on any residual correlation among the breakdown events, and even a small increase in the trap generation rate after a breakdown may change the statistics of subsequent breakdown events significantly. In this paper, we develop, for the first time, a theoretical framework to discuss the TDDB reliability in the presence of correlation and show, with concrete examples, how this theory should be interpreted in practice.
5A.3 ANALYSIS OF QUANTUM YIELD IN n-CHANNEL MOSFETS—A.S. Spinelli, University degli Studi dell'Insubria, Como, Italy, D. Ielmini, A.L. Lacaita, Politecnico di Milano, Italy, A. Sebastiani, and G. Ghidini, STMicroelectronics, Agrate Brianza, Italy
By a new technique for carrier separation, we analyze hole SILC and quantum yield (QY) in n-MOSFET. Hole SILC in n-MOSFETS fairly agree with-MOSFETs, indicating that the SILC physics is independent from the type of substrate. We show that, for increasing annealing times and stress dose, the QY is not correlated with stationary SILC, thus cannot be used for probing the energy loss of electrons in the SILC process.
5A.4 TEMPERATURE DEPENDENCE AND CONDUCTION MECHANISM AFTER ANALOG SOFT BREAKDOWN—T. Nigam, S. Martin, and D. Abusch-Magder, Agere Systems, Berkeley Heights, NJ
The current conduction after analog soft breakdown (SBD) is studied as a function of temperature. It is known that transistors are operational after SBD has occurred, but the power dissipation due to enhanced gate leakage is critical. Therefore, it is important to understand the voltage and temperature dependence of gate leakage after SBD. In this work, we show that the electron cotunneling explains the effect of temperature and oxide thickness for current conduction after A-SBD.
5A.5 EVIDENCE FOR DEFECT-GENERATION-DRIVEN WEAR-OUT OF BREAKDOWN CONDUCTION PATH IN ULTRA THIN OXIDES—F. Monsieur, E. Vincent, G. Ribes, STMicroelectronics, Crolles, France, V. Huard, Philips, Crolles, France, S. Bruyère, D. Roy, STMicroelectronic, Crolles, France, G. Pananakakis, and G. Ghibaudo, IMEP/ENSERG, Grenoble, France
The physical mechanisms responsible for the progressive (i.e. smooth or noisy) breakdown manifestation commonly measured on ultra-thin oxides (Tox<25Å) are considered. First, it is verified that the theory previously published is relevant by highlighting progressive behavior predicted on thicker oxides (50Å). Second, the stored energy is shown not to be correlated to the progressive behavior even if it influences the failure and its occurrence. At last, the progressiveness being gate voltage and temperature driven, it is stated that the defect generation probability drives the breakdown degradation after its creation. This is proven by measuring the influence on the progressiveness of a bulk bias applied during the stress of a pMOS in the inversion regime. At last, on the basis of this physical understanding of the progressiveness, an analytical progressiveness modeling is provided. In addition, the final paper will show the use of substrate hot hole devices enabling to understand clearly the link between defect generation probabilities operating before and after the breakdown occurrence as suggested in the conclusion.
5A.6 SOFT BREAKDOWN IN THIN GATE OXIDE _ A MEASUREMENT ARTIFACT—K.P. Cheung, Rutgers University, Piscataway, NJ
Experimental evidences are reported here to show that soft breakdown in ultra thin gate oxide under electrical stress is an experimental artifact induced by the inability to eliminate the current surge at the moment of the formation of a percolation path. Soft breakdown may not happen in real circuit under normal operation.
5A.7 NEGATIVE SUBSTRATE BIAS ENHANCED BREAKDOWN HARDNESS IN ULTRA-THIN OXIDE pMOSFETs—T. Wang, C.W. Tsai, M.C. Chen, C.T. Chan, H.K. Chiang, National Chiao-Tung University, Hsinchu, Taiwan, S.H. Lu, H.C. Hu, C.K. Yang, G.S. Yang, D.Y. Wu, J.K. Chen, S.C. Chien, S.W. Sun, and F. Wen, UMC, Hsinchu, Taiwan
Breakdown hardening in ultra-thin oxide (1.4nm) pMOS devices with negative substrate bias is observed. This hardening is attributed to substrate bias enhanced hole stress current via breakdowninduced carrier heating. Numerical analysis of hole tunneling current and hot carrier luminescence measurement are performed to support the proposed theory. This observed phenomenon is particularly significant to gate oxide reliability in floating substrate (SOI) or substrate biased (DTMOS) devices.
Thursday, April 3, 8:00 a.m. Landmark C
Packaging (5B)
5B.1 (Invited) WHEATSTONE BRIDGE METHOD FOR ELECTROMIGRATION STUDY OF SOLDER BALLS IN FLIP-CHIP PACKAGES—M. Ding, H. Matsuhashi, P.S. Ho, The University of Texas at Austin, Austin, TX, A. Marathe, R.N. Master and V. Pham, Advanced Micro Devices, Sunnyvale, CA
In this paper, we describe a new approach and a new system developed for electromigration tests of solder balls in packaging assembly. The approach is based on the Wheatstone Bridge method, which provides significant improvement in the sensitivity for detecting EM damage in solder balls. This method has been successfully demonstrated for EM test of high Pb (97Pb-Sn) solder balls in ceramic flip-chip packages.
5B.2 BOARD LEVEL SOLDER RELIABILITY vs RAMP RATE & DWELL TIME DURING TEMPERATURE CYCLING—C. Zhai, Sidharth, and R.C. Blish, AMD, Sunnyvale, CA
Board level FEA modeling and experimental results show solder joint fatigue life is more sensitive to dwell time than ramp rate during thermal cycling. Our focus should NOT be on number of chambers, nor upon ramp rate, but upon dwell time. We recommend 8-10 minutes dwell at 125 C.
5B.3 A SIMPLE MODEL FOR THE MODE II POPCORN EFFECT IN THIN PLASTIC IC PACKAGES—P. Alpern, Infineon Technologies, Munich, Germany and K.C. Lee, Infineon Technologies Asia Pacific Pte Ltd., Singapore
A simple model for the mode II popcorn effect is presented here for thin packages. A package "stability parameter", relating to its moisture sensitivity, is derived from the popcorn model. It describes the influence of materials properties and package design parameters on the robustness of the package when it is subjected to soldering shock. Furthermore, nomograms generated from the model enable for the first time an easy estimation of the mode II moisture sensitivity level for soldering temperatures up to 260°C (Pb-free soldering).
5B.4 ADVANCED GETTER SOLUTIONS AT WAFER LEVEL TO ASSURE HIGH RELIABILITY TO THE LAST GENERATIONS MEMS—M. Moraja, M. Amiotti, SAES Getters SpA, Lainate, Italy, and R.C. Kullberg, SAES Getters SpA, Colorado Springs, CO
Getter films are needed inside wafer to wafer bonded MEMs cavities to assure long reliability under vacuum. Depositing appropriate getter films, few microns thick, with controlled geometries and with no loose particles onto the MEMs cap wafers satisfies these needs. This new approach is described.
Thursday, April 3, 10:05 a.m. Landmark C
Mems (5C)
5C.1 (Invited) Instrumentation for Genome Analysis (and beyond) based on the TI Digital Micromirror Device—H. Garner, UT Southwestern Medical Center, Dallas, Tx
This extended abstract will present an overview of various MEMS applications in the biological and medical research field. Specific examples will use the Digital Micromirror Device (DMD) developed by Texas Instruments. The University of Texas Southwestern Medical Center develops instrumentation and computational biology tools to exploit the emerging biomedical databases. We apply these tools to problems in biology, genetics, genomics, and medicine. The field of bioMEMS merges biology, physics, mathematics, engineering, computer science and clinical medicine.
5C.2 EFFECT OF Al2O3 ALD NANOCOATINGS ON THE THERMO-MECHANICAL BEHAVIOR OF Au/Si MEMS STRUCTURES—K. Gall, M.L. Dunn, M. Hulse, Y. Zhang, and S.M. George, University of Colorado, Boulder, CO
We examine the thermo-mechanical behavior of multilayer Au/Si structures used in MEMS. We consider beam-like structures with and without Atomic Layer Deposition (ALD) nanocoatings. Uncoated samples show creep and stress-relaxation during thermal hold periods and ratcheting during thermal cycling. Under some thermal loading conditions, the ALD nanocoatings suppress the aforementioned degradation mechanisms.
5C.3 EFFECTS OF OPERATING CONDITIONS ON DMD HINGE MEMORY LIFETIME—A.B. Sontheimer and D.J. Mehrl, Texas Instruments, Plano, TX
This paper will show how different operating conditions improve hinge memory lifetime of the Digital Micromirror Device (DMD). The correlation of parametric measurements to physical properties will also be developed. Specific operating conditions explored include the effects of (1) on/off duty cycle, (2) relaxation during non-operation and (3) reversibility on hinge memory lifetime performance.
5C.4 RELIABILITY OF MEMS-BASED MASS-FLOW CONTROLLERS FOR SEMICONDUCTOR PROCESSING—E. Lawrence and A.K. Henning, Redwood Microsystems, Menlo Park, CA
Microfabricated components are finding increasing application in semiconductor processing. We report detailed reliability and MTTF studies on mass-flow controllers created from silicon pressure sensors and microvalves. Attributes studied include accuracy, response time, inboard and outboard leak rate, and particle generation. MTTF is greater than 3M cycles. Failure modes are discussed.
5C.5 ON-CHIP MONITORING OF MEMS GEAR MOTION—D.M. Tanner, S.E. Swanson, and J. Dohner, Sandia National Labs, Albuquerque, NM
An on-chip technique for sensing MEMS gear motion has been demonstrated using two switch designs, both small enough to fit between gear teeth. The high polysilicon contact resistance was circumvented by monitoring the voltage change of a constant-current source when sliding contact was made between the activated switch pad and grounded contact.
Thursday, April 3, 2:00 p.m. Landmark AB
Memory (6A)
6A.1 VARIABLE STRESS-INDUCED LEAKAGE CURRENT AND ANALYSIS OF ANOMALOUS CHARGE LOSS FOR FLASH MEMORY APPLICATION—R. Yamada, Hitachi Ltd, Tokyo, Japan, and T.-J. King, University of California, Berkeley, CA
The random telegraph noise (RTN) behavior in SILC is found in small (<1x102 µm) MOS capacitor. The time dependence of SILC in small MOS capacitors is due to RTN current associated with multi-trap assisted tunneling. Multi-TAT involving three or more traps in each conduction path can account for anomalous charge loss in flash memory cells.
6A.2 DEGRADATION OF TUNNEL OXIDE BY FN CURRENT STRESS AND ITS EFFECTS ON DATA RETENTION CHARACTERISTICS OF 90-nm NAND FLASH MEMORY CELLS—J.-D. Lee, J.-H. Choi, D. Park, and K. Kim, Samsung Electronics, Gyunggi-Do, Korea
We have verified that interface trap generation rates increases as the transistor width decreases below 100 nm for the NAND flash memory. The major failure mechanism of the data retention of 90-nm cell transistors is the relaxation of interface traps, which consist of fast traps and the slow traps.
6A.3 DATA RETENTION, ENDURANCE AND ACCELERATION FACTORS OF NROM™ DEVICES—M. Janai, Saifun Semiconductors Ltd., Netanya, Israel
Results of reliability studies of NROM™ devices are presented. High temperature storage life tests indicate minimal acceleration factors of 104 to 106 relative to ambient operation conditions. The implications to NROM product qualification methodology are discussed.
6A.4 STUDY OF DATA RETENTION FOR NANOCRYSTAL FLASH MEMORIES—C.M. Compagnoni, D. Ielmini, A.S. Spinelli, A.L. Lacaita, C. Previtali, Politecnico di Milano, Italy, and C. Gerardi, STMicroelectronics, Catania, Italy
We studied retention in nanocrystal memories. Experimental data shows that no appreciable degradation in nanocrystal retention after extended cycling up to 106 cycles is found. Numerical modeling of charge loss indicates that 10-year retention for tunnel oxide thickness of 6 nm can be achieved below 1012 cm-2 node density, even with large SILC in one dot.
6A.5 AN ENHANCED ERASE MECHANISM IN FLASH MEMORY AND ITS IMPLICATION ON ENDURANCE RELIABILITY—J.M.Z. Tseng, B.J. Larsen, Y. Xiao, J. Yount, T. Randazzo, S. Shore, G. Miller, and D.A. Erickson, Atmel Corp, Colorado Springs, CO
An enhanced erase mechanism in flash memory by increasing the generation of holes through impact ionization is described. The endurance degradation associated with this erase mechanism is found to be different from those using the conventional source-side erase methods, as the better erase margin and worse program degradation are observed. The improvement of erase margin is then investigated by using a special cell structure with access to the floating gate and is explained in terms of injection efficiency of hot holes.
6A.6 EFFECT OF PROGRAMMING BIASES ON THE RELIABILITY OF CHE AND CHISEL FLASH EEPROMS—N.R. Mohapatra, S. Mahapatra, V.R. Rao, Indian Institute of Technology, Bombay, India, S. Shukuri, Hitachi Ltd., and J. Bude, Agere Systems, Berkeley Heights, NJ
Cycling induced degradation is studied in flash EEPROMs under CHE and CHISEL operation. CHE degradation increases at higher control gate bias (VCG) and is insensitive to drain bias (VD) change. CHISEL degradation is insensitive to changes in both VCG and VD. CHISEL always shows lower degradation when compared to CHE under identical bias or programming time.
Thursday, April 3, 1:35 p.m. Landmark C
Failure Analysis (6B)
6B.1 (Invited ESREF) A Novel Thermomechanics-Based Lifetime Prediction Model for Cycle Fatigue Failure Mechanisms in Power Semiconductors—M. Ciappa, W. Fichtener, Integrated Systems Laboratory, ETH Zurich, Switzerland, F. Carbognani, and P. Cova, University of Parma, Italy
6B.2 HIGH RESOLUTION BACKSIDE FAULT ISOLATION TECHNIQUE BY DIRECTLY FORMING Si SUBSTRATE INTO SOLID IMMERSION LENS—T. Koyama, E. Yoshida, J. Komori, Y. Mashiko, and T. Nakasuji, Mitsubishi Electric. Co., Hyogo, Japan
We developed a new backside fault isolation technique based on the concept of solid immersion lens, which can be applied for the technology node of 90 nm. This technique can dramatically improve spatial resolution and also sensitivity in the conventional techniques by directly forming the Si substrate into a hemisphere.
6B.3 RELIABILITY ISSUES AND ADVANCED FAILURE ANALYSIS TECHNQUES FOR COPPER/LOW-K—H. Wu, J. Cargo, C. Peridier, J.Serpiello, and J. McGinn, Agere Systems, Allentown, PA
New failure modes, reliability issues and failure analysis (FA) challenges for copper technology will be discussed firstly. Several FA deprocessing techniques and will be discussed: wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combination of these techniques. In addition, the detailed characterization and optimization of the RIE process for several inter-level dielectrics etching will be carried out. High etch selectivity, free of RIE grass and clean surfaces can be achieved. We found the combination of CMP and RIE deprocessing techniques works well for most situations for copper technologies. Cross-section analysis of copper devices will be also discussed. The development of reproducible backside silicon sample preparations techniques has be come increasingly important to accurately localize defects for Cu/Low-k technology. In this work, several backside sample preparation techniques will be discussed including mechanical milling, RIE, and wet chemical etching. Finally, some FA case studies of Cu/Low-k devices will be discussed.
6B.4 AUTOMATED PICA TRANSISTOR CHANNELING AND SPATIAL-TEMPORAL PHOTON CORRELATION FOR FASTER IC DIAGNOSIS—R. Desplats, F. Beaudoin, G. Faggion, O. Jesson, P. Perdu, CNES- French Space Agency, Toulouse, France, M. Leibowitz, T. Lundquist, and K. Shaht, NPTest, San Jose, CA
Debug of the latest ICs may be tackled with PICA (Picosecond Imaging Circuit Analysis). However, the acquisition time can be long even taking several hours. We have developed a novel approach called auto-channeling, based on the known physics of hot carrier induced photon emission which makes it possible to obtain results in minutes.
6B.5 LASER INTERACTION WITH SiCr THIN FILM RESISTORS (T.F.R.) _ THE BUBBLE THEORY—E. Coyne and D. Sheahan, Analog Devices, Limerick, Ireland
This paper introduces a theoretical model to qualitatively describe the mechanisms involved during laser trimming of SiCr (Silicon Chromium) thin film resistors. The model was developed to address the problems encountered when trying to cut these resistors. It is based upon the physical laws of laser-matter interaction and extrapolates them to the confines of a thin film resistor. This was done with planar tem images of the laser cut thin film resistors to provide support for the theory. With this model it was then possible to recommend and implement solutions about the design of the SiCr thin film in order to enhance its capabilities as a potential laser trim tab or thin film fuse.
6B.6 A NEW APPROACH TO DETECT SMALL-SIZED OXYGEN PRECIPITATES IN Si WAFERS USING REACTIVE ION ETCHING—K. Nakashima, T. Yoshida, Y. Watanabe, and Y. Mitsushima, Toyota, Nagakute-chu, Japan
A new technique to detect oxygen precipitates in Si wafers using highly selective RIE is presented. This technique is capable of detecting nanometer-sized precipitates and evaluating their size and morphology. Relations of the size or density of oxygen precipitates to OSF formation and GOI characteristics is demonstrated using this technique.
6B.7 CONSISTENCY OF OPTICAL DATA FROM PICA—T. Lundquist, K. Shah, A. Abraham, NPTest, Inc., San Jose, CA, and W. Ng, National Semiconductor Corp., Santa Clara, CA
Parallel collection of photon emission data from CMOS ICs for timing analysis has been the primary value of PICA. Emission duration seems related to circuit and transistor structure. To understand potential uses of this information, we investigate the consistency of this PICA data from one transistor to another.
Tuesday, April 1, 7:00 p.m. Union Station
Circuits (CR)
CR.1 A METHOD TO COMPREHEND THE IMPACT OF INTERCONNECT COUPLING EFFECTS ON GATE OXIDE RELIABILITY—A.A. Mutlu and P. Aminzadeh, Intel Corp., Santa Clara, CA
A method to quantify the interconnect coupling effects on gate oxide reliability is developed. Post-layout noise waveform at each gate node is obtained by using TCAD noise simulation tools. These waveforms are used to determine an average time to fail (TTF), which is eventually used in gate oxide failure probability calculations. Additionally, it is translated to DC equivalent voltage (DCEV) for quantification of the coupling impact in terms of voltage.
CR.2 ARET FOR SYSTEM-LEVEL IC RELIABILITY SIMULATION—X. Xuan, A. Chatterjee, Georgia Institute of Technology, Atlanta, GA, and A.D. Singh, Auburn University, Auburn, AL
In order to evaluate the reliability of post-fabrication ICs with physical defect and accomplish design-for-reliability based on system-level reliability simulation, a simulator ARET is developed. By focusing on system-level simulation, ARET integrates the device-level physics -of-failure models such as electromigration model for defective IC interconnect and hot-carrier model for CMOS transistors, with system-level models such as hierarchical model, probability model, and dig ital circuit delay model.
Tuesday, April 1, 7:00 p.m. Union Station
Compound Semiconductors (CS)
CS.1 DRAIN AVALANCHE BREAKDOWN AND GATE INSTABILITIES IN 4H-SiC MESFET's—H. Lv, Y. Zhang, and Y. Zhang, Xidian University, Shaanxi, China
The breakdown characteristic of 4H-SiC MESFET is simulated with a two-carriers model. The simulation results are considerately accurate using the impact ionization, thermal equation and anisotropy models. The breakdown mechanism is explained in terms of impact and conductivity modulation. The thermal effect and gate-bias dependence of the breakdown are analyzed in detail.
CS.2 A STUDY ON GaAs FET's FAILURE MECHANISM AND EXPERIMENTAL TECHNOLOGY OF RAPID EVALUATION OF RELIABILITY—L. Zhiguo, S. Zengchao, S. Dapeng, C. Yaohai, Z. Zhongrong, and Z. Wanrong, Beijing Polytechnic University, Bejing, China
When conducting accelerating life test with temperature as an accelerating stress, both domestic and abroad researchers apply for Arrhenius equation. This conventional method needs many samples, long experimental cycle time. Our new method bases on the temperature characteristic of IDSS which is a sensitive parameter to failure of GaAs FET and the degradation characteristic of devices under certain electro-thermo stress. With this new method we can extract the information of relationship between degradation of IDSS and temperature rapidly and on line, therefore some reliability parameters of GaAs FET can be figured out promptly, such as activating energy to failure Q, etc.
Tuesday, April 1, 7:00 p.m. Union Station
Device Dielectrics (DI)
DI.1 A PROPER LIFETIME-PREDICTION METHOD OF MOSFET WITH 1.1 nm GATE DIELECTRICS IN THE LOWER TESTING VOLTAGE REGION—N. Tamura and M. Kase, Fujitsu Ltd., Tokyo, Japan
We firstly found that TDDB lifetime of 1.1 NM gate dielectrics with the low voltage behavior of defect generation probability was ten times longer than that with high voltage ones and the voltage dependence of lifetime is power-law. This is explained by a new model, which incorporates both hole and electron.
DI.2 EXPERIMENTAL STUDY AND MODELING OF THE TEMPERATURE DEPENDENCE OF SOFT BREAKDOWN CONDUCTION IN ULTRATHIN GATE OXIDES—A. Avellán, Technische Universität Hamburg-Harburg, Hamburg, Germany, E. Miranda, Universidad de Buenos Aires, Buenos Aires, Argentina, B. Sell, Infineon Technologies AG, Dresden, Germany and W. Krautschneider, Technische Universität Hamburg-Harburg, Hamburg, Germany
A thorough experimental analysis of both voltage and temperature dependence of the soft breakdown current for a wide variety of samples and a simple and compact model reproducing the experimental curves is presented. The model's suitability for circuit simulation opens the perspective to determine the impact of soft breakdown on circuit behavior.
DI.3 VOLTAGE-DRIVEN DISTRIBUTION OF GATE OXIDE BREAKDOWN—A. Hiraiwa, S. Sakai, and D. Ishikawa, Hitachi, Ltd., Tokyo, Japan
The distribution of gate oxide breakdown is not driven by the conventionally-proposed thickness but by the gate voltage, and follows the minimum distribution of a lognormal stochastic variable. These new findings will be a key basis for investigating the reliability thinning limit.
Tuesday, April 1, 7:00 p.m. Union Station
Device & Process (DP)
DP.1 DBIE SHAPE AND HARDNESS DEPENDENCE ON GATE OXIDE BREAKDOWN LOCATION IN MOSFET CHANNEL—K.L Pey, Nanyang Technological University, Singapore, C.H. Tung, Institute of Microelectronics, Singapore, M.K. Radhakrishnan, Philips Electronics, Singapore, L.J. Tang, Institute of Microelectronics, Singapore, and W.H. Lin, Chartered Semiconductor Mfg. Ltd., Singapore
Dielectric-breakdown-induced-epitaxy (DBIE) in ultrathin gate oxides is dependent on breakdwon spot along transistor channel. While breakdowns near channel edge result in subtle and sharp DBIE for hard and soft failures, breakdowns near channel center lead to large and rounded DBIE only for soft failures. Channel resistance is the controlling parameter.
DP.2 DEFECT PASSIVATION AND DARK COUNT IN GEIGER-MODE AVALANCHE PHOTODIODES—J.C. Jackson, G. Healy, A-M. Kelleher, J. Alderman, J. Donnelly, P.K. Hurley, NMRC, Cork, Ireland, A.P. Morrison, University College Cork, Cork, Ireland, and A. Mathewson, NMRC, Cork, Ireland
An experimental study of post metal anneal conditions on dark count in Geiger-mode avalanche photodiodes (GM-APD) has been performed. The GM-APD structure will be shown to be extremely sensitive to post-metal anneals. Dark counts from measured samples decreased by a factor of two for each separate anneal in forming gas. Conversely anneals in ambient increased dark count for temperature cycles from 2 to 124 hours. Passivation and de-passivation of defect sites within the shallow junction active area are suspected as mechanisms contributing to the variations in dark count.
Tuesday, April 1, 7:00 p.m. Union Station
Failure Analysis (FA)
& David H. Su, TSMC
FA.1 LOCALIZATION AND ANALYSIS OF FUNCTIONAL FAILURES IN DEEP SUBMICRON ADVANCED ASIC PRODUCTS—M. Rubin, Agilent Technologies, Singapore
The problem of analyzing and identifying functional failures in modern ASIC designs becomes more challenging when the products are manufactured at the remote foundry. This paper addresses this issue in details and describes the novel approach for localization and failure analysis of functional failures. The new method, proposed and verified, does not require special equipment or test development. The paper also addresses the yield improvement methodology in foundry environment based on the described techniques and provides illustrative case studies.
FA.2 withdrawn
FA.3 FIB-INDUCED DEPOSITION OF INTERMEDIATE RESISTIVITY MATERIAL FOR DESIGN DEBUGGING—G.Y. Gu, N.J. Bassom, J.D. Casey, Jr., L. Scipioni, A. Saxonis, and C. Huynh, FEI Co., Peabody, MA
Recently, we have developed a process for the FIB deposition of material with a resistivity of 1-2 ×106 µohm-cm by combining W(CO)6 and TMCTS as precursors. Auger electron (AES) and energy-dispersive (EDS) spectroscopy indicate the presence of Si, Ga, W, C, and O. FIB secondary electron cross section imaging indicates that the film is single phase. The material shows excellent I-V linearity over a potential range of exceeding ±10 volts. It is also stable at ambient condition for several months and does not degraded after being stressed by either temperature or electrical current.
Tuesday, April 1, 7:00 p.m. Union Station
High K Dielectrics (HK)
HK.1 TEMPERATURE DEPENDENT CURRENT AND CHARGE TRAPPING IN THICK SiO2/ZrO2 STACKS—P. Blomme*, B. Govoreanu*, J. Van Houdt, and K. De Meyer*, IMEC, Leuven, Belgium *also with KULeuven
The influence of charge trapping on the temperature dependence of leakage through SiO2/ZrO2 is investigated, showing that temperature dependence of the leakage current can be explained by tunneling wherein the trapped charge alters the barrier for tunneling, not necessarily implying defect assisted leakage current.
Tuesday, April 1, 7:00 p.m. Union Station
Interconnects (IT)
IT.1 EFFECT OF CURRENT DIRECTION ON THE RELIABILITY OF MULTI-TERMINAL Cu DUAL-DAMASCENE INTERCONNECT TREES—C.L. Gan, Singapore-MIT Alliance, Singapore, C.V. Thompson, Massachusetts Institute of Technology, Cambridge, MA, K.L. Pey, Nanyang Technological University, Singapore, W.K. Choi, National University of Singapore, Singapore, C.W. Chang, Singapore-MIT Alliance, Singapore, and Q. Guo, Institute of Microelectronics, Singapore
While the reliability of a dual-damascene via is independent of the number of segments connected to it, it is strongly dependent on the distribution of current among the segments. The most highly stressed segments are not always the least reliable. This behavior for Cu is different than for Al.
IT.2 REAL CASE STUDIES OF FAILURE MECHANISMS FOR Cu TRENCH ELECTROMIGRATION—J.B. Lai, J.L. Yang, H.W. Yang, R.L. Hwang, D. Su, H. Chuang, and Y.S. Huang, TSMC, Hsin-Chu, Taiwan, ROC
Tuesday, April 1, 7:00 p.m. Union Station
Beol Dielectrics (LK)
LK.1 TDDB AND VOLTAGE-RAMP RELIABILITY OF SiC-BASED DIELECTRIC DIFFUSION BARRIERS IN Cu/LOW-K INTERCONNECTS—K. Jow, Massachusetts Institute of Technology, Cambridge, MA, G. Alers, M. Sanganeria, G. Harm, H. Fu, X. Tang, G. Kooi, G. Ray, M. Danek, Novellus Systems, San Jose, CA
The correlation between constant voltage and voltage-ramped breakdown testing is investigated. A continuous linear extrapolation between these tests confirms a similar breakdown mechanism. Variations of the dielectric barrier composition were correlated to changes in the field extrapolation parameter. Failure analysis revealed a breakdown mechanism that was physical in origin.
Tuesday, April 1, 7:00 p.m. Union Station
Product Reliability (PR)
& Nick E. Lycoudes, Motorola
PR.1 DEFECT BASED TESTING WITH NEW ISB CURRENT STRATEGY—B. Lisenker, Intel Israel Ltd., Haifa, Israel
It is shown that in dip-sub-micron CMOS products BI conditions can cause degradation of outgoing material because the electrical characterization of such material gives electrical signatures that correspond to integrated defect mechanisms. It is a reason to replace Burn-in test by a test that incorporates its past screening power with new techniques designed to improve cost efficiency and reduce the damage level of the outgoing material. Sampling BI with BI time adapts to reliability risk is the first step to BI elimination. Standby current versus Vcc voltage technical is a good way for unit's separation and reliability risk estimation.
PR.2 WAFER LEVEL RELIABILITY MONITORING STRATEGY OF AN ADVANCED MULTI-PROCESS CMOS FOUNDRY—A. Scarpa and G. Tao, Philips Semiconductors, Nijmegen, The Netherlands
In an advanced multi-process CMOS foundry it is strategically important to make use of an optimum reliability monitoring strategy, in order to be able to run well controlled processes. Philips Semiconductors Business Unit Foundries wafer fab MOS4YOU has developed an end-of-line ultra-fast reliability monitoring strategy, which provides a very fast and continuous feedback to the production line. In this work the advantages of such strategy are discussed by means of example cases, including hot-carrier reliability and a new end-of-line monitoring tool for non-volatile memory reliability.
PR.3 PROCESS QUALIFICATION STRATEGY FOR ADVANCED EMBEDDED NON-VOLATILE MEMORY TECHNOLOGY _THE PHILIPS' 0.18 µm EMBEDDED FLASH CASE—G. Tao, A. Scarpa, K. van Dijk and F.G. Kuper, Philips Semiconductors, Nijmegen, The Netherlands
Advanced embedded non-volatile memory technology is often a very complex technology. It uses of advanced STI isolation, multiple gate oxides, various well structures, advanced salicides, high number of metal layers, and low-K dielectrics, etc. It is a great challenge to timely qualify such processes with a good coverage of all the possible failure modes. In this paper, we report our strategy used in the successful qualification of Philips' 0.18µm embedded flash technology.
Tuesday, April 1, 7:00 p.m. Union Station
Transistors (TR)
TR.1 TRANSIENT EFFECTS AND CHARACTERIZATION METHODOLOGY OF NEGATIVE BIAS TEMPERATURE INSTABILITY IN pMOS TRANSISTORS—M. Ershov, R. Lindley, S. Saxena, A. Shibkov, S. Minehane, J. Babcock, S. Winters, H. Karbasi, and T. Yamashita, PDF Solutions, San Jose, CA
NBTI degradation in pMOSFETs is shown to be partially reversible, i.e. the amount of apparent degradation measured after stress interruption depends strongly on the time delay between stress and measurement. This effect has very important consequences for establishing a correct NBTI characterization procedure.
TR.2 DESIGN OPTIMIZATION OF N-LDMOS TRANSISTOR ARRAYS FOR HOT CARRIER LIFETIME ENHANCEMENT—D.J. Brisbin, A. Strachan, and P. Chaparala, National Semiconductor, Santa Clara, CA
Smart power management devices often require high voltage (20-30V) operation. These devices often are implemented in a high performance BICMOS process with a lateral-n-channel DMOS (N-LDMOS) driver. To achieve high drive current density and minimal on -resistance, LDMOS devices are implemented in transistor arrays. Because of the high voltages applied to these LDMOS arrays hot carrier degradation is a real reliability concern. This paper differs from previous work in that it discusses for the first time the multi-dimensional (1-D AND 2-D) ASPECTS of LDMOS transistor array layout on hot carrier performance. In addition this paper introduces for the first time a novel LDMOS transistor layout featuring a drain ring that dramatically improves the HC performance of these arrays.
TR.3 TIME AND VOLTAGE DEPENDENCE OF DEGRADATION AND RECOVERY UNDER PULSED NEGATIVE BIAS TEMPERATURE STRESS—H. Usui, M. Kanno, and T. Morikawa, Sony Corp., Tokyo, Japan
In order to simulate reliability impact on the deep sub-micron LSI. Time and voltage dependence of negative bias temperature instability (NBTI) under pulsed stress for p-MOSFET is reported with two uniform degradation stages, a uniform recovery stage and a DC NBTI like degradation.
TR.4 THE STUDY OF COMPRESSIVE AND TENSILE STRESS ON MOSFET's I-V, C-V CHARACTERISTICS AND IT'S IMPACTS ON HOT CARRIER INJECTION AND NEGATIVE BIAS TEMPERATURE INSTABILITY—J.R. Shih, Y.M. Lin, Ken Wu, Y. Peng and J.T. Yue, TSMC, Hsin-Chu, Taiwan, ROC
This paper study the effects of compressive and tensile stresses from etch stop layer on DC and AC characteristics of IO n-/p-MOSFETs, and its impacts on HCI and NBTI. Thermal SIN deposition not only increase the Idsat, but also results in worse Vt roll-off for nMOSFETs and Poly depletion effect on pMOSFETs. Thermal SIN film will also result in serious HCI and NBTI lifetime degradation.