Symposium Opening: General Chair: Eric S. Snyder, Sandia Technologies and Technical Program Chair: Timothy A. Rost, Texas Instruments

Foundry technology reliability—Shang-yi Chiang Ph.D., Sr. VP, Head, R & D Group, TSMC

Technology & reliability challenges at integrated device manufacturers—Mark Bohr, Intel Fellow, Tech. & Mfg Group, Dir., Process Architecture & Integration

CIRCUITS (New Session Intro)

Effect of gate oxide breakdown on RF device and circuit performance—H. Yang, J.S. Yuan, and E. Xiao

On the degradation of P-MOSFETS in analog and RF circuit under inhomogeneous negative bias temperature stress—C. Schlünder et al.

Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters—R. Rodríguez, J.H. Stathis, and B.P. Linder

Behavior of NBTI under AC dynamic circuit conditions—W. Abadeer and W. Ellis

(Invited) Stress polarity dependence of degradation and breakdown of SiO₂/high-k stacks—R. Degraeve et al.

Accurate reliability evaluation of non-uniform ultrathin oxynitride and high-k layers—P. Roussel et al.

Novel dielectric breakdown model of Hf-silicate with high temperature annealing—T. Yamaguchi et al.

Characterization of the VT instability in SiO₂/HfO₂ gate dielectrics—A. Kerber et al.

Dynamic reliability characteristics of ultra-thin HfO₂—Y.H. Kim et al.

SER (New Session Introduction)

(Invited) Neutron-induced latchup in SRAMs at ground level—P.E. Dodd et al.

Measuring the width of transient pulses induced by ionising radiation—M. Nicolaidis and R. Perez

A systematic approach to SER estimation and solutions—H.T. Nguyen and Y. Yagil

Contribution of device simulation to SER understanding—J-M. Palau et al.

(Invited) Latchup in CMOS—W.H. Morris

A new I/O signal latchup phenomenon in voltage tolerance ESD protection circuits—J. Salcedo-Suner et al.

Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of electrostatic discharge & latchup—A. Weger et al.

A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD Protection—A. Concannon et al.

A 90nm CMOS technology with modular quadruple gate oxides for advanced SoC applications—M. R. Mirabedini et al.

112

Detailed Investigation of the Transient Local Tunneling in Gate Oxides—M. F. Beug, R. Ferretti, and K. R. Hofmann

Abnormal Gate Oxide Thickening at Active Edge with SiN-Linered Shallow Trench Isolation—K.-S. Lee et al.

Using the Temperature Coefficient of the Resistance (TCR) as Early Reliability Indicator for Stressvoiding Risks in Copper Interconnects—A. von Glasow et al.

A study in flip-chip UBM/bump reliability with effects of Sn-Pb solder composition—J.D. Wu et al.

Line depletion electromigration characteristics of Cu interconnects—B. Li, T.D. Sullivan, and T.C. Lee

The influence of the SiN-cap process on the electromigration and stressvoiding performance of dual damascene copper interconnects—A. von Glasow et al.

Electromigration improvement with CVD TiN(Si) barrier in copper dual damascene structures—A. Vijayendran et al.

Stress-induced voiding and its geometry dependency characterization—K.Y.Y. Doong et al.

On the use of highly accelerated electromigration tests (SWEAT) on copper—A.E. Zitzelsberger et al.

Session 3B

BEOL DIELECTRICS

- - -

• 3B.1

(Invited) Leakage, Breakdown, and TDDB Characteristics of Porous Low-k Silica-Based Interconnect Dielectrics—E.T. Ogawa et al.

166

• 3B.2

The effect of low-K ILD on the electromigration reliability of Cu interconnects with different line lengths—C.S. Hau-Riege, A.P. Marathe, and V. Pham

Session 3C

TRANSISTORS (3C.1and 3C.2 Cancelled)

- - -

• 3C.3

Collapse of MOSFET drain current after soft breakdown and its dependence on the transistor aspect ratio W/L—A. Cester et al.

189

• 3C.4

Dynamic NBTI of PMOS transistors and its Impact on MOSFET lifeline—G. Chen et al.

196

• 3C.5

An improved interface characterization technique for a full-range profiling of oxide damage in ultra-thin gate oxide CMOS devices—S.-J. Chen et al.

203

• 3C.6

Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics—A. Shanware et al.

208

• 3C.7

Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors—P. Moens et al.

214

Session 3D

- - -

• 3D.1

(Invited) ESD Challenges in Magnetic Recording: Past, Present and Future—A. Wallash

222

• 3D.2

Impact of scaling on the high current behavior of RF CMOS technology—G. Boselli et al.

229

• 3D.3

Internal behavior of BCD ESD protection devices under very-fast TLP stress—M. Blaho et al.

235

• 3D.4

Moving current filaments in ESD protection devices and their relation to electrical characteristics—D. Pogany et al.

241

• 3D.5

Modeling of temperature dependent contact resistance for analysis of ESD reliability—K.-H. Oh et al.

249

• 3D.6

Dynamic substrate resistance snapback triggering of ESD protection devices—V. Vassilev et al.

256

• 3D.7

Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design—V.A. Vashchenko et al.

261

• 3D.8

The failure mechanism of the high voltage tolerance IO buffer under ESD—J.-H. Lee et al.

269

Session 4A

BEOL DIELECTRICS

- - -

• 4A.1

(Invited) Leakage Behavior and Reliability Assessment of Tantalum Oxide Dielectric MIM Capacitors—T. Remmel, R. Ramprasad, and J. Walls

277

• 4A.2

A physical model of time-dependent dielectric breakdown in copper metallization—W. Wu, X. Duan, and J.S. Yuan

282

• 4A.3

Cu ion migration phenomena and its influence on TDDB lifetime in Cu metallization—J. Noguchi et al.

287

• 4A.4

Reliability and electric properties for PECVD a-SiNx:H films with an optical band-gap from 2.5 to 5.38eV—M.H.W.M. van Delden and P.J. van der Wel

293

Session 4B

DEVICE & PROCESS

- - -

• 4B.1

HSG storage capacitor dielectric reliability of 0.13 µm embedded DRAM CMOS technology—S. Bruyère et al.

298

• 4B.2

New process damage during the etching of small-contact on long floating conductor layer—J. Choi et al.

303

• 4B.3

NMOS predope enhance off-state leakage current—K.Y. Lim, J. Lee, and E. Quek

307

• 4B.4

1/f noise degradation caused by Fowler-Nordheim tunneling stress in MOSFETs—M. Toita et al.

313

Session 4C

COMPOUND SEMICONDUCTORS

- - -

• 4C.1

(Invited) Semiconductor Reliability Challenges from the Fabless Company Perspective—T.M. Kole

318

• 4C.2

Current collapse induced in AlGaN/GaN HEMTs by short-term DC bias stress—J.A. Mittereder et al.

320

• 4C.3

Bias acceleration model of drain resistance degradation in InP-based HEMTs—Y.K. Fukai et al.

324

• 4C.4

Reliability characteristics of p-HEMT resulting from electron interaction with interface states under the gate—S. Mil'shtein et al.

329

SiGe

- - -

• 4D.1

(Invited) SiGe HBT Performance and Reliability Trends through fT of 350GHz—G. Freeman et al.

332

• 4D.2

Avalanche current induced hot carrier degradation in 200GHz SiGe heterojunction bipolar transistors—Z. Yang et al.

339

• 4D.3

Characterization of light emission from SiGe heterojunction bipolar transistor for photon emission microscopy applications—S. Polonsky et al.

344

• 4D.4

The influence of process and design of subcollectors on the ESD robustness of ESD structures and silicon germanium heterojunction bipolar transistor in a BiCMOS SiGe Technology—S.H. Voldman et al.

347

• 4D.5

Investigation of ESD devices in 0.18-µm SiGe BiCMOS process—S.-S. Chen et al.

PRODUCT RELIABILITY

- - -

• 4E.4

Reliability qualification of a smart power technology for high temperature application based on physics-of-failure and risk & opportunity assessment—A. Preussger et al.

378

• 4E.5

Product level verification of gate oxide reliability projections using DRAM chips—R.-P. Vollertsen et al.

385

• 4E.1

DRAM reliability characterization by using dynamic operation stress in wafer burn-In mode—I.-G. Kim et al.

361

• 4E.2

Challenges of testing high-volume, low-cost 8-bit microcontrollers—M. Stout et al.

366

• 4E.3

Correlation of the VT drift in a-Si:H TFT to the optically observed flicker increase in LCD—C.-C. Huang et al.

372

• 4E.6

Investigation of wafer level burn-In to SoC memory: 1TRAM—Y.L. Pan et al.

391

• 4E.7

Practical WLRC methodology & applications in a wafer foundry—W.T.K. Chien et al.

395

Session 5A

GATE DIELECTRIC

- - -

• 5A.1

Growth and scaling of oxide conduction after breakdown—B.P. Linder et al.

402

• 5A.2

A phenomenological theory of correlated multiple soft-breakdown events in ultra-thin gate dielectrics—M.A. Alam and R.K. Smith

406

• 5A.3

Analysis of quantum yield in n-channel MOSFETs—A.S. Spinelli et al.

412

• 5A.4

Temperature dependence and conduction mechanism after analog soft breakdown—T. Nigam et al.

417

• 5A.5

Evidence for defect-generation-driven wear-out of breakdown conduction path in ultra thin oxides—F. Monsieur et al.

424

• 5A.6

Soft breakdown in thin gate oxide – a measurement artifact—K.P. Cheung

432

• 5A.7

Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs—T. Wang et al.

437

Session 5B

PACKAGING

- - -

• 5B.1

(Invited) Wheatstone Bridge Method for Electromigration Study of Solder Balls in Flip-Chip Packages—M. Ding et al.

442

• 5B.2

Board level solder reliability vs ramp rate & dwell time during temperature cycling—C. Zhai, Sidharth, and R.C. Blish

447

• 5B.3

A simple model for the mode II popcorn effect in thin plastic IC packages—P. Alpern and K.C. Lee

452

• 5B.4

Advanced getter solutions at wafer level to assure high reliability to the last generations MEMs—M. Moraja et al.

458

Session 5C

MEMS

- - -

• 5C.1

(Invited) Instrumentation for Genome Analysis (and beyond) based on the TI Digital Micromirror Device—H.R. Garner

460

• 5C.2

Effect of Al₂O₃ ALD Nanocoatings on the thermo-mechanical behavior of Au/Si MEMS structures—K. Gall et al.

463

• 5C.3

Effects of operating conditions on DMD hinge memory lifetime—A.B. Sontheimer and D.J. Mehrl

473

• 5C.4

Reliability of MEMS-based mass-flow controllers for semiconductor processing—E. Lawrence and A.K. Henning

478

• 5C.5

On-chip monitoring of MEMS gear motion—D.M. Tanner et al.

484

Session 6A

MEMORY

- - -

• 6A.1

Variable stress-induced leakage current and analysis of anomalous charge loss for Flash memory application—R. Yamada and T.-J. King

491

• 6A.2

Degradation of tunnel oxide by FN current stress and Its effects on data retention characteristics of 90-nm NAND Flash memory cells—J.-D. Lee et al.

497

• 6A.3

Data retention, endurance and acceleration factors of NROM devices—M. Janai

502

• 6A.4

Study of data retention for nanocrystal Flash memories—C.M. Compagnoni et al.

506

• 6A.5

An enhanced erase mechanism in Flash memory and Its implication on endurance reliability—J.M.Z. Tseng et al.

513

• 6A.6

Effect of programming biases on the reliability of CHE and CHISEL Flash EEPROMs—N.R. Mohapatra et al.

518

Session 6B

FAILURE ANALYSIS

- - -

• 6B.1

(Invited ESREF revised) Lifetime prediction and design of reliability tests for high-power devices in automotive applications—M. Ciappa et al.

523

• 6B.2

High resolution backside fault isolation technique by directly forming Si substrate into solid immersion lens—T. Koyama et al.

529

• 6B.3

Reliability issues and advanced failure analysis technques for copper/low-k—H. Wu et al.

536

• 6B.4

Automated PICA transistor channeling and spatial-temporal photon correlation for faster IC diagnosis—R. Desplats et al.

545

• 6B.5

Laser interaction with SiCr thin film resistors _ the bubble theory—E. Coyne

553

• 6B.6

A new approach to detect small-sized oxygen precipitates in Si wafers using reactive ion etching—K. Nakashima et al.

559

• 6B.7

Consistency of optical data from PICA—T. Lundquist et al.

564