ESD Testing and Failure Analysis for Semiconductor IC's
Jonathan Brodsky, Ph.D. The Seminar will present the different stress models used in the
semiconductor industry to simulate real-world ESD events. Component-level
(HBM, MM, CDM, TLP) and system-level (IEC) test/characterization
methodologies used to gauge the robustness of IC products, along with their
issues and concerns, will be discussed. Additionally, various failure
analysis techniques that are helpful for trouble-shooting ESD failures will
be presented.
Texas Instruments
Jonathan S. Brodsky
Jonathan S. Brodsky received the B.S. degree in electrical engineering from Lafayette College, Easton, PA in 1991 and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, FL, in 1993 and 1997 respectively. His Ph.D. research dealt with the development of compact thermal impedance models for advanced semiconductor device structures. Since 1997, he has worked at Texas Instruments in the Mixed Signal Technology Development ESD Lab. His responsibilities have included the design, development and implementation of ESD protection circuits for analog CMOS, RF BiCMOS and high-voltage BiCMOS technologies. He is currently the Section Head of the MSTD ESD Lab and a member of TI's Technical Staff. He is the co-holder of one patent, with three others pending. He is a member of the ESD Association and the IEEE.