Problems and Solutions for FA on Advanced Microelectronic Circuits

As integrated circuits continue to increase in complexity, new challenges for the failure analyst continue to arise. In this tutorial, we cover the issues that affect failure analysis. These include increases in design complexity, technology and processing complexity, testing challenges, and packaging challenges. Finally, packaging schemes have made the analyst rethink how to access the die to examine signals. Clever analysts and developers have introduced a new group of tools and techniques to enable package access.

Christopher L. Henderson

Chris received his B.S. in physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Since 1988 he has worked at Sandia National Laboratories. He is currently a Principal Member of Technical Staff in the Failure Analysis Group. His job responsibilities include failure and yield analysis of components fabricated at Sandia's Microelectronics Development Laboratory, vulnerability assessment, smart card analysis, and research into the electrical behavior of defects. Chris also teaches courses in failure analysis, reliability and semiconductor technology for the semiconductor industry. He has published over 20 papers at various conferences in semiconductor processing, reliability, failure analysis, and test. He has received 2 R&D 100 awards and several best paper awards at several conferences. Prior to working at Sandia, Chris worked for Honeywell, BF Goodrich Aerospace, and Intel. Chris is a member of IEEE and EDFAS (the Electron Device Failure Analysis Society).