NBTI challenges in PMOSFETs
of Advanced CMOS Technologies
Giuseppe La Rosa
IBM Microelectronics
Because of its observed enhancement in deep submicron CMOS technologies the Negative Bias Temperature Instabilities (NBTI) wearout mechanism has risen as one of the key Reliability constraints in MOSFET scaling. This tutorial will give an overview of the physics of the NBTI damage as well as its sensitivities to gate oxide processes and submicron MOSFET device design schemes. Particular focus will be spent on AC and DC NBTI differences and their expected impact to circuit operations as well as NBTI stressing and testing methodologies.
Giuseppe La Rosa
Giuseppe La Rosa is a Senior Development Engineer at IBM Semiconductor Research and Development Center (NY). Since he joined IBM he has been working in the development of advanced DRAM/Logic submicron technologies. His main interests are in the area of submicron transistor reliability and device physics including Hot Carrier Effects. He holds a Laurea in physics (Italian Doctorate) from the University of Catania and an M.S. in electronic materials from MIT and an M.S. in physics from Northeastern University. He is a member of IEEE Electronic Devices Society.