Soft Error Rate Correction and Design Requirements for Future Server Memory
Charles Slayman, Memory Technology Engineer responsible for assessing technology and reliability issues of future SRAM and DRAM memory used in Sun Microsystems products
Upset of data in semiconductor memory due to terrestrial cosmic rays is a daily reality in large server applications. For a modest overhead, error correction code can be applied on large main memory and cache arrays to virtually eliminate the problem of cell upset. However, upset of SRAM and DRAM chips outside the core memory can go undetected and lead to much more disastrous consequences. More powerful detection and characterization techniques will be required to probe these fatal effects.