Opening & Keynote Address (Plenary Session)
Keynote: Johannes M.C. (Hans) Stork, Chief Technical Officer, Texas Instruments Inc.
Tuesday, April 27, 10:05 a.m., Room A
1. NOVEL TRANSISTOR RELIABILITY FINDINGS(Plenary Session)
1.1 BROAD ENERGY DISTRIBUTION OF NBTI-INDUCED INTERFACE STATES IN p-MOSFETs WITH ULTRA-THIN NITRIDED OXIDE—J.H. Stathis, G. LaRosa, A. Chou, IBM, NY
The energy distribution of interface states during NBTI stress of ultra-thin oxide p-FETs is studied using a combination of LV-SILC and DCIV measurements, sensitive to states near the conduction band edge and near mid-gap, respectively. The generated interface states are found to have a very broad energy distribution for nitrided oxides. The situation in pure SiO2 is qualitatively different. In addition, generated bulk neutral traps show a poor correlation with the NBTI-induced threshold voltage shift.
1.2 NEGATIVE BIAS TEMPERATURE INSTABILITY IN TRIPLE GATE TRANSISTORS—S. Maeda, J.-A. Choi, J.-H. Yang, Y.-S. Jin, S.-K. Bae, Y.-W. Kim, and K.-P. Suh, Samsung Electronics, Korea
Negative bias temperature instability (NBTI) in triple gate transistors was investigated. It is found that NBTI degradation in triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the side surface of the active silicon, which was verified by the examination of crystal orientation dependence.
1.3 INVESTIGATION OF HOT CARRIER EFFECTS IN n-MISFETs WITH HfSiON GATE DIELECTRIC—M. Takayanagi, T. Watanabe, R. Iijima, K. Ishimaru and Y. Tsunashima, Toshiba, Japan
HC reliability of n-MISFETs with HfSiO is studied. It is revealed that electron trap generation is the main cause and the worst stress condition is Vd =Vg than Isubmax. It is found that ΔVot strongly correlate to Ig, indicating that not only hot carriers but also tunneling electrons play an important role.
1.4 HOT CARRIER DEGRADATION IN NOVEL STRAINED-Si nMOSFETs—M.F. Lu, Sinclair Chiang, Alex Liu, S. Huang-Lu, M.S. Yeh, J. R. Hwang and T.H. Tang, W.T. Shiau United Microelectronic Corporation, Hsin-Chu, Taiwan and M.C. Chen and T. Wang National Chiao-Tung University, Hsin-Chu, Taiwan
High Id-sat enhancement is benefited from novel strained-Si process. However, it might cause reliability problems. Here we revealed the HCI degradation of strained-Si devices, which also can be correlated to Ib/Id, were worse than conventional bulk Si devices. Besides, it had high positive temperature coefficient in low voltages. Thus, it would be even worse at the operation voltage.
Tuesday, April 27, 1:35 p.m., Room A
2A TRANSISTORS I (Parallel Session)
2A.1 MODELING OF NBTI DEGRADATION AND ITS IMPACT ON ELECTRIC FIELD DEPENDENCE OF THE LIFETIME—H. Aono, E. Murakami, K. Okuyama, A. Nishida, M. Minami, Y.Ooji, and K. Kubota, Renesas Technology Corp., Japan
Negative Bias Temperature Instability of p-MOSFETs is investigated under various stress conditions. Degradation tends to saturate and the dependence of lifetime on electric field (Eox) is expressed as a power-law of Eox. We propose new empirical and kinetic models, which matches experimental data very well
2A.2 TWO CONCERNS ABOUT NBTI ISSUE: GATE DIELECTRIC SCALING AND INCREASING GATE CURRENT—S. Tsujikawa, Y. Akamatsu, H. Umeda, and J. Yugami, Renesas Technology Corp., Japan
In order to obtain a clear perspective concerning the NBTI issue toward 65-nm-node and beyond, (1) the impact of thinning gate dielectric on the basic mechanism of NBTI and (2) the influence of gate electron current that flows under NBT stress on NBTI have been investigated.
2A.3 A NEW WAVEFORM-DEPENDENT LIFETIME MODEL FOR DYNAMIC NBTI IN PMOS TRANSISTOR—S.S. Tan, T.P. Chen, Nanyang Technological Univ., C.H. Ang, and L. Chan, Chartered Semiconductor Mgf. Ltd., Singapore
We have performed a detailed characterization of dynamic NBTI (DNBTI) for inverter-alike digital waveforms, and formulated a new waveform-dependent phenomenal model for DNBTI lifetime extraction. In addition, a new degradation mode is discovered when PMOS is stressed under inverter-alike waveform as compared to unipolar and bipolar waveform. Finally, our study may help alleviate the NBTI-related concerns for IC design.
2A.4 HOLE TRAPPING EFFECT ON METHODOLOGY FOR DC AND AC NEGATIVE BIAS TEMPERATURE INSTABILITY MEASUREMENT IN PMOS TRANSISTORS—V. Huard, Philips Semiconductors, France, and M. Denaisb, STM, France
This works presents a thorough study of adequate methodology to be used in order to characterize the NBTI degradation by taking into account the transient effects. The hole trapping/detrapping effect on previously existent traps is the dominant origin of the transient effect and not the interface traps passivation by hydrogen atoms.
Tuesday, April 27, 1:35 p.m., Room B
2B BACK-END INTEGRATION (Parallel Session)
2B.1 (Invited) Convergence and interaction of BEOL and BE reliability methodology--S. Rzepka et al., Infineon Technologies AG, Munich, Germany
In high volume microelectronic fabrication, increasing convergence and stronger interaction between the features originated in the back end of line (BEOL) and the back end (BE) processes, respectively, can be seen. Without closely combining the BEOL and BE development efforts, the reliability challenges of next generation technologies will not be met in time. The talk discusses the foundation of appropriate reliability strategies.
2B.2 THERMAL CYCLE RELIABILITY OF STACKED VIA STRUCTURES WITH COPPER METALLIZATION AND AN ORGANIC LOW-k DIELECTRIC—R.G. Filippi, J.F. McGrath, T.M. Shaw, C. Murray, H. Rathore, P.S. McLaughlin, V. McGahay, L. Nicholson, P.-C. Wang, J.R. Lloyd, M. Lane, R. Rosenberg, X. Liu, W. Landers, T. Spooner, J. Demarest, B. Engel, J. Gill, G. Goth, E. Barth, G. Biery, C. Davis, R.A. Wachnik, R. Goldblatt, T. Ivers, A. Swinton, C. Barile, and J. Aitken, IBM, NY
The reliability of a stacked via chain stressed under various thermal cycle conditions is described. The chain consists of Cu Dual Damascene metallization with SiLK (trademark of Dow Chemical) as the organic low-k dielectric. Failure analysis indicates that cracks form in the Cu vias during thermal cycle stress. Due to the presence of two failure modes, the thermal cycle statistical behavior is described by a bimodal lognormal failure distribution. The thermal cycle lifetime exhibits a strong dependence on the temperature range and a rather weak dependence on the maximum temperature in the cycle. Evidence of a threshold temperature range below which thermal cycle fails should not occur is also reported.
2B.3 MEASUREMENTS OF EFFECTIVE THERMAL CONDUCTIVITY FOR ADVANCED INTERCONNECT STRUCTURES WITH VARIOUS COMPOSITE LOW-k DIELECTRICS—F. Chen, T. Sullivan, J. Gill, D. Harmon, B. Li, A. Strong, IBM, Essex Jct., VT, H. Rathore, IBM, East Fishkill, NY, D. Edelstein, IBM T.J. Watson, Yorktown Hgts., NY, C-C. Yang, A. Cowley, and L. Clevenger, IBM Microelectronics, East Fishkill, NY
The effective thermal conductivity for composite media including various low-k dielectric systems was investigated using a unique combination of fully embedded Cu lines as heater and thermometer, power versus temperature electrical measurements, and Harmon-Gill quasi-analytical heat conduction model. The thermal conductivities of all the systems were observed to increase with rising substrate temperature and the temperature dependence is nearly identical. By knowing the thermal conductivity of surrounding dielectric system, the design limitations of DC and AC lines in various low-k systems were also calculated and discussed.
2B.4 IMPACT OF OFF-STATE LEAKAGE CURRENT ON ELECTROMIGRATION DESIGN RULES FOR NANOMETER SCALE CMOS TECHNOLOGIES—S.-C. Lin, A. Basu, UCA, Santa Barbara, CA, A. Keshavarzi, Intel, Hillsboro, OR, A. Mehrotra, Univ. of Ill, Urbana-Champaign, IL, and K. Banerjee, UCA, Santa Barbara, CA
This paper introduces the idea of electrothermally coupled evaluation of junction temperature to accurately estimate the lifetime of interconnects under electromigration (EM) constraints in leakage dominant technologies. The junction temperature thus evaluated with our proposed methodology is incorporated into the interconnect temperature-rise equation (which includes Joule-heating) and is solved self-consistently with both unipolar and bipolar EM lifetime equations to estimate accurate interconnect metal temperature and to provide comprehensive design guidelines for maximum allowable current density in power/ground and signal lines
Tuesday, April 27, 1:00 p.m., Room C
2C GATE DIELECTRICS I - SiO2 (Parallel Session)
2C.1 IMPACT OF GATE OXIDE BREAKDOWN OF VARYING HARDNESS ON NARROW AND WIDE nFETs—B. Kaczer, R. Degraeve, A. De Keersgieter, S. Mahmood, and G. Groeseneken, IMEC, Belgium
A SBD event is observed to have negligible impact on the intrinsic parameters of even a narrow nFET. However, during subsequent wear-out of the BD path a significant effect of gate-to-channel BD's is found. It is also shown that i) the effect of voltage stress on gate oxide and ii) apparent electrical effects have to be separated out to correctly understand the intrinsic nature of the BD.
2C.2 OFF-STATE TDDB RELIABILITY FOR ULTRA-THIN GATE OXIDES: NEW METHODOLOGY AND THE IMPACT OF OXIDE THICKNESS SCALING—E. Wu, E. Nowak, and W. Lai, IBM Microelectronics, Essex Jct., VT
A new methodology has been developed to investigate the off-state TDDB reliability for ultra-thin oxides. This so-called voltage splitting technique can avoid the set-backs of excessive high drain-bias stress. It is shown that the off-state reliability will become an increasingly important reliability issue as the edge tunneling current increase with decreasing oxide thickness.
2C.3 ACCELERATION FACTORS AND MECHANISTIC STUDY OF PROGRESSIVE BREAKDOWN IN SMALL AREA ULTRA-THIN GATE—J. S. Suehle, NIST, Gaithersburg, MD, B. Zhu, Univ. of MD, College Park, MD, and Y. Chen, JPL, Pasadena, CA
The two phases ("digital" and "analog") observed during progressive breakdown in small area ultrathin gate oxides are studied in detail. Voltage and temperature acceleration parameters are determined. Substrate hot-electron experiments reveal that the "digital" and "analog" phases are different physical processes. The "digital" phase is gate current driven and the "analog" phase is gate voltage driven.
2C.4 IMPACT OF STRESS INDUCED LEAKAGE CURRENT ON POWER-CONSUMPTION IN ULTRA-THIN GATE OXIDES—W. Lai, E. Wu, IBM Microelectronics, Essex Jct., VT, J. Sune, Univ.Autónoma de Barcelona, Spain, and E. Nowak, IBM Microelectronics, Essex Jct., VT
A systematic study of the impact of SILC on chip reliability in terms of power-consumption is presented, and a reliability methodology is developed to provide a reliability assessment and projection for a range of ultra-thin oxides down to 1.0nm. It is shown that the power-consumption due to SILC increase will not be the limiting factor for ultrathin gate oxides.
2C.5 INVESTIGATION OF CIRCUIT-LEVEL STRESS AND ITS EFFECT ON MOSFET CHARACTERISTICS AND CMOS INVERTER OPERATION—B.J. Cheek, Boise State Univ., Boise, ID, N. Stutzke, Univ. of Colorado, Boulder, CO, S.Kumar, Cypress Semiconductor, San Jose, CA, J. Baker, A. J. Moll, and W.B. Knowlton, Boise State Univ., Boise, ID
Correlation between individual MOSFET oxide degradation and inverter performance is reported following circuit-level stress. A new circuit model was developed to simulate the DC response of degraded inverters. Inverter time-domain behavior, shown for the first time, may display severe degradation compared to the DC response, which may be negligible in terms of circuit reliability.
2C.6 GATE DIELECTRIC DEGRADATION MECHANISM ASSOCIATED WITH DBIE EVOLUTION—K.L Pey, R. Ranjan, Nanyang Technological Univ., Singapore, C.H. Tung, Institute of Microelectronics, Singapore, L.J. Tang, Nanyang Technological Univ., & Institute of Microelectronics, Singapore, W.H. Lin, Chartered Semiconductor Mfg .Ltd., Singapore, and M.K. Radhakrishnan, National Univ. of Singapore, Singapore
The degradation mechanism of breakdown spots in gate dielectrics associated with dielectric-breakdowninduced epitaxy(DBIE) evolution is physically analyzed. The initial breakdown location triggered by percolation path happens randomly along transistor channel and evolves to the formation of DBIE. For most hard breakdown events, DBIE shorts gate to source or drain region.
2C.7 DEGRADATION OF ULTRA-THIN OXIDES WITH TUNGSTEN GATES UNDER HIGH VOLTAGE: WEAR-OUT AND BREAKDOWN TRANSIENT—F. Palumbo, S. Lombardo, CNR-IMM, Italy, J.H. Stathis, V. Narayanan, F.R. McFeely, and J.J. Yurkas, IBM T.J. Watson Research Center, Yorktown Heights, NY
The reliability under accelerated high voltage stress of Tungsten / SiO2 / Si MOS stacks has been studied. Oxide degradation and breakdown transients are investigated in the range from 3 to 6 V for injection both from gate and substrate (both p- and n-type) and compared to standard poly-Si gates.
Tuesday, April 27, 4:05 p.m., Room A
3A LATCHUP (Parallel Session)
3A.1 CONTENTION-INDUCED LATCHUP—J. T. Mechler, C. Brennan, J. Massucco, R. Rossi, and L. Wissel, IBM, Microelectronics, Essex Jct., VT
In this card level failure investigation of a 0.18 µm non-epitaxial CMOS ASIC chip, a new latchup trigger mechanism is identified. This contention-induced latchup involved IEEE 1149.1 boundary scan structures for open-drain drivers which produce transient driver contention during JTAG testing on an unused, dotted, I2C bus whose off chip drivers employed a Miller feedback capacitor in the I2C driver output stage.
3A.2 MODEL-BASED GUIDELINES TO SUPPRESS CABLE DISCHARGE EVENT (CDE)-INDUCED LATCHUP IN CMOS ICs—K. Chatty, P. Cottrell, R. Gauthier, M. Muhammad, IBM Microelectronics, Essex Jct., VT, F. Stellari, A.J. Weger, P. Song, and M. McManus, IBM Research, Yorktown Heights, NY
Cable Discharge Event (CDE)-induced latchup is severe latchup condition affecting the server industry. An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBM's 130 nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.
3A.3 THE INFLUENCE OF DEEP TRENCH AND SUBSTRATE RESISTANCE ON THE LATCHUP ROBUSTNESS IN A BiCMOS SILICON GERMANIUM TECHNOLOGY—S.H. Voldman, IBM Microelectronics, Essex Jct., VT, and A. Watson, Penn State Univ., State College, PA
This paper demonstrates the effect of deep trench on the latchup robustness for a 0.13 µm 200 GHz BiCMOS SiGeC HBT technology. Key latchup metrics are evaluated using design contours in trench depth vs log (substrate resistance) space to define the latchup design space for trench depth- substrate doping optimization for RF technologies.
3A.4 THE INFLUENCE OF HEAVILY DOPED BURIED LAYER IMPLANTS ON ELECTROSTATIC DISCHARGE LATCHUP AND SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR IN A BiCMOS SiGe TECHNOLOGY—S.H. Voldman, L. Lanzerotti, IBM Microelectronics, Essex Jct., VT, W. Morris, Silicon Engineering, Inc., and L. Rubin, Axcelis Corp.
This paper demonstrates the effect of heavily doped buried layers (HDBL) implants on BiCMOS technology. ESD, latchup and transistor parametrics are evaluated for determining the impact of the HDBL on device parametrics.
Tuesday, April 27, 4:05 p.m., Room B
3B PRODUCTS AND CIRCUITS I (Parallel Session)
3B.1 RELIABILITY AND DESIGN QUALIFICATION OF A SUB-MICRON TUNGSTEN SILICIDE E-FUSE—W.R. Tonti, IBM Engineering and Technology Services, Essex Jct., VT, J.A. Fifield, J. Higgins, W.H. Guthrie, W. Berry, IBM Microelectronics, Essex Jct., VT, and C. Narayan, IBM Research, Yorktown Heights, NY
Sub Micron CMOS features are attractive for Polysilicon Electrical Fuse (E-Fuse) repair options in VLSI designs. E-Fuse implementations as contrasted to laser fuses provide large density advantages over laser fusing and allows for the repair of packaged die, thus providing substantial final yield benefits. Laser fusing typically requires keep out design rules such that fuse neighbors are not unintentionally programmed from a misaligned laser source. Additionally laser fuses typically require a protective cavity to act as a programming debris reservoir. These reasons as well as improving upon the fuse repair solutions required to manage reliability and yield of large die [1] are the major driving forces for providing E-Fuse solutions. In this paper we describe a case study to optimize E-Fuse long term reliability. The methodology employed is for a Tungsten Silicide E-Fuse (WSi2), but the intention of this paper is to benchmark a qualification plan that can be employed for any E-Fuse, i.e. polysilicon, metal, or anti-fuse qualification.
3B.2 A NEW EXPERIMENTAL METHOD FOR EVALUATION ELECTRIC FIELD AT THE JUNCTIONS OF DRAM CELL TRANSISTORS AND THE EFFECT OF ELECTRIC FIELD STRENGTH ON THE RETENTION CHARACTERISTICS OF DRAM—Y. Mori, Hitachi, Ltd., Japan, Y. Takeda, Renesas Technology Corp., Japan, S. Kimura, Hitachi, Ltd., Japan, K. Ohyu, H. Uchiyama, Elpida Memory, Inc., Japan, and R.-I. Yamada, Hitachi, Ltd., Japan
We examined the relationship between leakage-current and electric field at the reverse-biased junctions of DRAM cells through experiment and simulation. We then developed method for evaluation of electric field and firstly confirmed the relationship between electric field and the tail component of the retention-time distribution through experiment rather than simulation.
3B.3 CHARACTERIZATION OF THE TIME-DEPENDENT RELIABILITY FALLOUT AS A FUNCTION OF YIELD FOR A 130 nm SRAM DEVICE AND APPLICATION TO OPTIMIZE PRODUCTION BURN-IN—K.R. Forbes and P. Schani, Motorola SPS, Austin, TX
A model is presented that describes the effect of yield defectivity on time-dependent reliability. Parameters for this model are estimated from interval lifetest data for a 130 nm SRAM device. Parameters are fitted simultaneously using the Maximum Likelihood Estimation (MLE) methodology. These results are used to optimize burn-in and to describe the effect of other defect screening techniques.
3B.4 PMOS NBTI-INDUCED CIRCUIT MISMATCH IN ADVANCED TECHNOLOGIES—M. Agostinelli, S. Lau, S. Pae, P. Marzolf, H. Muthali, and S. Jacobs, Intel, Hillsboro, OR
Of particular concern to analog circuits is the effect of PMOS NBTI-induced mismatch on matched device pairs. The goal of this work is to examine the effect of device mismatch on a thin gate technology through both device and circuit characterization.
Tuesday, April 27, 4:30 p.m., Room C
3C GATE DIELECTRICS II - HIGH-k (Parallel Session)
3C.1 RELIABILITY ASSESSMENT OF ULTRA-THIN HfO2 OXIDES WITH TiN GATE AND POLYSILICON-N+ GATE—X. Garros, CEA-Leti & STM, France, C. Leroux, G. Reimbold, J. Mitard, B. Guillaumot, F. Martin, STM, France, and J.L. Autran, L2MP, France
Reliability of ultra-thin HfO2 oxides with polysilicon and TiN metal gate was thoroughly investigated. Firstly, positive trapping and SILC increase were, for the first time, quantitatively correlated to breakdown. Then HfO2 was compared to SiO2 in term of TBD showing generally much higher long-term reliability at same EOT.
3C.2 CORRELATION BETWEEN STRESS-INDUCED LEAKAGE CURRENT (SILC) AND THE HfO2 BULK TRAP DENSITY IN A SiO2/HfO2 STACK—F. Crupi, Univ. of Calabria, Italy, R. Degraeve, IMEC, Belgium, A. Kerber, Infineon Technologies, affiliated at IMEC, Belgium, D.H. Kwak, Samsung Electronics, affiliated at IMEC, Belgium, G. Groeseneken, Univ. of Calabria, Italy & Catholic Univ. of Leuven, Belgium
The SILC in a 1nm/4nm SiO2/HfO2 stack first rises proportionally with the HfO2 trap density (single-trap conduction paths) and close to breakdown this relation becomes quadratic (two-trap conduction paths). At high stress voltage and/or at elevated temperature, the SILC severely reduce the low leakage benefit. At low stress voltage and room temperature, the SILC poses no reliability restriction.
3C.3 CARRIER SEPARATION ANALYSIS FOR CLARIFYING LEAKAGE MECHANISM IN UNSTRESSED AND STRESSED HfAlOX/SiO2 STACK DIELECTRICS—W. Mizubayashi, N. Yasuda, H. Ota, MIRAI-ASRC, AIST, Japan, H. Hisamatsu, K. Tominaga, K. Iwamoto, K. Yamamoto, MIRAI-ASET, AIST, Japan, T. Horikawa, T. Nabatame, MIRAI-ASRC, AIST, Japan, and A. Toriumi, MIRAI-ASRC, AIST, and Univ. of Tokyo, Japan
We have investigated the carrier type of the leakage current through HfAlOX/SiO2 dielectric layers using the carrier separation method for both the unstressed and stressed cases. It is found that the dominant carriers in the unstressed and stress-induced leakage current (SILC) are holes, while electron current becomes dominant after soft breakdown (SBD).
Tuesday, April 27, 7:00 p.m., Reception Hall
AP ASSEMBLY & PACKAGING POSTERS
AP01 THE DETECTION OF TIN PLATING AND TIN WHISKER MITIGATION—W.D. Bjorndahl, L. Singleton, R. Griese, and F. Chong, Northrop-Grumman Space Technology, Redondo Beach, CA
For the detection of tin plated parts, the XRF technique has been found to be a valuable technique that allows the survey of a large number of parts in a short period of time when compared to other techniques such as EDX. It does have limits however. Not all parts can be resolved using just this technique, and some need further examination using EDX analysis. XRF is most suitable for parts with homogeneous surface finish platings. The XRF technique has advantages of portability and can be used in receiving, stores and the production environments. In addition, it can be taken to vendor sites for on-site evaluation.
AP02 ELECTROMIGRATION RELIABILITY ENHANCEMENT OF FLIP CHIP INTERCONNECTS USING Cu-DOPED SnPb SOLDER—J.D. Wu, C.W. Lee, S.Y. Wu, and S. Li, Advanced Semiconductor Engineering, Inc., Kaohsiung, Taiwan
Electromigration reliability of flip chip interconnects, i.e. SnPb, SnPbCu, SnPbNi solders, are studied with Al/NiV/Cu as under bump metallization. FCBGA with Cu-doped SnPb interconnects are observed to have 3.5-fold improvement in characteristic life (t63) than that of FCBGA using eutectic SnPb solder. On the other hand, significant reliability degradation (55 %) is obtained when employing Ni-doped SnPb solder.
AP03 RELIABILITY AND MICROSTRUCTURE OF LEAD-FREE SOLDER DIE ATTACH INTERFACE IN SILICON POWER DEVICES—D. Huff, D. Katsis, K. Stinson-Bagby, T. Thacker, G.-Q. Lu, and J. D. van Wyk, Virginia Polytechnic Institute and State Univ., Blacksburg, VA
Thermal performance of packaged power devices and multichip modules depends largely on the quality of the solder interface between the silicon power semiconductor devices and the substrate-heat sink assembly. The presence of voids at this interface after solder reflow, along with its mechanical degradation due to thermal cycling have been the leading causes of reduction in thermal performance and reliability of power packages. In addition, environmental regulations have forced the industry to search for lead-free alternatives. This project examines the effects of temperature cycling on the solder interface of power devices attached using lead-free solders that are attached in a flux-less vacuum-solder reflow process. After reflowing the lead-free solder the quality of the die-attach solder interface is evaluated by scanning acoustic microscopy and metallographic analysis. Thermal cycling is then performed and acoustic images of the solder layer are periodically taken to characterize the effects of the solder interface fatigue. Cross-sectional samples are also prepared to monitor the evolution of the solder layer microstructure in an effort to draw a relationship between performance and microstructure.
AP04 INTERFACIAL DEGRADATION OF Au-Al BONDING IN QUAD FLAT PACKAGE—J. Park, B.-S. Kim, H.-J. Cha, Y.-B. Jo, S.-C. Shin, G.-R. Kim, J.-K. Park, M.-Y. Shin, K.-I. Ouh, and H.-G. Jeon, Samsung Electronics, Youngin_City, Korea
In this paper, we have studied the failure mechanism of Au-Al bonding in epoxy encapsulated quad flat package (QFP) induced by high temperature storage (HTS) test conditions. At regular time intervals, the QFP was removed from the chamber, and functional test was performed to monitor the degradation of Au-Al bonding. In a way of root cause analysis to formulate the failure mechanism, the surface morphology and contamination were examined on the wafer level, and chemical precipitate and locus of failure were explored on the devices failed after HTS by using atomic force microscope (AFM), SEM-EDX (energy disperse X-ray) and Auger analysis. It is found that oxidation in a range of 110-300Å and carbon up to 40Å exist on the Al pad. As a result, the bonding strength of the wire pull and ball shear decreases with increasing the thickness of preexisting contamination layer and roughness of Al pad that play a barrier to disturb intimate Au-Al bonding. The plasma etching on the Al pad prior to an epoxy molding, however, enhances the wire pull and ball shear strength up to 10 and 20%, respectively. Apparently, SEM-EDX and Auger reveals that the fractured surface left on the Al bonding pad consists of Au, Al, and O, while the surface of ball lifted is Au, Sb, and O. It is also found that the locus of failure exists between Au and Au2Al in which crack initiates then propagates, leading to an open failure. Furthermore, experimental results that include changes in wire pull and ball shear strength as a function of HTS to understand the effects of 1) plasma etch on the Al pad; 2) Au-Pd (palladium) wire; and 3) epoxy molding compound (EMC) on integrity of Au-Al bonding will be discussed and presented.
Tuesday, April 27, 7:00 p.m., Reception Hall
BE BACK-END DIELECTRICS
BE01 ANALYSIS OF LEAKAGE MECHANISMS AND LEAKAGE PATHWAYS IN INTRA-LEVEL Cu INTERCONNECTS—V.C. Ngwan, C. Zhu, National Univ. of Singapore, Singapore, and A. Krishnamoorthy, Institute of Microelectronics, Singapore
Using the carrier transport modeling in intra-level Cu interconnects, we are able to distinguish the dominant leakage mechanisms: Ohmic, Poole-Frenkel and Schottky mechanisms. In addition, the probable dominant leakage pathways: bulk-induced, barrier layer-induced or their interfaces-induced pathways are deduced to explain the leakage behavior in multlayer interconnects.
BE02 RELIABILITY OF SILICON NITRIDE DIELECTRIC-BASED METAL-INSULATOR-METAL CAPACITORS—T. Remmel, Motorola, Chandler, AZ, R. Ramprasad, Motorola, Tempe, AZ, D. Roberts, M. Raymond, Motorola, Austin, TX, M. Martin, D. Qualls, Motorola,Chandler, AZ, E. Luckowski, Motorola, Austin, TX, S. Braithwaite, M. Miller, Motorola, Tempe, AZ, and J. Walls, Motorola, Chandler, AZ
TDDB testing of various thickness PEN MIM capacitors yielded high quality lifetime data, with very large Weibull betas, consistency between wafer and package level tests and well-behaved field dependencies. Despite this near-ideal set of data, differentiation between the two more popular models for lifetime extrapolation models (E- vs ÖE-) remains, to date, inconclusive.
BE03 EFFECTS OF CHEMICAL ENVIRONMENT ON THIN FILM DELAMINATION—T.Y. Tsui, Texas Instruments, Dallas, TX, Y. Lin, J.J. Vlassak, DEAS Harvard Univ., Cambridge, MA, and A.J. McKerrow, Texas Instruments, Dallas, TX
We have studied the effects of moisture, pH, and temperature on the adhesion strength and sub-critical crack growth rate of OSG/capping layers; OSG/SiN, OSG/TEOS, and OSG/TaN. Results show that the sub-critical crack growth velocities and threshold fracture strengths of all OSG samples are moisture and pH sensitive.
Tuesday, April 27, 7:00 p.m., Reception Hall
CD COMPOUND DEVICES POSTERS
CD01 THE IMPACT OF PROCESS OPTIMIZATION ON PLANAR THz-SCHOTTKY DEVICE RELIABILITY—B. Mottet, C. Sydlo, B. Kogel, Darmstadt Univ. of Technology, Darmstadt, Germany, Q. de Robillard, AMD, Dresdan, Germany, O. Cojocari, and H.L. Hartnagel, Darmstadt Univ. of Technology, Darmstadt, Germany
The technological complexity as well as space application quality standards require sophisticated process control and optimization for reliability improvement of planar THz-Schottky devices. Degradation mechanisms are excited using the TLP-method and monitored for comparison with conventional accelerated stress tests. The degradation analysis is performed by IV- and noise measurements on the one side and by TEM on the other side.
CD02 A STUDY OF OUTPUT POWER STABILITY OF GaN HEMTs ON SiC SUBSTRATES—K.S. Boutros, P. Rowell, and B. Brar, Rockwell Scientific Company, Thousand Oaks, CA
In this paper we investigate the stability of GaN/AlGaN HEMTs under RF operation. We study device parameters such as output power, efficiency, and leakage currents as a function of time, and various bias and RF stress conditions. The goal of the study is to identify the main factors affecting device degradation under RF stress.
Tuesday, April 27, 7:00 p.m., Reception Hall
DI GATE DIELECTRICS POSTERS
DI01 LIFETIME PROJECTIONS AND CONDUCTION MECHANISMS FOR HAFNIUM BASED HIGH-k CAPACITOR DIELECTRICS USING LOW THERMAL BUDGET PROCESS—J.H. Lee, J.P. Kim, J.-H. Lee, Y.-S. Kim, H.-J. Lim, H.-S. Jung, S.J. Doh, N.-I. Lee, and H.-K. Kang, Samsung Electronics Co., Ltd., Yongin-City, Korea
We evaluated the long-term lifetime for Hafnium based high-k dielectrics such as HfO2 and HfO2-Al2O3 laminates at 25ºC and 125ºC in capacitor applications. The extracted Weibull slope of HfO2 TBD distribution shows thickness dependence to be explained by percolation theory. We demonstrate that elevated operation temperature further accelerates HfO2 breakdown than HfO2- Al2O3 laminates, resulting from severe temperature dependent leakage currents due to different conduction mechanisms.
DI02 DIRECT DETERMINATION OF INTERFACE AND BULK TRAPS IN STACKED HfO2 DIELECTRICS USING CHARGE PUMPING METHOD—T.H. Hou, M.F. Wang, K.L. Mai, Y.M. Lin, M.H. Yang, L.G. Yao, Y. Jin, S.C. Chen, and M.S. Liang, TSMC, Hsin-Chu, Taiwan
For the first time, trap density at SiO2/Si interface, HfO2/SiO2 interface, and HfO2 bulk of stacked HfO2/SiO2 dielectrics are quantified respectively with a simple charge pumping method. It was found that the amount of each individual type of traps can be well correlated to specific process conditions as well as device performance, which makes such innovative characterization method very powerful for process optimization of high-k dielectrics.
DI03 STRUCTURE OF THE BREAKDOWN SPOT DURING PROGRESSIVE BREAKDOWN OF ULTRA-THIN GATE OXIDES—F. Palumbo, S. Lombardo, CNR-IMM, Catania, Italy, K.L. Pey, Nanyang Technological Univ., Singapore, L.J. Tang, Nanyang Technological Univ. & Institute of Microelectronics, Singapore, C.H. Tung, Institute of Microelectronics, Singapore, W.H. Lin, Chartered Semiconductor Mfg. Ltd., Singapore, M.K. Radhakrishnan, National Univ. of Singapore, Singapore, and G. Falci, Univ. of Catania, Italy
In ultra-thin gate oxides under high voltage stress it is investigated the physical structure of the breakdown spot progressively evolving towards hard BD. This evolution is monitored and arrested under well defined conditions. The corresponding BD spot structure is studied by transmission electron microscopy and post-BD I-V measurements. A quantitative model based on these data is proposed.
DI04 INFLUENCE OF CHARGE TRAPPING ON AC RELIABILITY OF HIGH-k DIELECTRICS—M. Kerber, R. Duschl, H. Reisinger, Infineon Technologies, Munich, Germany, S. Jakschik, U. Schroder, T. Hecht, and S. Kudelka, Infineon Technologies, Dresden, Germany
The life time of Al2O3 dielectrics in trench DRAM capacitors is investigated under bipolar AC stress. Other than expected from the literature a frequency dependent life time reduction together with lower voltage acceleration and steeper Weibull distributions are found. This is attributed to the trapping characteristics of high-k dielectrics.
DI05 EFFECTS OF THIN SiN INTERFACE LAYER ON TRANSIENT I-V CHARACTERISTICS AND STRESS INDUCED DEGRADATION OF HIGH-k DIELECTRICS—C.Y. Kang, H.-J. Cho, C.S. Kang, R. Choi, Y.H. Kim, S.J. Rhee, C.H. Choi, A. Shahriar, and J.C. Lee, Univ. of Texas at Austin, Austin, TX
Effects of thin interface SiN on charge trapping characteristics and its time dependent threshold voltage instability is reported. Thin SiN interface showed better DIT and GM degradation compared to constant voltage stress and transient I-V measurement. It is believed that mobility degradation is primarily caused by interface states.
DI06 DRAIN BIASED TDDB LIFETIME MODEL FOR ULTRA THIN GATE OXIDE—C.-Y. Ko, Y.S.Tsai, P.J.Liao, J.J.Wang, A.S. Oates, and K. Wu, TSMC, Hsin-Chu, Taiwan
For drain biased TDDB, hole injection enhanced gate oxide degradation has been discussed and modeled, and the model is in excellent agreement with the experimental data. Although hole injection will degrade gate oxide, lifetime of drain biased TDDB is better than gate bias due to stress area difference and strong area dependence (is small) for ultra thin gate oxide; however, it may become a concern for thickoxide for drain bias.
DI07 POLARITY DEPENDENCE OF CHARGE TRAPPING IN POLY-SILICON GATE HfO2 MOSFETs—H.M. Bu, X.W. Wang, D.C. Guo, L.Y. Song,T.P. Ma, Yale Univ., New Haven, CT, H. Tseng, and P. Tobin, Motorola, Austin, TX
Polarity dependence of charge trapping in poly-Si gate HfO2 MOSFETs has been systematically studied. It is shown that both the stress-induced threshold voltage shift (deltaVth) and the trans-conductance degradation (deltaGm) are worse in nMOSFETs than in pMOSFETs. For substrate injection in nMOSFETs, electron trapping occurs at the n-poly/HfO2 interface and/or in bulk HfO2, whereas for gate injection in pMOSFETs hole trapping near the Si substrate is observed.
DI08 GATE OXIDE MULTIPLE SOFT BREAKDOWN (MULTI-SBD) IMPACT ON CMOS INVERTER—H.-M. Huang, C.Y. Ko, M.L. Yang, P.J. Liao, J.J. Wang, A.S. Oates, and K. Wu, TSMC, Hsin-Chu, Taiwan
The impact of gate oxide multiple soft breakdown (Multi-SBD) on the performance of CMOS inverter has been demonstrated. The results indicate that the CMOS inverter is still functioning when Multi-SBD event occurs, but noise margin degraded rapidly after extending a period of time. Moreover, off-state leakage current increasing and gate induced drain leakage (GIDL) phenomenon are other concerns. Multi-SBD may be acceptable in reliability viewpoint and the results also imply that we can relax the failure criteria of gate oxide reliability to allow a higher operation voltage, but it must depend on circuit design and application rather for all cases.
DI09 EFFECTS OF GATE ELECTRODES AND BARRIER HEIGHTS ON THE BREAKDOWN CHARACTERISTICS AND WEIBULL SLOPES OF HFO2 MOS DEVICES—Y.H. Kim, R. Choi, UT Austin, Austin, TX, R. Jha, J.H. Lee, V. Misra, NC State Univ., Raleigh NC, and J.C. Lee, UT Austin, Austin, TX
In this work, we present the effect of gate electrodes and barrier heights on the breakdown characteristics and WEIBULL slopes of HFO2 MOS devices. Higher WEIBULL slope (B) of RU gate electrode has been observed when compare that of RU-TA alloy. The higher B in RU devices is due to smaller charge fluence which results from relatively higher barrier height.
DI10 CHARGE TRAPPING AND DEVICE PERFORMANCE DEGRADATION IN MOCVD HAFNIUM-BASED GATE DIELECTRIC STACK STRUCTURES—C.D. Young, G. Bersuker, G.A. Brown, P. Lysaght, P. Zeitzoff, R.W. Murto, and H.R. Huff, International SEMATECH, Austin, TX
High-k gate dielectric stacks referred to as hybrid stacks (Hf Silicate/HfO2) of various thickness were investigated with respect to charge trapping using electrical and physical characterization of the samples. A plausible trapping model has been proposed that suggests trapping occurs in the bulk of the high-k film, which leads to less trapping in physically thinner high-k gate stacks.
DI11 THE LAST TRAP THAT FORM THE PERCOLATION PATH THE STRESS VOLTAGE EFFECT—K.P. Cheung, Rutgers Univ., Piscataway, NJ
In this paper, we use a recently developed kinetic model to show, quantitatively, that the combination of current increase and temperature rise at the moment of the formation of a "temporary percolation path" that triggers irreversible breakdown. At low voltage operation where both current surge and temperature rise are greatly reduced, most of the temporary percolation path will not lead to irreversible breakdown. Thus the whole methodology of TDDB is not applicable to predict ultra thin oxide lifetime for operation at low voltage.
DI12 FREQUENCY DEPENDENT DYNAMIC CHARGE TRAPPING IN
HFO2 AND THRESHOLD VOLTAGE INSTABILITY IN MOSFETS—C. Shen, H.Y. Yu, X.P.
Wang, M.-F. Li*, Y.C. Yeo, D.S.H. Chan, Univ. of Singapore,
Singapore, K.L. Bera, Institute of Microelectronics, Singapore, and
D.L. Kwong, Univ. of Texas at Austin, Austin, TX
*also Institute of Microelectronics, Singapore
We perform the first investigation of threshold voltage instability in MOSFETs with MOCVD HfO2 dielectrics under both static and dynamic stress. We report the frequency dependence of Dynamic BTI in transistors with the HfO2 dielectric. For an ac stress of a given gate voltage amplitude, we observed reduction of BTI degradation with an increase in stress frequency for both n- and p-MOSFETs. A new physical model that accounts for carrier trapping/de-trapping and generation of new traps in the HfO2 dielectric under stress is proposed. Simulation results based on the new model shows good agreement with all experiment data.
Tuesday, April 27, 7:00 p.m., Reception Hall
ES ESD POSTERS
ES01 CHIP-LEVEL ESD SIMULATION FOR FAIL
DETECTION AND DESIGN GUIDANCE—S. Druen, M. Streibl*, F. Zangl*, J. Schneider*,
U. Glaser#,, K. Esmark*, W. Stadler*, H. Gossner*, and D.
Schmitt-Landsiedel, Technical Univ. of Munich, Germany
*Infineon Technologies, Munich, Germany
#ETH Zurich,Switzerland
Modern VLSI products exhibit a new kind of ESD failure mode with its root cause lying in the overall chip-level ESD protection network. Root causes and impact of this failure class need to be investigated. Based on a case study the origin of this kind of fail is investigated and counter measures are derived using a new simulation approach.
ES02 INCREASED ESD PROTECTION ROBUSTNESS OF A LATERAL NPN STRUCTURE IN THE ADVANCED CMOS—V. Vassilev, G. Groeseneken, IMEC & K.U. Leuven/ESAT, Leuvan, Belgium, M. Steyaert, K.U. Leuven/ESAT, Leuven, Belgium, and H. Maes, IMEC & K.U. Leuven/ESAT, Leuven, Belgium
This paper describes a novel, more robust design of a lateral snapback structure for use as ESD protection device in the state of the art CMOS. The device shows factor of two increased failure levels in the investigated 90nm technology devices compared to the widely used ggNMOS, which is attributed to the absenced of gate oxide breakdown.
ES03 HIGH CURRENT CHARACTERISTICS OF COPPER INTERCONNECT UNDER TRANSMISSION-LINE PULSE (TLP) STRESS AND ESD ZAPPING—J.H. Lee, J.R. Shih, K.F. Yu, Y.H. Wu, J.Y. Wu, J.L. Yang, C.S. Hou and T.C. Ong, TSMC, Hsin-Chu, Taiwan
Real time I-V characteristics of copper (Cu) interconnect under low current and high current transmission-line pulse (TLP) stresses is found to be different due to self-heating.
ES04 COMPARISON OF ULTRA-THIN GATE OXIDE ESD PROTECTION CAPABILITY OF SILICIDED AND SILIDE-BLOCKED—J.H. Lee, J.R. Shih, K.F. Yu, Y.H. Wu, and T.C. Ong, TSMC, Hsin-Chu, Taiwan
In this paper, ultra-thin gate oxide ESD protection capability of silicided and silicide-blocked MOSFETS is studied. PMOS and NMOS capacitors with floating and non-floating drain are examined. Placement of ultra-thin gate oxide capacitor relative to the ESD protection MOSFET is also investigated.
Tuesday, April 27, 7:00 p.m., Reception Hall
FA FAILURE ANALYSIS POSTERS
FA01 FAILURE ANALYSIS ON RESISTIVE OPENS WITH SCANNING SQUID MICROSCOPY—S. Hsiung, K. Tan, A. Komrowski, D.J.D. Sullivan, LSI Logic Corp., Fremont, CA, J. Gaudestad, A. Orozco, E.Talanova, and L.A. Knauss, Neocera, Inc., Beltsville, MD
Scanning SQUID Microscopy (SSM) is a current density imaging technique that has been used in failure analysis to localize package- and die-level shorts [1, 2]. New developments have extended this technology to localizing resistive opens, augmenting other non-destructive failure analysis tools like TDR and assisting destructive deprocessing by further pin pointing defect locations. We present here a method to isolate resistive opens with Scanning SQUID microscopy and we illustrate the use of the technique to isolate actual resistive open yield failures in both wire-bond and flip-chip devices.
FA02 SIDEWALL DAMAGE INDUCED BY FIB MILLING DURING TEM SAMPLE PREPARATION—Q. Gao, M. Zhang, C. Niou, M. Li, K. Chien, and P. Liu, Semiconductor Mfg. International Co., Shanghai, China
A novel method was invented to observe the physical thickness of crystal damage layer on sidewall of TEM sample. The physical thickness of the damaged layer at different accelerated voltage and beam current was given. The effect of smart tilt on amorphous layer thickness and diffraction pattern is also discussed. Better understanding of this phenomenon was brought up based on our experiment results.
FA03 GOLD DENDRITE SIMULATION AND GROWTH KINETICS—J.L. Kersey, Jr. and R.C. Blish, II, AMD, Sunnyvale, CA
The necessary factors controlling internal Au dendrite growth kinetics are bias, hygroscopic die attach material and gold plating salt residues. Dendritic growth rate was linear with plating salt concentration, but the key factor was presence of residual nonylphenol. Laboratory simulations produce the same dendrite morphology as seen for failed units.
FA04 FAILURE ANALYSIS OF SINGLE BIT CELL IN THE SRAM CACHE AT THE 90 nm PROCESS NODE USING ATOMIC FORCE PROBING—A.N. Erickson, Multiprobe, Inc., Santa Barbara, CA
SRAM Cache Memory cell layout is traditionally the highest density layout in a CMOS IC. It is therefore subject to the greatest failure rate and therefore responsible for the largest yield loss. It is therefore critical for reasonable yield in each new process node to analyze the failures in this array. Atomic Force Probing has been used successfully to contact and analyze single bit failures with 3 and 4 probes in an individual cell. 90nm process node 6T SRAM cell failure characterization will be discussed
Tuesday, April 27, 7:00 p.m., Reception Hall
IT INTERCONNECTS POSTERS
IT01 EFFECT OF THERMAL GRADIENTS ON THE ELECTROMIGRATION LIFETIME IN POWER ELECTRONICS—H. V. Nguyen*, C. Salm*, B. Krabbenborg#, J. Bisschop#, A.J. Mouthaan*, F.G. Kuper*,# *Univ. of Twente, Enschede, The Netherlands #Philips Semiconductors, Nijmegen, The Netherlands
The combined effects of electromigration and thermomigration are studied. Significantly shorter electromigration lifetimes are observed in the presence of a temperature gradient that cannot be explained by thermomigration only (atoms moving due to a temperature gradient) but are attributed to the effect of temperature gradient on electromigration-induced failures.
IT02 EFFECTS OF LOW k FILM PROPERTIES ON ELECTROMIGRATION PERFORMANCE—W. Lu, Y.K. Lim, A. See, T.J. Lee, L.C. Hsia, Chartered Semiconductor Mfg. Ltd, Singapore, J. Hander, H. Fu, L.S. Wong, and F.P. Fen, Novellus Systems Inc., San Jose, CA
This paper will compare the reliability results of a traditionally used Carbon-doped low k dielectric film with a newer high mechanical strength (HMS) film. The standard low k film was found to have marginal electromigration (EM) performance. The HMS film was better due to increased film toughness and improved adhesion.
IT03 STRESS INDUCED DEGRADATION OF 90 nm NODE INTERCONNECTS—X. Federspiel, Philips Semiconductors, Crolles, France
Stress induced by thermal expansion mismatch between copper, substrate and dielectrics may damage the interconnects. In particular, voids formed by vacancy coalescence, are likely to induce open in the interconnects. On the basis of experimental results, we propose a model of the evolution of the resistance of voided via chains.
IT05 THE INFLUENCE OF SURFACE FLUCTUATIONS ON EARLY FAILURES IN SINGLE-DAMASCENE Cu WIRES: A WEAKEST LINK APPROXIMATION ANALYSIS—H. Wang, C. Bruynseraede, IMEC, Leuven, Belgium, and K. Maex, IMEC & K.U. Leuven, Leuven, Belgium
Different CMP slurries are used to obtain single-damascene Cu wires with different surface fluctuations and `intentional' surface defects in the lines with rougher surface. The presence of such intentional defects strongly increases the rate of early failures, up to almost 100%, reduces electromigration lifetime rapidly to the level of early failures, and changes the multimodal failure distribution into a monomodal one. The WLA analysis confirms that, although surface defects are not the fastest early failure mechanism, the 10 times higher surface-defect density in the rougher lines is responsible for the observed high early-failure rate and poor reliability performance.
IT06 ELECTROMIGRATION PERFORMANCE ENHANCEMENT OF Cu INTERCONNECTS WITH PVD Ta CAP—D.A. Gajewski, M. Lien, T. Meixner, B. Feil, and J. Walls, Motorola SPS, Chandler AZ
We demonstrate an electromigration (EM) performance enhancement of Cu interconnects with PVD Ta cap. The activation energy is higher than for more conventional caps such as silicon nitride, yet uses the same tools and materials as the conventional barrier/seed process, as opposed to electroless Pd or CoWP deposition.
IT07 VOID AND EXTRUSION INDUCED FAILURE OF SUBMICRON MULTILEVEL INTERCONNECTS—Y.-B. Jo, J. Park, C.-H. Jeon, K.-I. Ouh, and H.-G. Jeon, Samsung Electronics, Youngin-City, Korea
Failure mechanism of submicron multilevel interconnects contained in quad flat package (QFP) subjected to high temperature operating life (HTOL) test conditions under temperature and bias was investigated. Integral and differential non-linearity, direct current (DC) parameter of analogue to digital converter (ADC), was measured as an indicator to monitor degradation process induced by the given test conditions. In an effort to elucidate failure mode, scanning and transmission electron microscopy (TEM) combined with focused ion beam (FIB) milling were used on the devices failed. Apparently, the electron microscopy, SEM-EDX (X-ray dispersive), reveals that the extrusion of Al metallization appears on the ground and voltage imposed metal lines, and it potentially grows as test time increases and bridges an adjacent metal line, leading to a short failure in the presence of void near the via. In fact, the DC parameter drastically increases with increasing test time and number of damage sites resulting in malfunction of the ADC. Such phenomena which may need to be taken into account include the given stress test conditions correlated to the capability of electronic circuit design. For the verification purpose, a new circuit design is committed and subjected to the HTOL. Specific experimental results and the influence of such circuit change on the reliability of submicron interconnect technology will be discussed and presented in detail.
Tuesday, April 27, 7:00 p.m., Reception Hall
MS MEMS POSTERS
MS01 TEST STRUCTURES AND DRIE TOPOGRAPHY FOR BULK SILICON MEMS DEVICES—Y. Ruan and D. Zhang, Peking Univ., Beijing, China
New test structures and DRIE topography are put forward to overcome the problems in MEMS process. These structures are important for reliability and failure analysis in process, especially in silicon to glass anodic bonding and silicon DRIE process. Standard bulk silicon MEMS process was achieved, which have fabricated more than 30 types of MEMS devices successfully.
MS02 THERMO-MECHANICAL BEHAVIOR AND RELIABILITY OF Au/Si MEMS STRUCTURES—D. Miller, K. Spark, D. Finch, and K. Gall, Univ. of Colorado, Boulder, CO
We examine the thermo-mechanical behavior of composite gold/ polysilicon microcantilevers. Hillock formation was observed above 175°C. Creep was studied for parts briefly annealed at 190°C and then isothermally held at various temperatures. Significant creep driven change in shape was observed at all temperatures.
Tuesday, April 27, 7:00 p.m., Reception Hall
MY MEMORY POSTERS
MY01 MULTI-LEVEL PROGRAMMING OF NOR FLASH EEPROMS BY CHISEL MECHANISM—D.R. Nair, S. Mahapatra, Indian Institute of Technology, Bombay, India, S. Shukuri, Renesas Technology Corp., Tokyo, Japan and J. Bude, Agere Systems, Allentown, PA
Multi-level CHISEL programming of NOR flash EEPROM bitcells were studied. Six different bitcell doping schemes were used and optimized doping was identified based on their program and drain-disturb performance. Program transients show excellent self-convergence leading to accurate VT control both before and after cycling. Programmed VT levels show very little degradation, program/disturb margin remains within limit and erased VT level shows some degradation after cycling. The impact of bitcell scaling on the performance and reliability of ML CHISEL programming is also explored.
MY02 FLASH MEMORY UNDER COSMIC & ALPHA IRRADIATION—A.D. Fogle, D. Darling, R.C. Blish, II, and G. Daszko, AMD, Sunnyvale, CA
Neutron and proton irradiation to simulate cosmic ray jeopardy were used to established that NOR Flash memory (conventional floating polySi gate or ONO floating gate Mirror Bit™) soft error failure rate (cross section) is 4-5 orders of magnitude better than SRAM. Flash memory soft error rate for a given dose of alpha particle irradiation is much less that for the same dose from simulated cosmic rays.
MY03 INVESTIGATION OF PROGRAMMED CHARGE LATERAL SPREAD IN A TWO-BIT STORAGE NITRIDE FLASH MEMORY CELL BY USING A CHARGE PUMPING TECHNIQUE—S.H. Gu, M.T. Wang, C.T. Chan, National Chiao-Tung Univ., Hsin-Chu, Taiwan, N.K. Zous, C.C. Yeh, W.J. Tsai, T.C. Lu, Macronix International Co., Ltd., Hsin-Chu, Taiwan, T. Wang, National Chiao-Tung Univ., Hsin-Chu, Taiwan, J. Ku, and C.-Y. Lu, Macronix International Co., Ltd., Hsin-Chu, Taiwan
The lateral distribution of programmed charge in a hot electron program/hot hole erase nitride storage flash cell is investigated by using a charge pumping technique. Our study shows that the secondly programmed bit has a wider trapped charge distribution than the first programmed bit. In addition, we find programmed charge spreads further into the channel with program/erase cycle number.
MY04 DIFFERENT APPROACHES FOR RELIABILITY ENHANCEMENT OF p-CHANNEL FLASH MEMORY—S.S. Chung, Y.J. Chen, and H.W. Tsai, National Chiao Tung Univ., Hsin-Chu, Taiwan
In this paper, we will demonstrate two different strategies for designing p-channel flash memories, for achieving better reliability, in particular data retention and drain-disturb. The first one is by using a gate-engineering approach and the other one is using a newly developed substrate bias enhanced Avalanche Hot Electron (AHE) injection programming scheme. For the former, a p-doped floating gate on both p-channel flash cells can be achieved with superior data retention characteristics as well as a 3-order improvement of the drain disturb. For the latter, it exhibits much higher speed and much lower voltage for programming, and very good drain disturb characteristics.
MY05 STATISTICAL MODELING FOR POST-CYCLING
DATA RETENTION OF SPLIT-GATE FLASH MEMORIES—L.-C. Hu, A.-C. Kang*, I.-T. Liu*, Y.-F. Lin*, K. Wu*, and Y.-C.
King, National Tsing-Hua Univ., Hsin-Chu, Taiwan
*TSMC, Hsin-Chu, Taiwan
In developing a precise model for post-cycling data retention failure rate of split-gate flash memories, a statistical method is proposed for the extraction of the floating-gate potential from the measured bit-cell-current data. Floating gate charge leakage mechanism during retention of split-gate flash memories is investigated as well. While multiple leakage mechanisms maybe the responsible for the failure bits in stack-gate flash memories, it is found that stress induced leakage current is the major cause for post-cycling data retention failure bits in split-gate flash memories
Tuesday, April 27, 7:00 p.m., Reception Hall
PC PRODUCTS AND CIRCUITS POSTERS
PC01 DEVELOPMENT AND USE OF A MINIATURIZED HEALTH MONITORING DEVICE—V. Rouet and B. Foucher, EADS CCR, Suresnes, France
This article describes the architecture and the operation of a micro-Time Stress Measurement Device. This electronic system prototype integrates sensors allowing the acquisition of temperature, relative humidity and mechanical shocks. Optimised for low power consumption, it is an autonomous system that has been integrated inside the case of an electronic module for its environmental monitoring.
PC02 STANDBY CURRENT PREDICTION MODEL FOR MICROPROCESSORS RELIABILITY RISK ASSESSMENT—B. Lisenker, Intel, Haifa, Israel
For the first time, it is shown, that the application of the percolation theory makes it possible to integrate the MOSFET's off-current contribution to deep-sub-micron microprocessors standby current. A model for this current prediction is proposed and discussed. The model permits the standby current versus voltage and temperature test results for reliability risk assessment and process monitoring. The viability of this model is examined on 32-bit 0.13 um benchmark microprocessors.
PC03 CMOS TRANSISTOR ELECTRICAL AGEING EXPERIMENTS TO BUILD VHDL-AMS BEHAVIORAL MODELS—B. Mongellaz, F. Marc, and Y. Danto, Univ. of Bordeaux, Talence, France
Our main goal is to demonstrate the feasability of an ageing simulation using VHDL-AMS high level description behavioural models. An experimental case study focuses on hot-carrier injections that induce electrical ageing on CMOS devices and on analogue block as an Operational Transconductance Amplifier. We analyze experimental data to build MOSFET degradation behavioral models. Then degradation models are used in electrical simulation to evaluate ageing effects on CMOS and OTA electrical performances. This methodology is a basis to developp ageing simulation of complex analogue application.
PC04 LOCAL REDESIGN FOR RELIABILITY OF CMOS DIGITAL CIRCUITS UNDER DEVICE DEGRADATION—X. Xuan, A. Chatterjee, Georgia Tech, Atlanta, GA, and A.D. Singh, Auburn Univ., Auburn, AL
IC reliability simulator ARET was developed and with its reliability simulation and hotspot identification functions, ARET has played an essential role in IC design-for-reliability. A concept of local design-forreliability is proposed based on reliability simulation, and a set of such design approaches have been developed for CMOS digital circuits under device degradation mechanisms, such as hot-carrier and gate oxide wear-out. By performing local redesign for reliability, circuit reliability can be significantly improved, while the originally designed overall circuit performance is still maintained.
PC05 SOFT BREAKDOWN EFFECTS ON MOS SWITCH AND PASSIVE MIXER—A. Sadat, Y.Liu, J. Yuan, Univ. of Central FL, Orlando, FL, and H. Xie, Univ. of FL, Gainesville, FL
On wafer 0.16 µm NMOS transistors are stressed and measured. Soft breakdown effects on MOS switch and passive mixer are evaluated. Time constant for the switch increases. Conversion gain and LO feed-through of the mixer degrade.
PC06 THERMAL RUNAWAY AVOIDANCE DURING BURN-IN—A. Vassighi, O. Semenov, and M. Sachdev, Univ. of Waterloo, Waterloo, Canada
In deep sub-micron technologies, increased standby leakage current in high performance processors results in increased junction temperature. Elevated junction temperature causes further increase on the standby leakage current. The standby leakage current is expected to increase even more under the burn-in environment leading to still higher junction temperature and possibly the thermal runaway. In this paper we investigate the thermal management of high performance processors during burn-in.
PC07 RELIABILITY MODEL AND IMPLEMENTATION FOR EEPROM EMULATION USING FLASH MEMORIES—C. He, P. Kuhn, T. Jew, and M. Niset, Motorola, Austin, TX
For embedded applications requiring nonvolatile storage of data that is updated in byte or word granularity, special software is used to emulate EEPROM functionality on block-erasable Flash memories. In this paper, we present a reliability model for the emulated EEPROM, and discuss the impact of Flash reliability characteristics and implementation schemes.
PC08 NEW SCREEN METHODOLOGY FOR 0.13µm AND BEYOND TECHNOLOGIES—A. Wang, C.H. Wu, R.Y. Shiue, C.H. Hsieh, and K. Wu, TSMC, Hsin-Chu, Taiwan
Result of this study shows Less Noise Margin (LNM) dice have reliability weakness in 0.13µm and beyond technologies. High temperature chip probing test can narrow the noise margin and screen out weak dice effectively by functional test. This paper also demonstrated circuit speed and VDDmin are effective indexes to assess reliability risk.
PC09 THE CHALLENGE TO RECORD CORRECT FAST WLR MONITORING DATA FROM PRODUCTIVE WAFERS AND TO SET REASONABLE LIMITS—A. Martin, J. Fazekas, A. Pietsch, W. Muth, and D. Smeets, Infineon Technologies AG, Muenchen, Germany
A concept for fast WLR Monitoring on test structures in the scribe line of product wafers is described focussing on some reliability risks. A clear approach is required, starting with the very fast measurement method, the raw data screening, the precise data assessment and the control cards with reasonable limits. Through a correct iplementation fast WLR is an ideal process tool monitor and supports the concept to build in reliability.
PC10 DETERMINATION OF THE MAXIMUM VOLTAGE FOR A PRODUCT SCREENING STRESS BASED ON TDDB AND HC MEASUREMENTS—H.-H. Kuge, Philips Semiconductors, Boeblingen, Germany
Tuesday, April 27, 7:00 p.m., Reception Hall
PI PROCESS INTEGRATION POSTERS
PI01 LAYOUT DESIGN DEPENDENCE OF NBTI FOR I/O pMOSFET—V. Koldyaev, PDF Solutions, San Jose, CA
A set of experimental studies of NBTI of p-MOSFET with different layout designs across a wafer is carried out for a modern technology to see statistical behavior of this reliability mechanism. A strong layout dependence is discovered to out knowledge for the first time. A possible model is proposed considering negative effects of H and mechanical stress on the Si-SiO2 interface degradation during VLSI processing.
PI02 EFFECT OF MAGNETIC FIELD ON PLASMA DAMAGE DURING VIA ETCHING IN SUB-MICRON CMOS TECHNOLOGY—N.S. Kim, H.G. Yoon, C.K. Lee, J. Zhao, C.Y. Tuck, Y.S. Cheah, W.W. Yew, P. Southworth, S.H. Han, and K.S. Pey, Systems on Silicon Mfg. Co., Singapore
We have intensively investigated the effect of VIA etching process with magnetic field and main etch time variation on plasma damage to gate oxide of n/pMOSFET devices. It is reported that lower magnetic field during VIA etching process can reduce the plasma charging damage to gate oxide. In particular, we propose the optimal VIA etching condition with a lower magnetic field based on a higher main etch time to reduce the plasma charging dramatically, while still keeping a good VIA contact resistivity(Rc), for the first time.
PI03 THERMAL DEGRADATION OF DRAM RETENTION TIME: CHARACTERIZATION AND IMPROVING TECHNIQUES—Y.I. Kim and K.H. Yang, Samsung Electronics, Hwasung-City, Korea
Variation of DRAM retention time and reliability problem induced by thermal stress were investigated. Most of the DRAM cells revealed 2-state retention time with thermal stress. The effects of hydrogen annealing condition and fluorine implantation on the variation of retention time and reliability are discussed.
Tuesday, April 27, 7:00 p.m., Reception Hall
SE SER / SEU POSTERS
SE02 THRESHOLD ENERGY OF NEUTRON-INDUCED SINGLE EVENT UPSETS AS A CRITICAL FACTOR—Y. Yahagi, E. Ibe, Hitachi Ltd., Yokohama, Japan, Y. Takahashi, Y. Saito, A. Eto, M. Sato, Renesas Technology Corp., Kodaira, Japan, H. Kameyama, Renesas Kodaira Semiconductor, Co.,Ltd., Kodaira, Japan, M.Hidaka, Elpida Memory, Inc., Kanagawa, Japan, K. Terunuma, T. Nunomiya, and T. Nakamura, Tohoku Univ., Miyagi, Japan
The first direct measurement of neutron induced single event upset of SRAMs by using several MeVs monoenergetic neutrons revealed that upset threshold energy was as low as 2 MeV. A reliable estimation method for field soft error rate with threshold neutron energy was demonstrated.
SE03 AN ALPHA IMMUNE AND ULTRA LOW NEUTRON SER HIGH DENSITY SRAM—P. Roche, F. Jacquet, C. Caillat, and J.-P. Schoellkopf, STM, Crolles, France,
An alpha Immune and Ultra Low Neutron SER High Density SRAM fabricated in a standard 120 nm CMOS technology. Comparisons with a standard ECC protected SRAM and a regular HD SRAM are discussed. A testchip with 12.2 Mbit SRAM and shift registers demonstrates effectiveness.
SE04 MODELING AND VERIFICATION OF SINGLE EVENT TRANSIENTS IN DEEP SUBMICRON TECHNOLOGIES—M.J. Gadlage, NAVSEA, Crane, IN, R.D. Schrimpf, Vanderbilt Univ., Nashville, TN, J.M. Benedetto, Mission Research Corp., Colorado Springs, CO and P.H. Eaton, Mission Research Corp., Albuquerque, NM
In this paper, the propagation of single event transients in digital microcircuits is studied. Simulations are used to characterize the response of a circuit to a single event. These simulation results are then compared to data from a test chip designed to look at transients in deep submicron digital circuits.
SE05 TECHNOLOGY SCALING OF CRITICAL CHARGES IN STORAGE CIRCUITS BASED ON CROSS-COUPLED INVERTER-PAIRS—T. Heijmen, B. Kruseman, R. van Veen, and M. Meijer, Philips Research Labs, Eindhoven, The Netherlands
Technology scaling of the critical charge in SRAM cells and flip-flops has been studied using circuit simulation and illustrated with data from accelerated SER experiments. The state-dependency of the critical charge of flip-flops and the effect of processing variations in deep-submicron technologies are shown.
SE06 NEUTRON-INDUCED SEU IN BULK AND SOI SRAMS
IN TERRESTRIAL ENVIRONMENT—J. Baggio, D. Lambert*, V.
Ferlet-Cavrois, and C. D'hose, CEA DIF, Bruyeres le chatel, France
*also EADS-CCR, Suresnes, France,
In this work we compare the Soft Error Rate (SER) sensitivity of commercial bulk and fully-depleted SOI devices in terrestrial neutron environment. The SOI parts exhibit very low SER values that we explain by using Monte Carlo simulations.
Tuesday, April 27, 7:00 p.m., Reception Hall
TR TRANSISTORS POSTERS
TR01 RELIABILITY INVESTIGATIONS ON A UNIQUE DIRECT-TUNNELING-INDUCED HIGH PERFORMANCE PARTIALLY-DEPLETED SOI DEVICE—S.-S. Chen, S. Huang-Lu, and T.-H. Tang, UMC, Hsin-Chu, Taiwan
Using the converse poly-gate in partially-depleted (PD) SOI, the direct-tunneling mechanism is applied to improve the performances in current-driving capability, kink-onset voltage, subthreshold-swing, and hysteresis effect. Therefore, it is essential to further investigate its reliability. After a series of reliability investigations, direct-tunneling-induced high performance PD SOI shows the satisfied results.
TR02 NBTI EFFECTS OF PMOSFETs WITH DIFFERENT NITROGEN DOSE IMPLANTATION—Y.J. Lee, Y.C.
Tang, M.H. Wu, T.S. Chao*, P.T. Ho#, D. Lai, W.L. Yang#, and T.Y. Huang, National Chiao Tung Univ., Hsin-Chu, Taiwan
* also National Nano Device Labs, Hsin-Chu, Taiwan
#Feng Chia Univ., Taichung, Taiwan
In this study, NBTI effects of PMOSFETs with different nitrogen dose implantation and regions were investigated. High nitrogen dose implantation in the channel or source/drain extension results in serious NBTI degradation. Both the dynamic NBTI effects and substrate hot holes effects were also discussed in this study.
TR03 PMOS THIN GATE OXIDE RECOVERY UPON NEGATIVE BIAS TEMPERATURE STRESS—M.S Akbar, Univ. of Texas at Austin, Austin, TX, M. Agostinelli, Intel Corp., Hillsboro, OR, S. Rangan, Intel Corp., Santa Clara, CA , S. Lau, C. Castillo, S. Pae and S. Kashyap, Intel Corp., Hillsboro, OR
In this work, we have investigated the passivation/recovery behavior of thin gate PMOS devices under both static and dynamic negative bias temperature stress conditions and have shown that thin gate recovery characteristics differ somewhat from thick gate. Thin gate recovery also shows different behavior under low and high frequency dynamic stressing.
TR04 HYDROGEN-RELATED EXTRINSIC OXIDE TRAP GENERATION IN ULTRA THIN SiO2 DURING NEGATIVE-BIAS TEMPERATURE INSTABILITY STRESS—J.-S. Lee, Uiduk Univ., Gyongju, Korea, J.W. Lyding, and K. Hess, Univ.
This paper presents an extended model for NBTI of P-MOSFET with 3 NM gate oxide film. The devices, annealed with a standard forming gas (FG) process, have been subjected to an additional annealing process under high pressure, using both hydrogen and deuterium. We found that NBTI was accelerated by the high-pressure hydrogen (or deuterium) annealing compared to the standard FG annealing. This is attributed tothe higher hydrogen (deuterium) density that is introduced in the gate oxide, and that in turn causes higher densities of oxide charges. Our investigation (of recovery and isotope effect for NBTI under these different annealing conditions) shows that both interface-reaction and bulk-reaction for oxide traps, which can be the precursor for hole trapping, are among the origins of NBTI degradation in ultra-thin gate oxide.
TR05 COMPREHENSIVE STUDY AND NEW FINDINGS ON NBTI OF PARTIALLY DEPLETED SOI TRANSISTORS WITH ULTRA-THIN GATE DIELECTRICS—J. Zhang, A. Marathe, K. Taylor, E. Zhao, and B. En, AMD, Sunnyvale, CA
NBTI of PD-SOI PMOSFETs with ultra-thin gate-dielectrics was studied. SOI-specific issues were addressed. Diffusion-limited electromechanical reaction and dominance of interface states were evidenced. Extra holes due to body-tie were found responsible for worse NBTI in BT transistors. Both hole-population and oxide-field controlled NBTI. Self-relaxing signature of NBTI recovery was revealed.
TR06 MECHANISM FOR REDUCED NBTI EFFECT UNDER PULSED BIAS STRESS CONDITIONS—B. Zhu, Univ. of Maryland, College Park, MD, J.S. Suehle, NIST, Gaithersburg, MD, and J.B. Bernstein, Univ. of Maryland, College Park, MD
NBTI induced degradation of deep sub-micron p-MOSFETs were measured after DC and AC bias stresses with frequency up to 500K Hz. The DVth and degradation of Ion was observed to be significantly reduced for pulsed bias stress. A mechanism based on the trapping and detrapping of holes was proposed.
Wednesday, April 28, 8:25 a.m., Room A
4A MEMORY I (Parallel Session)
4A.1 MRAM technologies and their reliability implications--B. Hughes, Infineon Technologies, San Jose, CA
4A.2 RELIABILITY PROPERTIES OF LOW VOLTAGE PZT FERROELECTRIC CAPACITORS AND ARRAYS—J. Rodriguez, K. Remack, K. Boku, K.R. Udayakumar, S. Aggarwal, S. Summerfelt, T. Moise, H. McAdams, J. McPherson, Texas Instruments, Dallas, TX, G. Fox, R. Bailey, and M. Depner, Ramtron International Corp., Colorado Springs, CO
We report the importance of PZT crystallographic texture for the reliability properties of 70nm MOCVD PZT films. We show for the first time, excellent fatigue characteristics measured to 1E13 cycles. Data loss is primarily due to imprint, which follows a 1.3eV time and temperature activation.
4A.3 ANALYSIS OF PHASE-TRANSFORMATION DYNAMICS AND ESTIMATION OF AMORPHOUS-CHALCOGENIDE FRACTION IN PHASE-CHANGE MEMORIES—A. Itri, D. Ielmini, A.L. Lacaita, A. Pirovano, Politecnico di Milano, Milano, Italy, F. Pellizzer, and R. Bez, STM, Agrate Brianza, Italy
We analyzed experimental I-V curves as a function of programming current in PCM cells. Our electrical characterization provides clear evidence for a stacked distribution of phases after the current pulse. A technique to estimate the amorphous fraction of the chalcogenide is shown. Anomalous cells consistent with a parallel phase-change behavior have been detected, indicating a possible reliability concern.
4A.4 RELIABILITY OF FLASH MEMORY ERASING OPERATION UNDER HIGH TUNNELING ELECTRIC FIELDS—A. Chimenton and P. Olivo, Univ. di Ferrara, Ferrara, Italy
Experimental results show that the use of high electric fields during erasing of Flash memories leads to a degradation of the reliability of the erasing operation due to the increase of the erratic erase. The generation of new erratic bits during cycling has been related to the Anode Hole Injection phenomena.
Wednesday, April 28, 8:25 a.m., Room B
4B INTERCONNECTS
4B.1 (Invited) Effects of overlayers on electromi-gration reliability improvement for Cu/low k interconnects--C.-K. Hu, D. Canaperi, S.T. Chen, L.M. Gignac, B. Herbst, S. Kaldor, E. Liniger, D. L. Rath, D. Restaino, R. Rosenberg, J. Rubino, S.-C. Seo, A. Simon, S. Smith, and W.-T. Tseng, IBM T.J. Watson Research Ctr., Yorktown Hgts, NY
Electromigration in Cu Damascene lines capped with either a CoWP, Ta/TaN, SiNx, or SiCxNyHz layer was reviewed. A thin CoWP or Ta/TaN cap on top of the Cu line surface significantly reduced Cu interface diffusion and greatly improved the electromigration lifetime when compared with lines capped with SiNx or SiCxNyHz. Activation energies for electromigration were found to be 2.0, 1.4, and 0.85-1.1 eV for the Cu lines capped with CoWP, Ta/TaN, and SiNx or SiCxNyHz, respectively.
4B.2 THE IMPROVEMENT OF COPPER INTERCONNECT ELECTROMIGRATION RESISTANCE BY CAP/DIELECTIC INTERFACE TREATMENT AND GEOMETRICAL DESIGN—M.H. Lin, Y.L. Lin, J.M. Chen, C.C. Tsai, M.S. Yeh, C.C. Liu, Y.C. Sheng, K.P. Chang, K.C. Su, and Y.J. Chang, United Microelectronics Corp., Hsin-Chu, Taiwan
A significant improvement of electromigration(EM) lifetime is achieved by modification of pre-clean before cap-layer deposition and Cu cap/dielectric materials. Effects of geometrical layout variation and stress current direction are also demonstrated. The data indicate that interfacial cleanliness and bond character at the interface have a substantial impact on the resistance of EM.
4B.3 STRESS MODELING OF Cu/LOW-k BEOL - APPLICATION TO STRESS MIGRATION—C.J. Zhai, H.W. Yao, P.R. Besser, A. Marathe, R.C. Blish II, D. Erb, C. Hau-Riege, Sidharth & K.O. Taylor, AMD, Sunnyvale, CA
Volume-averaged SM-driving stress and SIV Risk Index vary strongly with ILD stack composition. Hydrostatic and Von-Mises stresses increase with line width, signaling increased driving forces for void nucleation and dislocation movement. Stress varies dramatically along the line, especially at the SM-sensitive region near the via bottom, consistent with failure analysis.
4B.4 STRESS-INDUCED VOIDING IN MULTI-LEVEL COPPER/LOW-k INTERCONNECTS—Y.K. Lim, Chartered Semiconductor Mfg. Ltd.& Nanyang Technological Univ., Singapore, Y.H. Lim, C.S. Seet, B.C. Zhang, K.L. Chok, K.H. See, T.J. Lee, L.C. Hsia, Chartered Semiconductor Mfg. Ltd., Singapore, and K.L. Pey, Nanyang Technological Univ., Singapore
More stress-induced damaged vias were observed at the upper metallization layers and at the edge of the wafer. The stress-induced voiding mechanism was explained and shown to be more prounced when Cu was integrated with dielectric of lower constant values. Some strategies were recommended to effectively manage such effect.
4B.5 IDENTIFICATION OF ELECTROMIGRATION DOMINANT DIFFUSION PATH FOR COPPER DAMASCENE INTERCONNECTS AND EFFECT OF PLASMA TREATMENT AND BARRIER DIELECTRICS ON ELECTROMIGRATION PERFORMANCE—T. Usui, T. Oki, H. Miyajima, Toshiba Corp., Yokohama, Japan, K. Tabuchi, K. Watanabe, T. Hasegawa, Sony, Yokohama, Japan, and H. Shibata, Toshiba Corp., Yokohama, Japan
Electromigration testing pattern to identify the dominant diffusion path for Cu damascene interconnects is proposed. It is confirmed that dominant diffusion path is interface of Cupper/barrier dielectrics using the proposed testing pattern. After identification, it is found that CuOx at the interface accelerates the diffusion and that nitrogen at the interface retards it drastically.
Wednesday, April 28, 8:25 a.m., Room C
4C MEMS
4C.1 INVESTIGATION OF RELIABILITY PROBLEMS IN THERMAL INKJET PRINTHEAD—J.-H. Lim, S.-S. Baek, S.-J. Shin, K. Kuk, J.-W. Shin, Y.-J. Kim, and Y.-S. Oh, Samsung Advanced Institute Technology, Yongin_si, Korea
This paper presents a failure analysis result for enhancing the reliability of thermal inkjet printhead. A novel inkjet printhead is fabricated using MEMS technique, and we analyze the failure mechanism of inkjet head based on detailed experimental observations. The design modification of micro heater to avoid an early stage of failure yields the reliability enhancement of printhead.
4C.2 CALIBRATION AND OPTIMIZATION OF INTERCONNECTS BASED MEMS TEST
STRUCTURES FOR PREDICTING THERMO MECHANICAL STRESS
IN METALLIZATION—J.M. dos Santos, A.B. Horsfall, J.C. Prata Pina*, N.G. Wright, A.G. O'Neill, K.Wang, S.M. Soare, S.J.
Bull, J.G. Terry#, A.J. Walton#,
J.T.M. Stevenson#, and A.M. Gundlach#, Univ. of Newcastle, Newcastle upon Tyne, UK
*Univ. of Coimbra,
Coimbra, Portugal
#Univ. of Edinburgh, Edinburgh, UK
The dependence of process conditions on the behavior of interconnects based sensor structures has been studied. The study shows that the fabricated sensors are capable of indicating both compressive and tensile stress in the metal interconnects. Work is on-going to optimize the geometric features of the sensors, by improving its sensitivity. Calibration of the devices is being made by X-ray diffraction methods.
4C.3 WIDEBAND AND HIGH RELIABILITY RF-MEMS SWITCHES USING PZT/HfO2 MULTI-LAYERED HIGH K DIELECTRICS—J. Tsaur, K. Onodera, T. Kobayashi, M. Ichiki, R. Maeda, and T. Suga, National Institute of Advanced Industrial Science and Technology, Ibaraki, Japan
The novel approach using a PZT/HfO2 multi-layered dielectric with high equivalent dielectric constant was investigated for obtaining high switching isolation of capacitive contact type MEMS switches. It also performs very low charging effects in comparison to Si3N4. The preliminary performance of the p-match switch demonstrated low insertion loss and high isolation.
Wednesday, April 28, 10:05 a.m., Room C
5. TRANSISTORS II (Parallel Session)
5.1 PMOS DRAIN BREAKDOWN VOLTAGE WALK-IN: A NEW FAILURE MODE IN HIGH POWER BiCMOS APPLICATIONS—D. Brisbin, A. Strachan, and P. Chaparala, National Semiconductor Corp., Santa Clara, CA
Today's power management devices (e.g. DC-DC converters) frequently require operation in the 50V to 100V range. These circuits implement a BiCMOS process that combine low to medium voltage (5-15V) with high voltage (50-100V) devices. In these applications the high voltage PMOS must be able to operate at high currents, voltages (e.g. 80V) and temperatures (150°C) while sustaining a drain breakdown voltage well in excess of the device operating voltage. Because of the high voltages, currents and temperatures seen by these devices the long-term reliability is a real concern. This paper focuses on an HV-PMOS device failure mode identified during operational life testing that resulted n functional device quiescent current failure. This paper differs from previous work in that it presents data on a new PMOS failure mechanism "breakdown voltage walk-in" not yet discussed in the literature.
5.2 DYNAMIC POSITIVE BIAS TEMPERATURE INSTABILITY CHARACTERISTICS OF ULTRA-THIN HfO2 NMOSFET—S.J. Rhee, Y.H. Kim, C.Y. Kang, C.S. Kang, H.-J. Cho, R. Choi, C.H. Choi, M.S. Akbar, and J.C. Lee, UT Austin, Austin, TX
The studies of VT instability under dynamic stress demonstrate that the dependencies of VT on both frequency and duty cycle for HfO2 dielectrics. The bulk trap in HfO2 is believed as a primary factor for larger VT shift than interface trap. Compared to constant voltage stress, AC stress allows higher 10-year lifetime operating voltage.
5.3 A COMPREHENSIVE FRAMEWORK FOR PREDICTIVE MODELING OF NEGATIVE BIAS TEMPERATURE INSTABILITY—S. Chakravarthi, A.T. Krishnan, V. Reddy, C.F. Machala and S. Krishnan, Texas Instruments, Dallas, TX
A quantitative model is developed for the first time, that comprehends all the unique characteristics of NBTI degradation. Several models are critically examined to develop a reaction/diffusion based modeling framework for predicting interface state generation during NBTI stress. The model predicts mechanisms resulting in a range of fractional time dependence (time0.15-0.3) for NBTI degradation. The model predicts post stress effects like recovery, experimental delay and frequency effects successfully.
5.4 HOT-CARRIER INJECTION IN STEP-DRIFT RF POWER LDMOSFET—G. Cao and M.M. De Souza, De Montfort Univ., UK
Substrate current in step-drift LDMOSFET can be reduced to nearly one-forth of the value in single-drift design, due to the lower electric field close to the channel region. However, an additional origin of hot-carrier generation is found at the location of step drift. Although the hot-carrier injection at this location does not cause drift of quiescent current, it degrades IDsat, transconductance and breakdown voltage. The major degradation can be attributed to donor-type interface states created by hole injection. As a result, the output power, gain and efficiency of power amplifier are degraded.
Wednesday, April 28, 1:35 p.m., Room A
6A SER / SEU (Parallel Session)
6A.1 COMPARISON BETWEEN NEUTRON-INDUCED SYSTEM-SER AND ACCELERATED-SER IN SRAM—H. Kobayashi, H. Usuki, K. Shiraishi, H. Tsuchiya, and Jun Kase Sony Corp., San Jose, CA
High energy neutron induced SSER and ASER were compared on SRAM. A large discrepancy was observed. We assume that the discrepancy originates from the assumed value of terrestrial neutron flux. The ASER results were normalized to the SSER of 0.18 µm SRAM. The SER of 0.13 µm 16Mb SRAM is approximately 180 FIT/Mb.
6A.2 PROCESS IMPACT ON SRAM ALPHA-PARTICLE SEU PERFORMANCE—Y.Z. Xu, H. Puchner, A. Chatila, O. Pohland, B. Bruggeman, B. Jin, D. Radaelle and S. Danieli, Cypress Semiconductor, San Jose, CA
A single poly, 0.15mm process has been modified to fabricate a 18 Mb fast synchronous memory for evaluation of the process impact on the alpha-particle SEU (single Event Upset) performance. The process options include (1)increasing the source/drain junction capacitance, (2)adding a backend capacitor between the storage nodes, and (3)using the epitaxial substrate. In addition, the fraction factorial splits were carried out for other implants, such as n-well and p-well processes to quantify their impact on the SEU FIT rate. The P-Latch transistor drive current and threshold voltages have been changed as well to explore the influence on the SRAM alpha-ASER. It is found that the most effective method to improve the SEU FIT rate is to add additional capacitor, followed by the junction capacitance increase. The rest of the process options have only a secondary impact on the SRAM ASER.
6A.3 SRAM SER IN 90, 130 AND 180 nm BULK AND SOI TECHNOLOGIES—E.H. Cannon, D.D. Reinhardt, and P.S. Makowenskyj, IBM Microelectronics, Essex Jct., VT
We investigate the soft error rate (SER) of bulk and SOI SRAMs in the 90, 130 and 180 nm technology nodes with accelerated tests and Monte Carlo modeling. We discuss SER trends with scaling and compare the sensitivity of bulk and SOI devices. Lifetests at multiple locations confirm SER predictions.
6A.4 NEUTRON-INDUCED SOFT-ERROR IN LOGIC DEVICE USING QUASI-MONOENERGETIC NEUTRON BEAM—S. Yamamoto, Renesas Technology Corp., Japan, K. Kokuryou, Tada Electric Corp., Japan, Y. Okada, J. Komori, E. Murakami, K. Kubota, Renesas Technology Corp., Japan, N. Matsuoka and Y. Nagai, Research Center for Nuclear Physics, Japan
The SER of the flip-flop circuit is approximately 1/3~1/5 that of the embedded SRAM per bit. The SER of the logic circuits can no longer be ignored with the increasing circuit scale. We propose a method of SER estimation for various component circuits in logic devices.
6A.5 TRANSISTOR SIZING FOR RADIATION HARDENING—Q. Zhou and K. Mohanram, Rice Uniiversity, Houston, TX
We present an efficient and accurate numerical analysis technique to simulate single event upsets (SEUs) in logic circuits. A novel method for transistor resizing to harden CMOS gates to SEUs of particular magnitudes is also presented. Experimental results agree well with SPICE simulations, while allowing for very fast analysis.
Wednesday, April 28, 1:35 p.m., Room B
6B BACK-END DIELECTRICS (Parallel Session)
6B.1 (Invited) COMPREHENSIVE RELIABILITY EVALUATION OF A 90 nm CMOS TECHNOLOGY WITH Cu/PECVD LOW-k BEOL—D. Edelstein, H. Rathore, C. Davis, L. Clevenger, A. Cowley, T. Nogami, B. Agarwala, S. Arai, A. Carbone, K. Chanda, S. Cohen, W. Cote, M. Cullinan, T. Dalton, S. Das, P. Davis, J. Demarest, D. Dunn, C. Dziobkowski, R. Filippi, J. Fitzsimmons, P. Flaitz, S. Gates, J. Gill, A. Grill, K. Ida, D. Klaus, N. Klymko, M. Lane, S. Lane, J. Lee, W. Landers, WK. Li, Y-H. Lin, E. Liniger, X-H. Liu, A. Madan, S. Malhotra, J. Martin, S. Molis, C. Muzzy, D. Nguyen, S. Nguyen, M. Ono, C. Parks, D. Questad, D. Restaino, A. Sakamoto, T. Shaw, Y. Shimooka, A. Simon, E. Simonyi, A. Swift, T. Van Kleeck, S.Vogt, W. Wille, J. Wright, C-C. Yang, M. Yoon, and T. Ivers, IBM/Sony/Toshiba/AMD Advanced Semiconductor Technology Alliance, Hopewell Jct., NY
Results are reported from comprehensive reliability testing of a 90 nm CMOS technology with Cu/low-k organosilicate glass BEOL. Tests included E-M, S-M, TDDB, T/C, THB, packaging stresses, and product functional stresses. Materials and integration enhancements maximized reliability without penalty to R or C. Results equaled those of our concurrent Cu/oxide technologies.
6B.2 HIGHLY RELIABLE DIELECTRIC/METAL BILAYER SIDEWALL DIFFUSION BARRIER IN Cu/POROUS ORGANIC ULTRA LOW-k INTERCONNECTS—Z. Chen, K. Prasad, Nanyang Technological Univ., Singapore, C.Y. Li, P.W. Lu, S.S. Su and L.J. Tang, Institute of Microelectronics, Singapore
Reliability of Cu/porous organic ultra low-k damascene structures, in terms of leakage current, breakdown electric field and TDDB lifetime, is greatly enhanced by a dielectric/metal bilayer sidewall diffusion barrier. The use of a-SiC;H as a dielectric layer in the bilayer results in a better surface sealing of the ultra low-k dielectric, leading to better reliability.
6B.3 BARRIER INTEGRITY AND RELIABILITY OF Cu POROUS-LOW-k INTERCONNECTS—Z. Tokei, IMEC, Belgium, V. Sutcliffe, TI assigned at Imec, S. Demuynck, IMEC, Belgium, F. Iacopi, IMEC & Katholike Univ., Belgium, P. Roussel, G.P. Beyer, IMEC, and K. Maex, IMEC & Katholike Univ., Belgium
When porous low-k materials are integrated into damascene structures barrier integrity is a very important parameter in TDDB behavior. The main degradation mechanism is copper drift through the not fully dense diffusion barrier. Sealing of the porous low-k sidewalls leads to significant interconnect reliability improvement and is key in achieving reliable interconnects for the 45 nm node and beyond.
6B.4 RELIABILITY IMPROVEMENT USING BURIED CAPPING LAYER IN ADVANCED INTERCONNECTS—K.Y. Yiang, T.S. Mok, and W.J. Yoo, National Univ. of Singapore, Singapore, A. Krishnamoorthy, Institute of Microelectronics, Singapore
Reliability of Cu/SiOC damascene structures is greatly enhanced by a buried capping layer (BCL) of 100 Å thickness. Leakage current is reduced by ~ 1 order. Breakdown field is improved by a factor of 1.5 to 2. In addition, the BCL is able to suppress process-induced traps formation in the low-k dielectric.
6B.5 TDDB RELIABILITY ASSESSMENTS OF 0.13 µm CU/LOW-K INTERCONNECTS FABRICATED WITH PECVD LOW-k MATERIALS—N. Hwang, M.C. A. Micaller-Silvestre, C.F. Tsang, J. Y.-J. Su, C.C. Kuo and A.D. Trigg, Institute of Microelectronics, Singapore
Time-dependent dielectric breakdown (TDDB) measurements were used to predict lifetime of Cu/low-k interconnects. A voltage ramp test (Vramp) was performed in the beginning, to determine appropriate TDDB stress conditions. The low-field “E-Model” was then used to extrapolate to MTTF at 3.3V and 100°C. The calculated E-Model parameters are comparable to other published results. It was observed that thermally-induced diffusion dominates the lifetime extrapolation by at least two orders of magnitude. By delaying the Cu diffusion process by relevant interface engineering, reliability of Cu/low-k interconnects can be improved.
Wednesday, April 28, 2:00 p.m., Room C
6C FAILURE ANALYSIS (Parallel Session)
6C.1 FINDING OF VOID IN DUAL DAMASCENE Cu VIAS AND IMPACT ON RELIABILITY—W. Dong, J. Ji, S. Liang, M. Zhang, S. Liao, C. Niou, and K. Chien, SMIC, China
This paper presents the identification of a major problem, void in via, in advanced 0.13 µm Cu interconnection process development through failure analysis. We can find several kinds of void in Cu via, which will be detail discussed in this paper. Particularly, we will introduce the impact on reliability coming from void in vias.
6C.2 A NEW BREAKDOWN FAILURE MECHANISM IN HfO2 GATE DIELECTRIC—R. Ranjan, K.L. Pey, Nanyang Tech. Univ., L.J. Tang, Nanyang Tech. Univ. & Institute of Microelectronics, C.H. Tung, Institute of Microelectronics, Singapore, G. Groeseneken, IMEC, Belgium, M.K. Radhakrishnan, National Univ. of Singapore, B. Kaczer, R. Degraeve, and S. De Gendt, IMEC, Belgium
The breakdown mechanism in HfO2 gate dielectric is physically analyzed by HRTEM. The breakdown phenomenon in HfO2 is different from that of ultrathin SiON and Si3N4. The main microstructural damages observed in the BD of the HfO2 gate dielectric are likely related to HfSix and HfSiOx formation during BD event.
6C.3 C-V AND C-P CHARACTERIZATION SENSITIVITY FOR FAST AND SLOW-STATE TRAPS IN VERY THIN MOSFETs—J.-Y. Rosaye, FASL, Japan, Y. Yasuda, A. Sakai, Nagoya Univ., Japan, P. Mialhe, Perpignan Univ., France, J.-P. Charles, Metz Univ., France, and Y. Watanabe, Toyota, Japan
Very thin MOSFET transistors were characterized at its Si/SiO2 interface using a Temperature Dependent C-V method, which introduces an original insight for temperature-activated processes. New defect properties are investigated when oxide thickness is shrinking. Fast-state traps appear as interface states for 5 nm thick oxide. Sensibility is discussed for very low defect densities by using TDCV but also charge-pumping method (C-P).
6C.4 THERMAL LASER STIMULATION OF ACTIVE DEVICES IN SILICON A QUANTITATIVE FET PARAMETER INVESTIGATION—C. Boit, A. Glowacki, S. Brahma, and K. Wirth, TUB Berlin Univ. of Technology, Germany
Thermal Laser Stimulation (TLS) can localize also silicon device anomalies using free carrier absorption in heavily doped areas. We present frontside and backside results on the quantitative influence of TLS on FET parameters. We show how the FET output curve shifts as function of laser power and scanning speed.
6C.5 POSITIVE PHOTON DISCRIMINATION FOR ULTRA LOW VOLTAGE IC ANALYSIS—R. Desplats, M. Remmach, F. Beaudoin, P. Perdu, French Space Agency, France, M. Leibowitz, K. Sanchez, S. Guilaume, and T. Lundquist, NPTest, San Jose,
Debug is facilitated with Time Resolved Photon Emission. .Latest technologies are now working at ultra low power supply voltages, <1V. At such voltages, background noise begins to mask commutation peaks thus biasing the analysis. With the positive photon discrimination approach signal is extracted even below the noise level.
6C.6 TRANSIENT-LU FAILURE ANALYSIS OF THE ICS, METHODS OF INVESTIGATION AND COMPUTER AIDED SIMULATIONS—K. Domanski, Infineon Technologies AG, Germany & Nicholas Copernicus Univ., Poland, S. Bargstädt-Franke, W. Stadler, M. Streibl, G. Steckert, Infineon Technologies AG, Germany, and W. Bala, Nicholas Copernicus
With the ongoing downscaling of the technologies, transient latch-up (TLU) will become increasingly important. In this paper detailed studies on three different products with fails which have been assigned to TLU are presented. Physical failure analysis methods and TLU measurements have been used to locate the failing devices. With TCAD simulation the failure mechanism could be revealed and counter measures could be derived successfully.
6C.7 STRUCTURAL ANALYSIS OF INTEGRATED CIRCUITS USING SCANNING LASER ULTRASONICS—G. Andriamonje, V. Pouget, Y. Ousten, D. Lewis, and Y. Danto, Univ. Bordeaux, France
We present the in-depth analysis of a VLSI circuit using the picosecond ultrasonics technique. This optical non-destructive technique is based on ultrasound generation and detection by ultrashort laser pulses. The experimental setup and methodology are described. The indepth and lateral resolution of the technique are illustrated by experimental results.
Wednesday, April 28, 4:05 p.m., Room A
7A ESD (Parallel Session)
7A.1 NATIVE-NMOS-TRIGGERED SCR (NANSCR) FOR ESD PROTECTION IN 0.13-µM CMOS INTEGRATED CIRCUITS—M.-D. Ker and K.-C. Hsu, National Chiao-Tung Univ., Taiwan
A native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-µm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and CDM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.
7A.2 BASE PUSHOUT DRIVEN SNAPBACK IN PARASITIC BIPOLAR DEVICES BETWEEN DIFFERENT POWER DOMAINS—U. Glaser, Integrated Systems Lab, & Infineon Technologies, J. Schneider, M. Streibl, K. Esmark, Infineon Technologies, Germany, S. Druen, Technical Univ. of Munich, Germany, H. Gobner, Infineon Technologies, Germany, and W. Fichtner, Integrated Systems Lab, Switzerland
Modern integrated circuits still exhibit unexplored ESD failure modes. In this work, the trigger voltage of the base pushout driven snapback in parasitic bipolar devices is identified as a limiting value for the ESD concept design and the cause for damage in a 0.13 µm technology. Its strong dependence on base driving by standard ESD protection elements is considered carefully. Effective countermeasures are examined.
7A.3 EFFECTS OF HOT SPOT HOPPING AND DRAIN BALLASTING IN INTEGRATED VERTICAL DMOS DEVICES UNDER TLP STRESS—P. Moens, AMI Semiconductor, Belgium, S. Bychikhin, TU Vienna, Austria, K. Reynders, AMI Semiconductor, Belgium, D. Pogany, TU Vienna, Austria, M. Zubeidat, AMI Semiconductor, Belgium
The effects of hot spot hopping and drain ballasting in integrated VDMOS transistors under TLP stress are investigated. The influence of the BLN layer on the hopping frequency and the drain ballasting are verified experimentally. Both mechanisms are competing, leading to an optimum BLN dose for maximum ESD robustness.
7A.4 GATE DIELECTRIC BREAKDOWN: A FOCUS ON ESD PROTECTION—B.E. Weir, C.-C. Leung, P.J. Silverman, and M.A. Alam, Agere Systems, Allentown, PA
Transmission line pulse (TLP) measurements are used to demonstrate that oxynitride breakdown projections from DC measurements using conventional area, voltage, and thickness-scaling techniques can be extended to the nanosecond time-scale. ESD protection systems can thus be designed to prevent dielectric breakdown.
7A.5 A PMOSFET ESD FAILURE CAUSED BY LOCALIZED CHARGE INJECTION—J.-H. Chun, Stanford Univ., Stanford, CA, C. Duvvury, G. Boselli, H. Kunz, Texas Instruments, Dallas, TX, and R.W. Dutton, Stanford Univ., Stanford, CA
A new failure mechanism of PMOSFET device under ESD conditions has been reported and analyzed by investigating various I/O structures. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection into the body of the PMOSFET. This phenomenon can be implicated in ESD failures of all future ASIC I/O circuits which require more compact layouts. Critical layout parameters affecting this problem are discussed based on 2-D device simulations; a general strategy for avoiding this failure mode is also suggested.
Wednesday, April 28, 4:05 p.m., Room B
7B RF PRODUCTS & CIRCUITS (Parallel Session)
7B.1 RF HCI TESTING METHODOLOGY AND LIFETIME MODEL ESTABLISHMENT—W.L. Ng, N. Toledo, K.F. Lo and A. Yap, Chartered Semiconductor Mfg., Singapore
The degradation of the RF and DC performance as a result of Hot Carrier degradation mechanism is widely reported. For the RF performance, degradation in the cut-off frequency (fT) and maximum frequency (fmax) is reported to be due to degradation in the transconductance (gm) and the gate-source capacitance (Cgs) of the transistors. Moreover, it is observed that a correlation exists between the degradation of the RF and DC performance thus indicating the possibility of predicting RF performance from measured DC performance. In our study, we have established a good correlation between RF and DC performance degradation due to Hot Carrier using Chartered's 0.18µm technology. With the established correlation we have proposed an efficient method to predict RF HCI lifetime from the DC parameter degradation of the transistors. In our study, the HCI Lifetime of the RF parameter, fT is predicted using the Substrate Current Model. A good fit is observed indicating that the traditional lifetime models could be used to predict RF HCI lifetime.
7B.2 RELIABILITY EVALUATION AND COMPARISON OF CLASS-E AND CLASS-A POWER AMPLIFIERS WITH 0.18µM CMOS TECHNOLOGY—W.-C. Lin, L.-J. Du and Y.-C. King, National Tsing-Hua Univ., Taiwan
Circuit reliability of Class-E and Class-A power amplifiers are investigated based on a degradation sub-circuit model. In this study, we've found that Class-E amplifier degrades faster than Class-A amplifier, due to the relatively large switch stress voltage between gate to drain. The decrease of power added efficiency lead to the functional failure of a power amplifier.
7B.3 EFFECTS OF HOT-CARRIER STRESS ON THE PERFORMANCE OF CMOS LOW NOISE AMPLIFIER—S. Naseh and M.J. Deen, McMaster Univ., Canada
Effects of DC hot-carrier stress on the performance of a CMOS LNA are investigated. The gain of the LNA decreases with stress time which is due to the drop of transconductance gm of the transistors. The input and out matching of the LNA slightly degrades with stress. The IIP3 of the LNA was observed to improve with hot-carrier stress which is believed to be due to improvement in linearity of the I-V characteristics of the MOSFETs. The 1-dB compression point does not change with stress significantly. Simulation shows that the noise figure of the LNA also degrades with hot-carrier stress.
7B.4 RF S-PARAMETER DEGRADATION UNDER HOT CARRIER STRESS—J. Walko and B. Abadeer, IBM Microelectronics, Essex Jct., VT
Devices with channel length of 0.09 µm and oxide thickness of 2.2 nm were stressed for the hot carrier mechanism. The NFETS stressed at Vgs = ½ Vds and PFETs were stressed at Vds =Vgs. The changes in Sparameters due to hot carriers are quantified due to changes in threshold voltage, overlap capacitance and device resistance. Acceleration models for changes in S-parameters are shown to be consistent with device current degradation model.
Thursday, April 29, 8:00 a.m., Room A
8A PRODUCTS & CIRCUITS II (Parallel Session)
8A.1 (Invited) 6-T CELL CIRCUIT DEPENDENT GOX SBD MODEL FOR ACCURATE PREDICTION OF OBSERVED VCCMIN TEST VOLTAGE DEPENDENCY—K. Muellera, S. Gupta, S. Paeb, M. Agostinelli, and P. Aminzadeh, Intel, Hillsboro, OR
This paper describes a new monte carlo method coupling gate oxide soft breakdown, pmos bias-temp effect and circuit dependency for the 6-T SRAM cell. The model correctly predicts an observed test voltage dependency of the minimum stable vcc voltage for cache cells. Initial measured data correlate well with modeled results.
8A.2 A METHODOLOGY FOR ACCURATE ASSESSMENT OF SOFT-BROKEN GATE OXIDE LEAKAGE AND THE RELIABILITY OF VLSI CIRCUITS—P.W. Mason, M.A. Alam, A.J. La Duca, C.H. Holder, Agere Systems, Allentown, PA, and D.K. Hwang, Micron Technologies, Boise, ID
We present a comprehensive methodology modeling, as a function of time, increased standby leakage current of VLSI circuits due to soft-breakdown. Predictions using a leakage scaling model and device level TDDB data, agree remarkably well with observations of circuit leakage. The implications regarding the appropriate evaluation of the absolute reliability of intrinsic, ultra-thin oxides are discussed.
8A.3 A CHIP AND PIXEL QUALIFICATION METHODOLOGY ON IMAGING SENSORS—Y. Chen, S.M. Guertin, M.Petkov, D.N. Nguyen, JPL, Pasadena, CA, and F. Novak, NASA Langley Research Center, Hampton, VA
This paper presents a qualification methodology on imaging sensors. In addition to overall chip reliability characterization based on sensor's overall figure of merit, such as Dark Rate, Linearity, FPN and PRNU, a simulation technique is proposed to project pixel reliability which is directly related to imaging quality and provide additional sensor reliability information and performance control.
8A.4 HOT-CARRIER STRESS INDUCED LOW-FREQUENCY NOISE DEGRADATION IN 0.13µm AND 0.18µm RF CMOS TECHNOLOGIES—Z. Jin, J.D. Cressler, Georgia Tech, Atlanta, GA, W. Abadeer, X. Liu, M. Hauser, and A.J. Joseph, IBM Microelectronics, Essex Jct., VT
We investigate the impact of hot-carrier stress on low-frequency noise of 0.13µm and 0.18µm RF-CMOS technologies. The nFETs and pFETs show a different dc and low-frequency noise degradation response after time-dependent hot-carrier stressing. The underlying noise degradation mechanisms are investigated with the aid of 2-D device-level microscopic noise simulation.
8A.5 QUALIFICATION METHOD FOR DRAM RETENTION BY LEAKAGE CURRENT EVALUATION USING SUBTHRESHOLD CHARACTERISTICS OF CELL TRANSISTORS—Y.P. Kim, B.J. Jin, S.-G. Lee, S. Choi, U. Chung, J.T. Moon, and S.U. Kim, Samsung Electronics Co. Ltd., Korea
An evaluation method of MOS transistor leakage current using subthreshold characteristic parameters was introduced and its application to give an efficient way for qualification of retention property of DRAM products was investigated with a detailed consideration of the retention statistics of the DRAM cells
Thursday, April 29, 8:00 a.m., Room B
8B COMPOUND SEMICONDUCTORS (Parallel Session)
8B.1 HOT CARRIER RELIABILITY OF SiGe/Si HETERO-INTERFACE IN SiGe MOSFETS—T. Tsuchiya, Shimane Univ., Matsue, Japan, M. Sakuraba, and J. Murota, Tohoku Univ., Sendai, Japan
It has been shown for the first time that hetero-interfacee traps are generated by hot carriers in SiGe/Si heterostructures, and the trap density is estimated, using a newly established low-temperature charge pumping technique in SiGe-CHANNEL MOSFETS. These results will enable a new level of improvements to the performance and reliability of strained-Si and SiGe devices.
8B.2 ENHANCED HOT-ELECTRON PERFORMANCE OF STRAINED Si NMOS OVER UNSTRAINED Si—D.Q. Kelly, D. Onsongo, S. Dey, UT Austin, TX, R. Wise, R. Cleavelin, TI, Dallas, TX , and S.K. Banerjee, UT Austin, TX
Strained Si/relaxed Si1-xGex heterostructures provide a viable means of improving CMOS performance. For NMOS devices, the tensile strain in pseudomorphic Si on relaxed Si1-xGex splits the six-fold degeneracy of the conduction band minimum, rendering increased electron mobility due to a lower in-plane effective mass and reduced intervalley scattering. We present strained Si hot-electron degradation characteristics for the first time, showing improvement over unstrained Si.
8B.3 DEGRADATION MECHANISM OF GaAs PHEMT POWER AMPLIFIERS UNDER ELEVATED TEMPERATURE LIFETEST WITH RF-OVERDRIVE—Y.C. Chou, R. Grundbacher, M. Yu, D. Leung, L. Callejo, R. Lai, D. Okazaki, B. Yamane, K. Kiyono, Q. Kan, D. Eng, P.H. Liu, and A. Oki, Northrop Grumman Space Technology, Redondo Beach, CA
The degradation mechanism of 0.15 µm GaAs PHEMTs subjected to 3-temperature elevated lifetest under RF-overdrive was investigated. The results show that the Pout degradation is due to Ids degradation induced by Ti interdiffusion into the AlGaAs layer. The DIMAX, DGmp, and Ti sinking depth depend on the RF-drive levels. Accordingly, a distinct difference of reliability performance between DC lifetest (no RF-overdrive) and RF-overdrive lifetest was demonstrated for the first time.
8B.4 BIPOLAR SCR ESD PROTECTION IN 0.25 µm Si-Ge PROCESS USING SUB-COLLECTOR REGION MODIFICATION—V.A. Vashchenko, A. Concannon, M. ter Beek and P. Hopper, National Semiconductor Corp., Santa Clara,
Reliable ESD operation of new Bipolar SCR (BSCR) devices for 0.25 µm Si-Ge process with shallow epi was studied. Two new BSCR device variants are proposed and validated using 2-D physical process and device simulation followed by the test chip based ESD measurements. Both variants rely on modifications to the subcollector to reduce P-SCR-emitter region isolation.
8B.5 FAILURE MECHANISMS OF GaN-BASED LEDs RELATED WITH INSTABILITIES IN DOPING PROFILE AND DEEP LEVELS—G. Meneghesso, S. Levada, E. Zanoni, Univ. of Padova, Italy, G. Salviati, N. Armani, F. Rossi,IMEM-CNR Institute, Italy, M. Pavesi, M. Manfredi, Univ. of Parma, Italy, A. Cavallini, A. Castaldini, Univ. of Bologna, Italy, S. Du, and I. Eliashevich, GELcore LLC, Valley View, OH
Failure mechanisms of GaN/InGaN visible LEDs have been studied by means of EL and CL spectra, emission microscopy, I-V, C-V and DLTS profiling. Instabilities in the p-type GaN Layers as well as growth of non radiative centers are likely to be responsible for the observed degradation in emitted optical power.
Thursday, April 29, 8:25 a.m., Room C
8C PROCESS INTEGRATION (Parallel Session)
8C.1 (Invited) Integration issues of high-k gate stacks--G. Bersuker,International SEMATECH, Austin, TX
8C.2 IMPACT OF GATE SIDEWALL SPACER STRUCTURES ON DRAM CELL TRANSISTORS UNDER FOWLER-NORDHEIM AND GATE-INDUCED-DRAIN-LEAKAGE STRESS CONDITIONS—K.-Y. Lim, S.-A. Jang, Y.S. Kim, H.-J. Cho, J.-G. Oh, S.-O. Chung, S.-J. Lee, W.-Ky. Sun,J.-B.m Suh, H.-S. Yang, and H.-C. Sohn, Hynix Semiconductor Inc., Korea
We investigated the reliability of DRAM cell transistors with two different gate spacer structures under F-N or GIDL stress in terms of gate oxide SILC, junction leakage, GIDL, and Id-Vg characteristics. It was found that nitride/oxide/nitride spacered device was more degraded by GIDL stress than oxide/nitride spacered one.
8C.3 PATTERN DENSITY EFFECT OF TRENCH ISOLATION-INDUCED MECHANICAL STRESS ON DEVICE RELIABILITY IN SUB-0.1 µm TECHNOLOGY—J.R. Shih, Y.M. Sheu, H.C. Lin and K. Wu, TSMC, Taiwan
Pattern density effect of STI-induced mechanical stress on device reliability in sub-0.1µm technology has been characterized and analyzed. Reducing the space between gate edge and STI edge will increase compressive stress, but will not degrade hot carrier lifetime.
8C.4 INVESTIGATION OF MISFIT DISLOCATION LEAKAGE IN SUPERCRITICAL STRAINED SILICON MOSFETs—J.G. Fiorenza, G. Braithwaite, C. Leitz, M.T. Currie, Z.Y. Cheng, V.K. Yang, T.A. Langdo, J. Carlin, AmberWave Systems Corp., Salem, NH, M. Somerville, Franklin W. Olin College of Engineering, Needham, MA, A. Lochtefeld, H. Badawi, and M.T. Bulsara, AmberWave Systems Corp., Salem, NH
This paper investigates off-state current leakage in strained silicon MOSFETs built on supercritical strained silicon films. It proposes a simple conceptual model for the off-state leakage: it is caused by a combination of surface and sub-surface leakage paths created by enhanced dopant diffusion near misfit dislocations. It shows DC IV characteristics and photon emission microscopy images of NMOSFETs with several different supercritical strained silicon thickness values. Finally it demonstrates that the response to an applied gate or substrate voltage of the IV characteristics and the emission data can be understood within the context of the proposed conceptual model.
8C.5 A LOW COST TEST VEHICLE FOR EMBEDDED DRAM CAPACITOR: INVESTIGATION AND MONITORING OF THE PROCESS—L. Lopez, STM, & Lab. de Microélectronique, France, D. Nee, STM, France, P. Masson, and R. Bouchakour, Lab. de Microélectronique, France
A low cost test vehicle for embedded DRAM capacitor is developed. This test vehicle allows us to get planar DRAM capacitors for process investigation and monitoring. We show that in-line AFM is a monitoring tool for HSG deposition. We show that the leakage of the DRAM capacitor is linked to its intrinsic reliability.
8C.6 RELIABILITY CONCERN AND MODEL OF USING TaN AS PRECISION THIN FILM RESISTOR—T.C. Lee and K. Watson, IBM Microelectronics, Essex Jct., VT
As IC technology advances, the circuits require the high precision resistors over a broad range of use conditions for temperature and current. The TaN resistors provide a viable circuit element for both logic and analog circuits. TaN can produce high precision resistors with small, negative values of temperature coefficient of resistance. Therefore, understanding the TaN material becomes important for reliability. This paper reports the TaN stability with respect to temperature, current, and time. The maximum allowed use current of TaN resistor is also discussed from the prospects of interconnect conductor and TaN material itself.
Thursday, April 29, 10:30 a.m., Room A
9A MEMORY II (Parallel Session)
9A.1 STATISTICAL ANALYSIS OF NANOCRYSTAL MEMORY RELIABILITY—C.M. Compagnoni, D. Ielmini, A.S. Spinelli, A.L. Lacaita, Politecnico di Milano, Milano, Italy, C. Gerardi, STM, Catinia, Italy, and S. Lombardo, CNR-IMM, Catania, Italy
This paper shows a detailed statistical analysis of reliability for nanocrystal memories. Anomalous cells in large nanocrystal memory arrays (256kbit) are characterized by field-accelerated data-retention experiments after cycling. Our data and a comparison with state-of-the-art Flash demonstrate, for the first time, the array-level SILC-immunity of nanocrystal memories. We finally show that Monte Carlo calculations of SILC and lateral tunneling among nanocrystals allow for an order-of-magnitude estimate of retention failure.
9A.2 A NEW CHANNEL PERCOLATION MODEL FOR VT SHIFT IN DISCRETE-TRAP MEMORIES—D. Ielmini, C.M. Compagnoni, A.S. Spinelli, A.L. Lacaita, Politecnico di Milano, Italy and C. Gerardi, STM, Italy
In this paper we investigate channel transport in discrete-trap memories. We presenta new percolation model, able to evaluate the memory VT shift and spread as a function of gate size, trap density and trapped charge. The model allows for an accurate evaluation of the channel-control factor R, relating trapped charge and VT shift in the memory. The impact of the percolation mechanism from the reliability point of view is finally discussed.
9A.3 CAUSE OF ERASE SPEED DEGRADATION DURING TWO-BIT PER CELL OPERATION OF A TRAPPING NITRIDE STORAGE FLASH MEMORY CELL—W.J. Tsai, N.K. Zous, M.H. Chou, S. Huang, H.Y. Chen, Y.H. Yeh, M.I. Liu, C.C. Yeh, T. Wang, J. Ku, and C.-Y. Lu, Macronix International Company, Ltd., Taiwan
Erase speed degradation in a dual-bit, trapping nitride storage flash memory cell is investigated. Our study shows that the trapped-charge area of the second-programmed bit would extend more toward the central channel region if its neighboring bit (of the same cell) has been programmed. The second bit would then be erased slower. This effect gets more obvious after P/E cycling. In addition, the erase speed would be modulated by adjacent junction biases in a short-channel, nearly punch-through cell.
9A.4 RETENTION LOSS CHARACTERISTICS OF LOCALIZED CHARGE-TRAPPING DEVICES—E. Lusky, Saifun Semiconductors Ltd., Israel, Y. Shacham-Diamand, A. Shappir, Tel Aviv Univ., Israel, I. Bloom, G. Cohen, and B. Eitan, Saifun Semiconductors Ltd., Israel
Retention after cycling theory is proposed, extending the lateral re-distribution model. The retention loss is due to the lateral re-distribution of holes trapped in the ONO dielectric stack, above the n+ junction. Electrons that are localized in deeper traps exert an electric field that directs the hole transport towards the channel.
Thursday, April 29, 10:30 a.m., Room B
9B ASSEMBLY & PACKAGING
9B.1 ELECTRICAL FAILS SPECIFIC TO PRESSURE COOKER TEST—L. Wiggins, C. Perry, E. Dyll, J. Coffin, M. Fausse, and M. Kuzuno, IBM, Hopewell Jct., NY
The commonly accepted practice of subjecting electronic components to accelerated aging or stress, for reliability studies, produces a useful result if the test does not result in unrealistic modification of the product. The PCT calls for the relative humidity to be 100%. The high activity of water extracted Br from the solder mask and the build up material as the bromide ion which catalyzed the unusual formation of Sn oxides. The resulting 33% volume expansion provided the over pressure which drove the extrusion of the high melt solder between C4s at temperatures far below its melting point. This emphasizes the need for through failure analysis and an understanding of the chemical systems involved in the testing!
9B.2 DEGRADATION MECHANISMS OF SILOXANE-BASED THERMAL INTERFACE MATERIALS UNDER RELIABILITY STRESS CONDITIONS—S.L.B. Dal and A. Aguinaldo, Intel Technology Philippines Inc., Philippines
This paper describes the degradation behavior of siloxanes as thermal interface materials in semiconductor packages. A good correlation was established between known chemical reactions and material and failure analysis data after stress. With these data, a good understanding of the reliability performance of siloxanes as thermal interface material was established.
9B.3 DENDRITE FUSE REGROWTH KINETICS ON ORGANIC SUBSTRATES FOR MICROPROCESSORS—D. Lambert, R. Gannamani, and R.C. Blish, II, AMD, Sunnyvale, CA
The kinetics of fuse crystal growth during Temperature Humidity Bias (THB) stresses were modeled with a Peck Law exponent of ~3.5 for Relative Humidity (RH) and a power law for bias voltage (exponent ~1.35). Using these results we determined the optimal laser cut parameters to maximize product reliability.
9B.4 EFFECT OF VACUUM ON HIGH-TEMPERATURE DEGRADATION OF GOLD/ALUMINUM WIRE BONDS IN PEMs—A. Teverovsky, GSFC/NASA, Greenbelt, MD
Degradation of three types of PEMs during high-temperature ageing in air and vacuum has been studied. The results show that the presence of oxygen in ambient significantly increases the failure rate and the dry corrosion of gold/aluminum wire bond is a major failure mechanism.
9B.5 PACKAGING EFFECT ON RELIABILITY FOR Cu/LOW k STRUCTURES—G. Wang, UT Austin, Austin, TX, S. Groothuis, Micron Technology, Allen, TX and P.S. Ho, UT Austin, Austin, TX
In this paper, we employed 3D finite element analysis (FEA) based on a multilevel sub-modeling approach in combination with high-resolution moire interferometry to examine the packaging effect on low k interconnect reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures.
Thursday, April 29, 12:35 p.m., Room B
2005 IRPS COMMITTEE INTRODUCTION
| Make Plans Early for 2005 The 2005 IEEE International Reliability Physics Symposium will be held April 17 - 21, 2005 at the San Jose Convention Center, San Jose, California. Visit our web site www.irps.org for the Call for Papers and watch for the 2005 Preliminary Program early in 2005 for Symposium details. |
