Effects of Reliability Mechanisms on VLSI Circuit functionality

This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to activate latent defects and screen out those chips that cannot meet product specifications for performance, power and operating margins. The advent of degraded VLSI circuit operating margins due to the activated defects as well as reliability mechanisms such as negative bias temperature instability (NBTI), hot carrier injection (HCI), and others will be discussed. How these failing circuits can then manifest themselves in observed product failures will also be discussed.

Wayne F. Ellis received the A.A.S. in Electrical Technology from Hudson Valley Community College in 1974. He joined the IBM East Fishkill facility where he worked as a layout technician on MOS logic chip designs capable of containing up to 120 NAND gates. He received the BSEE from Union College in 1985, and MSEE and Ph.D. in Materials Science from the University of Vermont in 1992 and 1993. From 1977 to the present he has worked at the IBM Microelectronics division labs in Essex Junction Vermont, in DRAM, eDRAM and eSRAM product and technology development. Dr. Ellis spent the fall semester 2002 at the University of Linkoping, Sweden as a Distinguished Visiting Professor in Information Technology, under the auspices of the Swedish and American Fulbright Associations. He is an Adjunct Professor at the University of Vermont and also serves on the Board of Directors for the Vermont Fulbright Association.