NBTI: Device & Circuit Issues

PMOS negative bias temperature instability (NBTI) has become one of the key reliability concerns in recent years, resulting in a significant activity in this area. Several interesting phenomena have been discovered/rediscovered, such as recovery and frequency effects. This tutorial will review these recent results and its implications on device and circuit reliability. Models proposed to describe the degradation/recovery kinetics will be discussed. In addition, incorporation of NBTI degradation into SPICE models will also be addressed.

Anand T. Krishnan received his B. Tech in Metallurgical Engineering from Institute of Technology, BHU, (Varanasi, India) in 1994, and M.S. and Ph. D degrees in Materials from The Pennsylvania State University in 1997, and 2000, respectively. In 2000, he joined the silicon technology development group at Texas Instruments, where he is currently working as a Reliability Engineer. He has two issued patents, and has authored/co-authored 18 conference presentations/publications and one IRPS tutorial. He has served in the program committees for IRPS and P2ID. His interests and activities are in the areas of charging damage and negative bias temperature instability.