Software Approaches to Mitigating SERs

The effects of bit flips (SEUs) occurring in a processor-based architecture as a consequence of the interaction with energetic particles can be attenuated by using hardware or software fault tolerance techniques. This tutorial explores the efficiency of a set of rules transforming a target program providing it with on-line capability of detecting bit-flips perturbing the program execution. Advantages and limitation of this purely software strategy will be discussed and illustrated by practical examples.

Fabien Faure received his B.S. in physics from University of Montpellier in 1998, and holds a M.S. in electrical engineering and computer science from University of Grenoble. He is currently finishing his Ph.D. at TIMA Laboratory, Grenoble (France). His research topics include the study of radiation effects on advanced microelectronics circuits and methodologies for microprocessor SEU testing.