Simulation Techniques for FPGA Soft-Errors

This talk will introduce a technique to simulate the effects of soft-errors in SRAM-based FPGAs. This technique evaluates the behavior of an FPGA by artificially inserting errors within the configuration memory of the device. The FPGA is carefully monitored and compared to a golden standard to identify discrepancies in device operation. Sensitive configuration bits are recorded to create a sensitivity map for the FPGA design. The results from this testing method will be presented for several FPGA designs.

Michael J. Wirthlin receieved his B.S. and Ph.D. degrees from Brigham Young University (BYU) in 1992 and 1997, respectively. After completing his B.S. degree in 1992, he worked at a small start-up in Salt Lake City designing high-performance sound processing circuits using FPGAs. After completing his Ph.D., he worked as a Staff Research Engineer in the Systems Architecture Laboratory at National Semiconductor Corporation in Santa Clara, CA. At National, he participated in efforts to model and specify large, single-chip systems including the single-chip PC. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at BYU. His research interests include configurable computing, system modeling, reliability techniques for FPGAs, and computer-aided design for application-specific computing.