Gate Oxide Reliability Methodology and Models

Gate oxide affects the competing features performance and reliability of CMOS circuits. Accurate reliability evaluation is necessary to support the performance goals. This tutorial summarizes the methods and models used for state-of-the-art gate oxide reliability assessment. The physics of current conduction and breakdown are briefly reviewed. Then the statistical nature of breakdown and it's usual evaluation methods are presented. Different breakdown types and the consequences for devices are described. Finally an overview over acceleration models is given.

Rolf-Peter Vollertsen received his doctoral degree (Ph.D.) in 1987 in material science engineering from the University of Erlangen, Germany. Since joining the microelectronics division of Siemens AG in Munich, Germany his research focused on thin and ultra-thin single and multi layer dielectric quality and reliability. He spent several years in the DRAM Development Alliance, a cooperation between IBM and Infineon Technologies (formerly Siemens Semiconductor Division), and temporarily also Toshiba, at the IBM Microelectronics Division site in Essex Junction, Vermont. Dr. Vollertsen works currently at Infineon Technologies's central Reliability Methodology department in Munich, Germany, on fast wafer level reliability test development for DRAM and logic technologies. His field of interest is reliability assessment and modeling of thin dielectrics. He authored and co-authored numerous journal and conference papers. Dr. Vollertsen served on technical committees of different conferences and is the Technical Program Chair of IRW 2004.