Reliability Issues on High-k Gate Dielectrics - What is Different from SiO2?

Hideki Satake
Takeshi Yamaguchi, Masato Koyama
Izumi Hirano, Yuichiro Mitani
Advanced Technology Laboratory, Corporate R&D Center
Toshiba Corporation

High-k materials are indispensable for gate dielectrics in future ULSI. However, some serious reliability issues exist for realizing high-k gate dielectrics. Especially, long-term reliability is one of the most serious concerns. The understanding of the basic reliability physics concerning the high-k materials will become a key point to realizing the high-k gate dielectrics in the ULSI processes. In this tutorial, recent noteworthy topics on the reliability issues of high-k gate dielectrics are discussed from the viewpoint of comparison between high-k and SiO2.

Hideki Satake received the B.S. and M.S. degrees in material processing from Tohoku University, Sendai, Japan, in 1984 and 1986, respectively. He joined the Research and Development Center of Toshiba Corporation, Kawasaki, Japan, in 1986, where he was engaged in the research on physical and electrical properties of the Si bipolar devices and the thin dielectrics for gate oxides in Si MOSFETs. He has been with the Toshiba Advanced LSI Technology Laboratory, Kawasaki, since 1999. His research interests include the physics and engineering of the reliability of thin gate dielectrics. Mr. Satake received the Outstanding Paper Award in the IEEE International Reliability Physics Symposium in 1998, and the SSDM Paper Award in the International Conference on Solid State Devices and Materials in 2001. He has served on the technical program committee of the International Reliability Physics Symposium and the Solid State Devices and Materials. He is a member of the Japan Society of Applied Physics and the Japanese Society for Synchrotron Research.

Takeshi Yamaguchi received the B.S. (1992), M.S. (1994) and Ph.D. (1997) in materials science from the University of Tsukuba, Ibaraki, Japan. He joined the Advanced LSI Technology Laboratory, TOSHIBA Corporation, Yokohama, Japan, in 1997, where he was engaged in the research on the physics and technology of the ferroelectric devices. Since 1999, he has been engaged in the research on the physics and properties of high-k gate dielectrics. His current interests are the electrical characteristics and reliability physics of the MISFET with high-k gate dielectrics.

Masato Koyama received the B.S., M.S. and Ph.D. degrees in electrical and electronic engineering from Waseda University, Tokyo, Japan, in 1992, 1994, 1998 respectively. He joined the Corporate Research and Development Center, Toshiba Corporation, Kawasaki, Japan, in 1994, where he was engaged in the research on characterization of defects in Si and metal/Si interfaces. He has been also engaged in the physics and technology of non-volatile device using ferroelectric materials. He is currently working on physical and electrical characterization of high-k gate stacks. Dr. Koyama is a member of the Japan Society of Applied Physics.

Izumi Hirano received the B.S. and the M.S. degrees in physics from Kyoto University in 2000 and 2002, respectively. In 2002, she joined the Research and Development Center, Toshiba Corporation, Kawasaki, Japan. Her research interests include the reliability physics of new materials for Si ULSIs, especially of high-k gate dielectrics materials. She received the Young Scientist Award for the Presentation of the Excellent Paper from the Japan Society of Applied Physics in 2004. Ms. Hirano is a member of the Japan Society of Applied Physics.

Yuichiro Mitani received the B. E. and M. E. in material science and engineering from Tohoku University, Sendai, Japan, in 1990 and 1992, respectively. He joined the R&D Center, Toshiba Corporation in 1992. His primary works were concerned in the Si-CVD and the ultra-shallow junction process technology. Since 1999, he has been with the Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama, Japan. His present research interests and activities cover the ultra-thin oxide process technology and the study of the reliability of ultra-thin gate oxide layer for VLSI technology. He is a member of the Japan Society of Applied Physics.