Girish Dixit
Applied Materials

The presentation on "Integration Issues for Cu/Low-k Interconnects" will cover some of the schemes used to integrate CDO based films. The issue of via poisoning is discussed for the via first dual damascene integration scheme. Techniques to over come via poisoning in this flow are presented. Case studies are used to illustrate the differences in poisoning characteristics while using different unit process steps such as types of resist, wet clean chemistries etc. The presentation also covers the aspect of interface properties control for producing mechanically stable stacked structures. Key aspects of processing for improving dielectric isolation reliability are discussed. Copper barrier and seed deposition process together with its impact on via resistance and reliability is also presented. A case study for a Cu B/S and plating related integration defect is presented. The presentation concludes with a short discussion of the scalability of the Cu CMP process.