Planarization for Cu/Low k Interconnects

In this session, planarization processes for Cu/low k Interconnects will be reviewed. Special focus will be on how to control the process parameters and to select adequate consumables design to achieve low defect and compatibility to low k materials. We will discuss the impact of post CMP clean on the device performance, e.g. TDDB and breakdown. An overview of future development on planarization of Cu other than chemical mechanical polish will also be presented.

Wei-Yung Hsu is Head of the CMP Product Technology, CMP Product Business Group of Applied Materials. Previously, he was responsible for the Copper Metallization Module for Texas Instruments, SiTR, Dallas, TX. He received his Ph.D. in Materials Science and Engineering from Cornell University, where he investigated integrated non-linear optical devices.