Via Stress Migration and Via Voiding

Stress levels in copper interconnects can be very high due to the differential thermal contraction of copper and the dielectric. Wafer processing includes multiple thermal cycles to temperatures of ~400°C and circuit operating conditions that can approach ~200°C. This tutorial will focus on three forms of failure that can occur from thermally induced stress in copper. The first is a loss in yield due the separation of weak interfaces that cannot withstand high local stress. The second failure occurs with the slow relaxation of copper stress after a long period at ambient conditions (creep). Finally, multiple thermal cycles such as those induced by power cycling can exaggerate interface failures such as cracks. Low-k materials are especially sensitive to these failures because of their large thermal expansion coefficient and poor adhesion. Each of these three failure mechanisms will be reviewed and critical process steps identified to control the failures.

Glenn Alers received his PhD in 1991 from the University of Illinois, Urbana-Champaign. He was a Research Associate in the Physics Department of Michigan State University for two years before joining Bell Laboratories as a member of technical staff in 1993. While at Bell Laboratories he worked on reliability issues for silicon based circuits including electromigration, thin gate oxide reliability and high-k dielectrics. From 2000 to the present, he has been a senior process manager at Novellus Systems working on integration and reliability issues associated with copper / low k interconnects.