SiGe and Si Base RF Technologies; Device Models and Characterization, Circuit and System Applications and Reliability Issues.

RF Technologies and its application such as wireless systems have seen new focus and an increased level of significance. The continuing downs scaling of CMOS technologies has produced significant improvement in RF performance. In this tutorial the basic elements of RF devices and their RF modeling methodology will be reviewed. Common model errors and their avoidance, layout related issues, Monte Carlo and model override methods, as well as device linearity and stress effects will be discussed. RF circuits and system level applications will be reviewed. Critical circuit parameters, measurements and characterization, and effect of parameter variations on system performance will be discussed. RF parameters such as 1/f noise and S-parameters can degrade as a result of reliability degradation mechanisms such as gate-oxide hard and soft breakdown, hot carriers and NBTI. In this tutorial, physics and model development for RF device and circuit RF parameter degradation will be reviewed.

Bill W. Abadeer is a Senior Engineer with the Quality and Reliability Engineering group at the Burlington facility of the IBM Microelectronics Division. He joined IBM at the Burlington facility in 1976 and has since worked on the reliability of semiconductor devices. Dr. Abadeer received his M.S. and Ph.D. degrees in electrical engineering in 1970 and 1976 respectively, from the University of Vermont. From 1968 to 1976, Dr. Abadeer received teaching and research fellowships at the University of Vermont. Dr. Abadeer is a member of the IEEE and the Electrochemical society, he published extensively and has several patents.

Joe Walko (joswalko@us.ibm.com) is an engineer at the IBM Microelectronics Division facility in Essex Junction, Vermont. Since joining IBM in 1996 he has been active in solving plasma-physics related manufacturing problems and since 1998 has been active responsible for developing compact models for low and high frequency applications. Most recently, Joe was the technical team leader for 0.13 um bulk Si model development and has been active creating RF MOSFET models for 90nm applications. Joe holds a Ph.D. in Superconducting Device Physics from the University of Illinois.

Tony Bonaccio is a Distinguished Engineer at the IBM Microelectronics Division facility in Essex Junction, Vermont. Since joining IBM's analog and mixed-signal design group in 1979, Tony has been responsible for the design and development of a wide variety of analog integrated circuit products. Tony's main focus has been on integrated circuits for hard disk drives, including custom interface driver chips, phase locked loop chips, and low-noise preamplifiers for magneto-resistive heads. Most recently, Tony was the technical team leader for the development of CMOS and biCMOS partial-response, maximum likelihood (PRML) data channel chips for use in IBM's mobile and consumer hard disk drives. His current assignments include high-speed serial interface and data converter cores for IBM microprocessors and ASICs. Tony holds a Bachelor of Science in Electrical Engineering from the University of Rochester (NY) and a Master of Science in Electrical Engineering from the University of Vermont. He holds 27 United States patents in the area of analog integrated circuit design and has 10 pending. He is a Senior Member of the IEEE and an Adjunct Professor of Electrical and Computer Engineering at the University of Vermont, where he has offered graduate-level courses in MOS and bipolar analog circuit design since 1988.