Technical Program

Tuesday, April 19, 8:00 a.m., Room A, Plenary Session

• Symposium Opening—Timothy Rost, General Chair and Ed Cole, Jr., Technical Program Chair

• Keynote: David W. Yen, Ph.D., Executive Vice President, Scalable Systems Group, Sun Microsystems, Inc.

• Jim Black Retrospective—Jim Lloyd, IBM

• 2004 IRPS Best/Outstanding Paper Awards—Carole Graas, 2004 IRPS Technical Program Chair

Tuesday, April 19, 10:05 a.m., Room A, Plenary Session

2A HIGH k DIELECTRICS

Co-Chairs: Masaaki Niwa, Panasonic and Barry P. Linder, IBM

2A.1 SINGLE-ELECTRON EMISSION OF TRAPS IN HfSiON AS HIGH-k GATE DIELECTRIC FOR MOSFETs—C.T. Chan, C.J. Tang, C.H. Kuo, C.W. Tsai*, H. C.-H. Wang*, M.H. Chi*, and T. Wang, National Chiao-Tung Univ., Hsin-Chu, Taiwan *TSMC, Hsin-Chu, Taiwan

A novel method for characterizing MOSFET with (HfSiON) high-k gate dielectric is demonstrated for the 1st time by direct measurement of single electron de-trapping behavior. The physical path of de-trapping can be identified from the emission time of such single-electron de-trapping. An analytical model based on thermally assisted tunneling can predict the emission time behavior, trap activation energy, trap density, and total available traps in high-k dielectric.

2A.2 TRAP GENERATION AND PROGRESSIVE WEAROUT IN THIN HfSiON—T. Kauerauf⁺, R. Degraeve, IMEC, Leuven, Belgium, F. Crupi, Univ. of Calabria, Arcavacata di Rende, Italy, B. Kaczer, G. Groeseneken⁺, and H. Maes⁺, IMEC Leuven, Belgium ⁺IMEC and KU Leuven

The degradation and breakdown of thin nitrided Hf-silicate under Constant Voltage Stress is evaluated. Two main mechanisms proceed simultaneously: the formation of percolating paths and the wearout of those localized paths. We demonstrate that sufficient reliability can only be guaranteed when the progressive wearout phase is taken into account.

2A.3 PBTI & HCI CHARACTERISTICS FOR HIGH-k GATE DIELECTRICS WITH POLY-Si & MIPS (METAL INSERTED POLY-Si) GATES—H.-S. Jung, S.K. Han, M.J. Kim, J.P. Kim, Y.-S. Kim, H.J. Lim, S.J. Doh, J.H. Lee, M.Y. Yu, J.-H. Lee, N.-I. Lee, H.-K. Kang, S.G. Park and S.B. Kang, Samsung Elect. Co., Ltd., Yongin-City, Korea

Reliability characteristics of high-k gate dielectrics with poly-Si gate and metal gate inserted poly-Si(MIPS) gate are investigated in terms of PBTI and HCI characteristics. The results indicate that the dopants(P or As) from the poly-Si severly degrade PBTI and HCI characteristics. Therefore, the high-k/MIPS stack, which is not influenced by gate dopants, shows significant improvement in PBTI and HCI characteristics. By the same reason, the worst HCI condition of high-k/poly-Si stack is V_g=V_d instead of V_g at I_sub-max, while that of high-k/MIPS stack is V_g at I _{sub_max}.

2A.4 INTERFACE STATES IN HfO₂ STACKS WITH METAL GATE: NATURE, PASSIVATION, GENERATION— X. Garros⁽¹⁾, G. Reimbold⁽¹⁾, D. Duret⁽¹⁾, C. Leroux⁽¹⁾, B. Guillaumot^(1,2), O. Louveau^(1,2), C. Hobbs⁽³⁾, and F. Martin⁽¹⁾ (1) CEA-Leti, Grenoble, France, (2) STMicroelectronics, Crolles, France, (3) Freescale, Crolles, France

Interface states D_it nature, passivation and generation in TiN/HfO₂ is deeply investigated. The Si/SiO₂ interface is modified by RTP anneals and is passivated by FGA at T>500°C for capacitors and 425°C for NMOS. The lowest D_it density is obtained after H⁰ plasma anneal. Finally similar interface degradation is observed whatever the FGA temperature, contrary to bulk degradation.

2A.5 HIGH-k DIELECTRICS BREAKDOWN ACCURATE LIFETIME ASSESSMENT METHODOLOGY—G. Ribes^(1,2), S. Bruyère⁽¹⁾, M. Denais^(1,3), F. Monsieur⁽¹⁾, D. Roy⁽¹⁾, E. Vincent⁽¹⁾, and G. Ghibaudo⁽²⁾ (1) STMicroelectronics, Crolles, France, (2) IMEP-ENSERG, Grenoble, France, (3) L2MP-SEM, Toulon, France

In this paper we propose a statistical analysis of the breakdown linking the PBD to the breakdown of the interfacial layer and the SBD or HBD to the high-k layer breakdown. Based on this analysis we study the degradation mechanisms and we demonstrate that the MVHR process is the prevalent mechanism which drives the interfacial layer breakdown.

2A.6 THERMOCHEMICAL UNDERSTANDING OF DIELECTRIC BREAKDOWN IN HfSiON WITH CURRENT ACCELERATION—T. Yamaguchi, I. Hirano, R. Iijima, K. Sekine, K. Eguchi, M. Takayanagi, Y. Mitani and N. Fukushima, Toshiba Corp., Yokohama, Japan

Based on experimental results, the suitable lifetime projection of the breakdown and its mechanisms in HfSiON were well discussed. In HfSiON, the total hole fluence to breakdown is not dominant factor. We proposed that the thermochamical breakdown with the acceleration by injected carriers is the primary degradation mechanism in Hf SiON dielectrics, especially at high temperature

2A.7 INTERFACIAL LAYER DEPENDENCE OF HfSi_XO_Y GATE STACKS ON V_T INSTABILITY AND CHARGE TRAPPING USING ULTRA-SHORT PULSE I-V CHARACTERIZATION—C.D. Young, R. Choi, J.H. Sim, B.H. Lee⁽¹⁾, P. Zeitzoff⁽²⁾, Y. Zhao, K. Matthews, G.A. Brown, and G. Bersuker, SEMATECH, Austin, TX (1) IBM assignee, SEMATECH, Austin, (2) Keithley Instruments, Solon, Ohio

The ultra-short pulse I-V measurement technique and bias dependence is shown to provide unique capability for the investigation of the intrinsic properties of high-k gate stacks. It is found that the fast electron trapping is a significant source of DC measurement degradation observed in high-k devices and the electron trapping process is found to be strongly dependent on the interfacial layer

2A.8 COMPARISON OF NMOS AND PMOS STRESS FOR DETERMINING THE SOURCE OF NBTI IN TiN/HfSiON DEVICES—H.R. Harris, R. Choi, B.H. Lee, C.D. Young, J.H. Sim, K. Mathews, P. Zeitzoff, P. Majhi, and G. Bersuker, SEMATECH, Austin, TX

The understanding of NBTI reliability is confounded by the presence of charge trapping in hi-K dielectrics. Using observations of PMOS and NMOS under comparable negative stress, an understanding of the charge trapping effect and its correlation to threshold voltage instability is studied. A model is proposed that explains the change in threshold voltage and it recoverability.

Tuesday, April 19, 2:00 p.m., Room B, Parallel Session

2B ESD

Co-Chairs: Gianluca Boselli, Texas Instruments and
Warren R. Anderson, Intel Massachusetts, Inc.

2B.1 ESD INDUCED DAMAGE ON ULTRA-THIN GATE OXIDE MOSFETs AND ITS IMPACT ON DEVICE RELIABILITY—A. Cester, S. Gerardin, A. Tazzoli, A. Paccagnella, E. Zanoni,
G. Ghidini*, G. Meneghesso, Università di Padova, Padova, Italy *STM, Agrate Brianza, Italy,

The impact of ESD events on oxide breakdown MOSFET reliability and degradation under subsequent electrical stresses was studied. It was found that ESD stresses modify MOSFET characteristics immediately after ESD and during subsequent accelerated stresses, while not affecting TTBD. It was also found that ESD-induced damage increases with the reduction of the gate oxide thickness.

2B.2 INTERACTION BETWEEN ELECTROSTATIC DISCHARGE AND ELECTROMIGRATION ON COPPER INTERCONNECTS FOR ADVANCED CMOS TECHNOLOGIES— D.K. Kontos*, R. Gauthier, , D.E. Ioannou*, T. Lee, M. Woo, K. Chatty, C. Putnam, M. Muhammad, IBM, Essex Jct., VT * George Mason University, Fairfax, VA,

In this study, current carrying capability of Cu interconnects for EM prior to TLP stress and vice-versa was performed. It was found that TLP stress causes damage on Cu interconnects only when peak current value nears Jcrit and degrades EM lifetime. TLP-induced-degradation appears when Joule heating causes the temperature to increase above the melting point.

2B.3 STUDY OF FACTORS LIMITING ESD DIODE PERFORMANCE IN 90 nm CMOS TECHNOLOGIES AND BEYOND—K. Chatty, R. Gauthier, C. Putnam, M. Muhammad, M. Woo, R. Halbach and C. Seguin, IBM Systems and Technology Group, Essex Jct., VT

We report that the on-resistance and failure current of ESD diodes in 90 nm and 65 nm bulk CMOS technologies is largely determined by the resistance and failure of metal lines, contacts and vias. Through design optimization, P+/NWell diodes with an area of 330 µm² achieved 1.66V at 2A, on-resistance of 0.27 ohms and a TLP failure current >5A.

2B.4 ACCURATE PREDICTION OF THE ESD ROBUSTNESS OF SEMICONDUCTOR DEVICES THROUGH PHYSICAL SIMULATION—C. Salaméro, N. Nolhier, M. Bafleur, CNRS, Toulouse, France, and M. Zécri, Freescale, Toulouse, France

In this study, a new TCAD-based method to obtain failure current of devices stressed under ESD conditions is presented. By including full process simulation, this method allows an excellent ESD robustness prediction with a significantly reduced computation time. A smart power technology is used for experimental verification.

Tuesday, April 19, 4:05 p.m., Room B, Parallel Session

2C LATCHUP

Co-Chairs: Steven H. Voldman, IBM and
Ming-Dou Ker, National Chiao-Tung University

2C.1 INFLUENCE OF SILICON DIOXIDE-FILLED TRENCH ISOLATION (TI) STRUCTURE AND IMPLANTED SUB-COLLECTOR ON LATCHUP ROBUSTNESS—S.H. Voldman, E.G. Gebreselasie, L.W. Lanzerotti, N.B. Feilchenfeld, S.A. St. Onge, A. Joseph, and J. Dunn, IBM, Essex Jct., VT

This paper discusses CMOS latchup with a new low-cost oxide-filled trench isolation structure and implanted sub-collector for the first time. These results have significant value for CMOS, RF CMOS, and low-cost Silicon Germanium technology.

2C.2 EVALUATION ON EFFICIENT MEASUREMENT SETUP FOR TRANSIENT-INDUCED LATCHUP WITH BIPOLAR TRIGGER—M.-D. Ker and S.-F. Hsu, National Chiao-Tung Univ., Hsin Chu, Taiwan

An efficient measurement set-up for transient-induced latchup (TLU) using bipolar triggering is evaluated. The measurement methodology includes a current blocking diode and current-limiting resistance of both a silicon controlled rectifier and a ring oscillator structure.

2C.3 LATCHUP IN MERGED TRIPLE WELL STRUCTURE—S.H. Voldman, E.G. Gebreselasie, D. Hershberger, D.S. Collins, N.B. Feilchenfeld, S. A. St. Onge, A. Joseph, and J. Dunn, IBM, Essex Jct., VT

CMOS latchup in "merged triple-well" technology is discussed for the first time. These results are key for integration of merged triple well technology in order to improve noise isolation and latchup immunity in advanced CMOS, RF CMOS, and Silicon Germanium technologies.

2C.4 LATCH-UP IN 65 nm CMOS TECHNOLOGY: A SCALING PERSPECTIVE—G. Boselli, V. Reddy and C. Duvvury, Texas Instruments, Dallas, TX

A detailed analysis of four CMOS technology nodes latchup sensitivity is investigated. This study assesses the measure at which CMOS latchup will be a major reliability concern for future CMOS technologies.

2C.5 LATCHUP AND THE DOMINO EFFECT—S.H. Voldman, IBM, Essex Jct., VT

This paper discusses the analytical model for external latchup problem and the "domino effect" for the first time. An analytical development addresses the pimary and secondary current sources, the propagation mechanisms, temporal response and propagation truncation, as well as substrate and well resistance criteria to minimize propagation.

Tuesday, April 19, 2:00 p.m., Room C, Parallel Session

2D MEMORY I

Co-Chairs: Guoqiao Tao, Philips Semiconductors and
Hanmant Belgal, Intel

2D.1 (INVITED) RELIABILITY INVESTIGATION FOR MANUFACTURABLE HIGH DENSITY PRAM—K. Kim and S.J. Ahn, Samsung Electronics Co. Ltd., Yongin-City, Korea

This paper introduces Phase-Change Memory exploiting new memory material called chalcogenides. The reliability issues for high density commercial memory products such as operation temperature dependency, disturbance immunity, endurance and data retention have been evaluated by using 64Mb PRAM with 0.12 µm technology. Observed degradation modes and the underlying physical mechanism were investigated.

2D.2 RELIABILITY OF 4 MB MRAM—J. Akerman, P. Brown, M. Martin, H. Mekonnen, D. Gajewski, M. Griswold, and S. Tehrani, Freescale, Chandler, AZ

The reliability of magnetoresistive tunnel junction (MTJ) memory bits and the metal interconnect system of MRAM is demonstrated. A lifetime over 10 years is achievable under the operating condition. In addition. data retention is demonstrated over times longer than 10 years.

2D.3 NOVEL SOFT ERASE AND RE-FILL METHODS FOR A P+POLY GATE NITRIDE-TRAPPING NON-VOLATILE MEMORY DEVICE WITH EXCELLENT ENDURANCE AND RETENTION PROPERTIES—H.-T. Lue, Y.-H. Shih, K.Y. Hsieh, R. Liu and C.Y. Lu, Macronix International Co. Ltd, Hsinchu, Taiwan

A novel P+-poly gate nitride trapping memory device using a soft erase method is introduced. This soft erase can recover both the hard-to-erase and over-erase cells during the sector erase. A variation of the soft erase when applied to the programmed state eradicates shallowly trapped electrons, greatly improving endurance and retention.

2D.4 THE KINETICS OF DEGRADATION OF DATA RETENTION OF POST-CYCLED NROM NON-VOLATILE MEMORY PRODUCTS—M. Janai, B. Eitan, A. Shappir and E. Lusky, Saifun Semiconductors, Netanya, Israel

The kinetics of degradation of post-cycled NROM products is compared to transport kinetics of amorphous silicon and silicon dioxide. The results support the model of lateral hole transport in the nitride layer, and disagree with vertical transport through the oxide as the root cause of retention degradation in NROM products.

2D.5 COMPARATIVE RELIABILITY INVESTIGATION OF DIFFERENT NITRIDE BASED LOCAL CHARGE TRAPPING MEMORY DEVICES—L. Breuil, L. Haspeslagh, P. Blomme, M. Lorenzini, D. Wellekens, J. De Vos, and J. Van Houdt, IMEC, Leuven, Belgium

This paper compares the endurance and retention characteristics of two charge trapping devices having different electron injection points and same hole injection points. We found that hole trapping in the bottom oxide can explain the different endurance behavior of both devices, and the degradation of their retention after cycling.

2D.6 MECHANISM OF DRAIN DISTURB IN SONOS FLASH EEPROMs—P.B. Kumar, R. Sharma, P.R. Nair, Deleep R. Nair, S. Kamohara*, S. Mahapatra, and J. Vasi, Indian Institute of Tech., Bombay, India * Renesas Tech. Corp., Tokyo, Japan

Program drain disturb in SONOS cells is studied and the mechanisms involved are established using its dependence on cell doping, channel length and applied bias. Injection of hot holes, generated from BTBT and channel leakage, into the ONO stack from substrate is identified as the main cause for charge loss in programmed state during disturb.

Tuesday, April 19, 4:55 p.m., Room C, Parallel Session

2E INTERCONNECTS II

Co-Chairs: Ennis T. Ogawa, Texas Instruments and
Glenn B. Alers, Novellus Systems

2E.1 SCALING EFFECT ON ELECTROMIGRATION RELIABILITY FOR Cu/LOW-k INTERCONNECTS—J.W. Pyun, X. Lu, S. Yoon, N. Henis*, K. Neuman, and P.S. Ho, UT Austin, Austin, TX * SEMATECH, Austin, TX

Scaling effects on EM from line width and barrier thickness were investigated for Cu/porous low k interconnects. Process-related issues were observed leading to decreasing early failure lifetime and reliability degradation for the 0.125 µm interconnects. The (jL)c product was found to decrease with decreasing barrier thickness due to decreasing confinement.

2E.2 THE DIELECTRIC MATERIAL DEPENDENCE OF STRESS AND STRESS RELAXATION ON THE MECHANISM OF STRESS-VOIDING OF Cu INTERCONNECTS—J.-M. Paik and Y.-C. Joo, Seoul National University, Seoul, Korea

The effect of stress and its gradient on stress-voiding was studied by stress analysis using x-ray diffraction and finite element method. The reason why the Cu/low-k is more vulnerable to stress-voiding despite a lower level of stress was explained by the concept of stress gradient.

2E.3 STRESS MIGRATION RELIABILITY OF WIDE Cu INTERCONNECTS WITH GOUGING VIAS—Y.K. Lim,
R. Arijit*, K. L. Pey, C.M. Tan, C.S. Seet, T.J. Lee, and D. Vigar, Chartered Semiconductor, Singapore * Nanyang Tech. Univ., Singapore

The presence of inherent weak points, coupled with high tensile stress caused stress-induced voiding at the Si₃N₄ cap/ via interface around the perimeter of the gouging via. The steep stress gradient formed around the void vicinity after its nucleation was postulated to be the driving force for the subsequent void growth.

Wednesday, April 20, 8:00 a.m., Room A, Parallel Session

3A SOFT ERRORS

Co-Chairs: Norbert Seifert, Intel and Ken Rodbell, IBM

3A.1 COMPARISON OF PRODUCT FAILURE RATE TO COMPONENT SOFT ERROR RATE IN A MULTI-CORE DIGITAL SIGNAL PROCESSOR—X. Zhu, R. Baumann, C. Pilch, J. Zhou, J. Jones, C. Cirba, and P. Patel, Texas Instruments, Dallas, TX

In this paper the authors compare the accelerated product SER of a 0.13 µm multi-core, voice-over packet DSP system with the sum of the individual component failure rates in an accelerated alpha-particle and neutron environment. In the product SER both memory SER as well as logic SER was taken into account. The results verify that properly done component tests can be used to extrapolate real product SER.

3A.2 RADIATION-INDUCED CLOCK JITTER AND RACE—N. Seifert, B. Gill, P. Shipley, M.D. Pant, V. Ambrose, Intel, Hillsboro, OR

In this study the simulated chip-level reliability risk due to radiation-induced clock jitter has been investigated for flip flop and pulse latch based designs. The results strongly indicate that radiation-induced clock jitter cannot be neglected anymore for high-performance microprocessors. Mitigation techniques are discussed to address this issue.

3A.3 A CMOS DESIGN STYLE FOR LOGIC CIRCUIT HARDENING—M. Zhang and N.R. Shanbhag, Univ. of Illinois at Urbana-Champaign, Urbana, IL

A novel CMOS design style is presented that effectively reduced the impact of single event transients (SET) in logic circuits by particle strikes. The described technique mitigates single event transient (SET) generation and propagation in logic circuits by: (1) actively biasing isolated wells and (2) heavily attenuating the propagation of SETs generated at other transistor drains by voltage division. It is particularly applicable to mitigating radiation-induced clock jitter.

3A.4 A NOVEL METHOD FOR ACCURATELY ESTIMATING ALPHA-INDUCED SOFT ERROR RATES—R. Takasu, Y. Tosaka*, H. Fukuda, and Y. Kataoka, Fujitsu Labs, Atsugi, Japan
*Fujitsu Labs, Tokyo, Japan

The accuracy of alpha-particle induced SER assessments depends on the detection limit of the alpha metrology. Gas flow proportional counter based systems exhibit detection limits of the order of 1x10^-3 aph cm^-2. A novel dosimetry called vacuum a-tracking (VAT) is introduced that shows to be up to 30 times more sensitive than traditional methodologies.

Wednesday, April 20, 10:05 a.m., Room A, Parallel Session

3B MEMORY II

Co-Chairs: Guoqiao Tao, Philips Semiconductors and
Hanmant Belgal, Intel

3B.1 (INVITED) HIGH-k MATERIALS FOR NONVOLATILE MEMORY APPLICATIONS—J. Van Houdt, IMEC, Leuven, Belgium

This paper will review the main reliability problems for conventional tunnel and interpoly dielectric scaling in Flash memories and will propose solutions based on high-k materials. The concept of engineered barriers will be reviewed as well as the main reliability issues associated with the introduction of these materials in memory devices.

3B.2 RELIABILITY ASSESSMENT OF DISCRETE-TRAP MEMORIES FOR NOR APPLICATIONS—C.M. Compagnoni, D. Ielmini, A.S. Spinelli, A.L. Lacaita, Politecnico di Milano, Milano, Italy, and R. Sotgiu, STMicroelectronics, Agrate Brianza, Italy

This work provides a comparative analysis of the reliability of nanocrystal and nitride cells for NOR applications. Lateral charge redistribution after bake can be an issue for these technologies. Drain disturb characteristics are shown comparable to state-of-the art Flash cells, whereas large improvements are shown for the drain turn-on immunity.

3B.3 BAKE ENHANCED ERRATIC BEHAVIOR IN GATE STRESS CHARACTERISTICS IN FLASH MEMORIES—G. Tao, A. Scarpa, L. van Marwijk, and D. Dormans, Philips Semiconductors, Nijmegen, Netherlands

A new possible Flash product failure mode is reported here: gate disturbance after bake step. It is found that the worst-case situation exists when the cells are baked at erased state. A gate stress test after the cells are baked at erased state is suggested for a screen.

3B.4 IMPACT OF MECHANICAL STRESS ON INTERFACE TRAP GENERATION IN FLASH EEPROMs—A. Toda, S. Fujieda, K. Kanamori, J. Suzuki, K. Kuroyanagi, N. Kodama, Y. Den, and T. Nishizaka, NEC, Kanagawa, Japan

The mechanical stress in a Flash memory cell degrades the data retention through the generation and recovery of the interface traps. We measured mechanical stress and interface trap density by using convergent-beam electron diffraction and charge pumping method. Hydrogen atoms, another possible factor, had less influence than the mechanical stress.

3B.5 THE EFFECT OF MECHANICAL STRESS FROM STOPPING NITRIDE TO THE RELIABILITY OF TUNNEL OXIDE AND DATA RETENTION CHARACTERISTICS OF NAND FLASH MEMORY—J. Om, C. Eunseok, and K. Sejun, Hynix Semiconductor, Icheon, Korea

With experiment and TCAD simulation, we demonstrated that mechanical stress from the stopping nitride is a key factor which degrades the reliability of tunnel oxide and data retention characteristics of NAND FLASH memory.

Wednesday, April 20, 8:00 a.m., Room B, Parallel Session

3C TRANSISTORS I

Co-Chairs: Anand Krishnan, Texas Instruments and
Muhammed Ashraful Alam, Purdue

3C.1 LOW FREQUENCY NOISE DEGRADATION IN ULTRA-THIN OXIDE (15Å) ANALOG n-MOSFETs RESULTING FROM VALENCE-BAND TUNNELING—J.W. Wu, H.C. Ma, C.C. Cheng, G.W. Huang⁽¹⁾, C.S. Chang⁽²⁾, and T. Wang, National Chiao-Tung Univ., Hsin-Chu, Taiwan (1) National Nano Device Labs, Hsin-Chu, Taiwan; (2) TSMC, Hsin-Chu, Taiwan,

Degradation of low frequency flicker noise in analog n-MOSFETs with 15Å gate oxide is observed. A new noise mechanism resulting from valence band electron tunneling is identified. The excess low-frequency noise is attributed to electron and hole recombination at interface traps, verified through random telegraph signal measurements.

3C.2 CHARACTERIZATION AND MODELING OF LOW FREQUENCY NOISE DEGRADATION DUE TO NMOS HOT ELECTRON STRESS—S. Dey, UT Austin, Austin, TX and M. Agostinelli, Intel, Hillsboro, OR

Hot electron stress induced low frequency (1/f) noise degradation in NMOS devices has been characterized and modeled. It has been demonstrated for the first time that that electrical stress regime affects noise degradation and that hot electron induced stress does not affect 1/f noise in ultra-thin gate oxide devices.

3C.3 ANOMALOUS nMOSFET HOT CARRIER DEGRADATION DUE TO TRAPPED POSITIVE CHARGE IN A DGO CMOS PROCESS—D. Brisbin, Y. Mirgorodski, and P. Chaparala, National Semiconductor, Santa Clara, CA

This paper presents a novel nmosfet hot carrier degradation behavior model based on hot carrier injected positive trapped charge that is spatially separated from the normal hot carrier trapped electron charge. This positive trapped charge creates a secondary impact ionization site resulting in anomalous and accelerated idsat hot carrier degradation.

3C.4 HOT CARRIER DEGRADATION ON n-CHANNEL HfSiON MOSFETs: EFFECTS ON DEVICE PERFORMANCE AND LIFETIME—S. Cimino, , L. Pantisano⁽¹⁾, R. Degraeve⁽¹⁾, D.H. Kwak⁽²⁾, F. Crupi⁽³⁾, G. Groeseneken^(1,4), and A. Paccagnella, Università degli Studi di Padova, Padova, Italy (1) IMEC, Leuven, Belgium; (2) Samsung Electronics, affiliated at IMEC, Belgium; (3) University of Calabria, Italy; (4) Katholieke Univ. Leuven, Leuven, Belgium

Hot carrier reliability of n-channel SiO₂/HfSiON MOSFETs with poly-Si gate was studied. Interface state and bulk defect generation were observed. Under maximum substrate current and maximum electron injection conditions, HfSiON MOSFETs show longer lifetime than SiON devices with similar EOT. Hot carrier degradation strongly reduces gate stack lifetime.

Wednesday, April 20, 10:05 a.m., Room B, Parallel Session

3D FAILURE ANALYSIS I

Co-Chairs: David P. Vallett, IBM and
William K. Lo, Credence Systems

3D.1 DYNAMIC THERMAL LASER SIGNAL INJECTION MICROSCOPY (T-LSIM) ON AC PROPAGATION FAILURES—M. LaPierre, Fairchild Semiconductor, S. Portland, ME, and R.A. Falk, Optometrix, Renton, WA

Dynamic T-LSIM (Thermal laser signal injection microscopy) can detect elevated resistance from a single via. Design simulations and FIB sectioning have confirmed the T-LSIM findings. The technique can be applied to digital or analog devices. Dynamic T-LSIM allows for quick fault isolation that conventional FA techniques are unable to match.

3D.2 ADVANCED FAILURE ANALYSIS, FAILURE MODES AND RELIABILITY STUDY ON CIRCUIT-UNDER-PAD (CUP) STRUCTURES WITH COPPER TECHNOLOGIES—H. Wu, V. Archer^(1,2), S.M. Merchant⁽¹⁾, J. Cargo⁽¹⁾, D. Chesire⁽¹⁾, J. Antol⁽¹⁾, R. Mengel⁽¹⁾, J. Osenbach⁽¹⁾, S. Horvat⁽¹⁾, C. Peridier⁽¹⁾, and M. White⁽²⁾ (1) Agere Systems, Allentown, PA (2) Lehigh University, Bethlehem, PA

New failure modes and FA challenges for circuit-under-pad (CUP) structures are introduced, including processing and packaging issues on copper / low-k technology. Backside deprocessing and cross-sectioning methods including RIE, polishing, wet etch, CMP, FIB, SEM, and TEM will be presented, as will case studies.

3D.3 INVESTIGATION ON THE BEHAVIOUR OF HIGH THERMAL WAVE AMPLITUDE REGION IN nMOSFET UNDER DIFFERENT OPERATION MODES BY SCANNING THERMAL MICROSCOPY—E. Hendarto⁽¹⁾, A. Altes⁽²⁾, R. Heiderhoff⁽²⁾, J.C.H. Phang⁽¹⁾, and L.J. Balk⁽²⁾
(1) National Univ. of Singapore, Singapore; (2) Bergische Univ., Wuppertal, Germany

The shift of high thermal wave amplitude region within the gate of an nMOSFET with width-to-length ratio (W/L) of 2.0µm/3.0µm is investigated under different operation modes using Scanning Thermal Microscopy (SThM). The thermal images exhibit 50 nm resolution, and this thermal analysis by SThM correlate to the electronic behaviour of nMOSFET.

3D.4 FACTORS THAT INFLUENCE IONIC MIGRATION ON PRINTED WIRING BOARDS—M. Reid, J. Punch, B. Rodgers, M. J. Pomeroy, Univ. of Limerick, Limerick, Ireland, T. Galkin, T. Stenberg, O. Rusanen, E. Elonen, M. Vilèn, and K. Väkeväinen, Nokia Corp., Finland

In order to assess the effects of moisture condensation on ionic migration on printed wiring boards (PWBs) this work compares two extreme tests for ionic migration on PWBs. The two tests are water droplet (WD) and cyclic temperature relative humidity conditions under a bias of 5V DC.

3D.5 DELAY VARIATION MAPPING INDUCED BY DYNAMIC LASER STIMULATION—K. Sanchez⁽¹⁾, R. Deplats⁽¹⁾, F. Beaudoin⁽¹⁾, P. Vedagarbha⁽²⁾, and D. Lewis, Bordeaux Univ., Talence, France (1) CNES_THALES Laboratory, Toulouse, France, (2) CREDENCE, Toulouse, France,

We present a novel technique based on Dynamic Laser Stimulation (DLS) to characterize CMOS structures by delay propagation mapping. Delays can be generated by injecting photocurrent or, to a lesser extent, heat. The proposed methodology extends the capabilities of DLS techniques such as SDL and LADA to characterize defective ICs.

Wednesday, April 20, 8:00 a.m., Room C, Parallel Session

3E MEMS

Co-Chairs: Ingrid De Wolf, IMEC and
Jeremy A. Walraven, Sandia National Labs

3E.1 (INVITED) RESULTS OF INDUSTRY STUDY ON ISSUE OF MEMS RELIABILITY AND ACCELERATED LIFETIME TESTING—T. Breunig^(1,2), M. Mignardi^(1,3), K. Lightman⁽¹⁾, C. Cabuz^(1,4), C. Fung⁽¹⁾ (1) MEMS Industry Group, Pittsburg, PA; (2) Nova Marketing Communications, San Francisco, CA; (3) Texas Instruments, Dallas, TX; (4) Honeywell International, Plymouth, MN

The MEMS Industry Group (MIG) is a global nonprofit trade association representing the MEMS and Microstructure Industry. MIG's goal is to address issues that are barriers to the greater commercial success of MEMS devices. The issues of MEMS Reliability and Accelerated Lifetime Test (ALT) are both topics that, when fully understood, can lead to faster and cheaper production and integration of MEMS devices, leading to greater commercialization. MIG conducted industry-wide surveys on MEMS Reliability and ALT and supplemented these surveys with information garnered from 16 working groups comprised of over 200 MEMS professionals that met over the course of the last two years. With this paper, we discuss our survey results and the results of our working groups, as well as outline some industry suggestions for collectively addressing the issues of MEMS Reliability and ALT.

3E.2 ACCELERATING AGING FAILURES IN MEMS DEVICES—D.M. Tanner, M.T. Dugger, J.A. Walraven, T.B. Parson, S.A. Candelaria, J.A. Ohlhausen, and E.M. Huffman, Sandia National Labs, Albuquerque, NM

This work investigates the acceleration factors of temperature and humidity for aging electrostatic-actuated MEMS devices with contacting surfaces. A clear dependence on humidity is observed at much lower levels than typical military-standard packaging

3E.3 DYNAMIC ANALYSIS AND CHARACTERIZATION OF MEMS ACCELEROMETERS BY COMPUTATIONAL AND OPTO-ELECTROMECHANICAL METHODOLOGIES—C. Furlong, R. Kok, and C.F. Ferguson, WPI-ME/CHSLT Laser Lab, Worcester, MA

Computational and opto-electromechanical methodologies for the characterization of the dynamic response of MEMS inertial sensors are presented. Three dimension (3D) finite element methods to predict the dynamic characteristics of specific MEMS accelerometers are developed. Experimental verification and computational model updating are performed by novel optoelectronic holographic microscopy (OEHM).

3E.4 PROCESS-INDUCED TRAPPING OF CHARGE IN PECVD DIELECTRICS FOR RF MEMS CAPACITIVE SWITCHES—J.R. Webster, C.W. Dyck, C.D. Nordquist, J.A. Felix, M.R. Shaneyfelt, and J.R. Schwank, Sandia National Labs, Albuquerque, NM

Charge-induced failure is the primary reliability issue facing RF MEMS capacitive switches. Mitigation of charge in the deposited dielectrics of these devices is crucial to improved performance and lifetime. The presence of large amounts of incorporated charge in PECVD dielectric films for MEMS is reported and correlated to film chemistry. Methods for further control of charge are discussed.

3E.5 THE INFLUENCE OF THE PACKAGE ENVIRONMENT ON THE FUNCTIONING AND RELIABILITY OF CAPACITIVE RF-MEMS SWITCHES—W.M. van Spengen, R. Puers*, I. De Wolf, IMEC, Leuven, Belgium *K.U. Leuven, Heverlee, Belgium

The paper discusses the influence of environmental pressure and gasses (air versus N₂) inside a MEMS-package on the switching speed, functioning and reliability of capacitive RF MEMS switches. It is shown that both pressure and gas clearly affect the switch.

3E.6 STRUCTURAL AND THERMAL INVESTIGATION FOR FBAR RELIABILITY IN WIRELESS APPLICATIONS—R.Y. Fillit⁽¹⁾, B. Ivira⁽²⁾, J. Boussey⁽²⁾, R. Fortunier⁽¹⁾, and G. Bouche⁽³⁾ (1) Ecole des Mines de Saint Etienne, Saint Etienne, France; (2) Inst. of Microelectronics, Electromagnetisms and Photonics, ENSERG, Grenoble, France; (3) STMicroelectronics, Crolles, France

Failure mechanisms in Film Bulk Acoustic Resonators (F-BAR) developed for wireless applications are assessed using two experimental setups: one based on X-ray (including simultaneous diffraction, radiography and chemical analyses), the other one presenting a brand-new, high resolution infrared in-situ thermal mapping camera.

Wednesday, April 20, 10:55 a.m., Room C, Parallel Session

3F PRODUCT & CIRCUIT RELIABILITY I

Co-Chairs: Bill Abadeer, IBM and
Andreas Preussger, Infineon Technologies AG

3F.1 MELT-SEGREGATE-QUENCH PROGRAMMING OF ELECTRICAL FUSE—T. Sasaki, N. Otsuka, K. Hisano and S. Fujii, Toshiba Corp., Kawasaki, Japan

We propose a novel electrical fuse (e-fuse) programming procedures with Melt-Segregate-Quench mechanism by applying a short and large current pulse. This mechanism enables a dramatic shortening of programming time. Experimental results and thermal conduction analysis are introduced for 90 nm technology.

3F.2 HOT CARRIER GENERATION AND RELIABILITY OF BODY-TIED FIN TYPE SRAM CELL TRANSISTORS (WFIN=20~70 nm)—Y.J. Ahn, H.J. Cho, H.S. Kang, C.-H. Lee, C. Lee, J. Yoon, T.Y. Kim, E.S. Cho, S.-K. Sung, D. Park, K. Kim, and B. Ryu, Samsung Electronics Co., Yongin-City, Korea

In this paper, we fabricated a body-tied FinFET SRAM device with the smallest cell size of 0.46 µm². For the first time, we revealed the mechanism of improved hot carrier immunity of sub 50 nm fin type MOSFET.

3F.3 IMPACT OF PROTON IRRADIATION ON THE RF PERFORMANCE OF 0.12 µm CMOS TECHNOLOGY—S. Venkataraman, B.M. Haugerud, E. Zhao, B. Banerjee, A. Sutton, P.W. Marshall⁽¹⁾, C.-H. Lee, J.D. Cressler, J. Laskar, J. Papapolymerou, and A.J. Joseph⁽²⁾, Georgia Inst. of Technology, Atlanta, GA (1) Consultant to NASAGSFC; (2) IBM, Essex Jct., VT

The effects of 63 MeV proton irradiation on the DC and RF performance of a 0.12 µm CMOS technology is presented for the first time. Measurements of the DC, 1/f-noise, S-parameters, and broadband noise characteristics were performed at room temperature before radiation and after equivalent total dose of 1 Mrad(Si).

Wednesday, April 20, 2:50 p.m., Room A, Parallel Session

4A DIELECTRICS

Co-Chairs: Masaaki Niwa, Panasonic and Barry P. Linder, IBM

4A.1 MEASUREMENT AND STATISTICAL ANALYSIS OF SINGLE TRAP CURRENT-VOLTAGE CHARACTERISTICS IN ULTRATHIN SiON—R. Degraeve, B. Govoreanu, B. Kaczer, J. Van Houdt, and G. Groeseneken⁽¹⁾, IMEC, Leuven, Belgium (1)  also with Catholic University Leuven, Belgium

We isolated the current-voltage characteristics of single-trap leakage paths in ultrathin SiON and we evaluated their statistical properties. A uniform distribution of bulk oxide traps with fixed energy level can describe the measurements satisfactorily.

4A.2 OXIDE VOLTAGE/OXIDE FIELD (V_OX/E_OX) -DRIVEN BREAKDOWN OF ULTRA-THIN SiON GATE DIELECTRIC IN P+GATE-pMOSFET UNDER LOW STRESS VOLTAGE OF INVERSION MODE—S. Tsujikawa, K. Shiga, H. Umeda, Y. Akamatsu, J. Yugami, Y. Ohno, and M. Yoneda, Renesas, Hyogo, Japan

Systematic study with varying gate doping concentrations has revealed that, in the case of p+gate-pMOSFET in inversion mode, gate dielectric breakdown under low stress voltage is driven by oxide voltage (V_ox) or oxide field (E_ox), while the breakdown under higher stress voltage is driven by gate voltage (V_g).

4A.3 UNIVERSALITY OF POWER-LOW VOLTAGE DEPENDENCE FOR TDDB LIFETIME IN THIN GATE OXIDE PMOSFETs—K. Ohgata, M. Ogasawara, K. Shiga, S. Tsujikawa, E. Murakami, H. Kato, H. Umeda, and K. Kubota, Renesas, Ibaraki, Japan

We investigated the voltage dependence of T_bd in n-FETs and p-FETs. The exponent of the power-law is constant except for p-FETs subjected to inversion mode stress. In this case the exponent changes from 45 to 33 at |V_g|=3.8V independent of oxide thickness. This phenomenon is explained by the cathode side hydrogen release model.

4A.4 MVHR (MULTI-VIBRATIONAL HYDROGEN RELEASE): CONSISTENCY WITH BIAS TEMPERATURE INSTABILITY AND DIELECTRICS BREAKDOWN—G. Ribes^(1,2), S. Bruyère⁽¹⁾, M. Denais^(1,3), D. Roy⁽¹⁾, and G. Ghibaudo⁽²⁾ (1) STMicroelectronics, Crolles, France; (2) IMEP/ENSERG, Grenoble, France; (3) L2MP/ISEM, Toulon, France,

In this work we report on interface states generation time dependence and we link it with the Multi-Vibrational Hydrogen Release (MVHR) mechanism. After that we show with experimental evidence that the oxide breakdown and the MVHR are strongly linked.

4A.5 A DISORDER-CONTROLLED-KINETICS MODEL FOR NEGATIVE BIAS TEMPERATURE INSTABILITY AND ITS EXPERIMENTAL VERIFICATION—B. Kaczer, V. Arkhipov, R. Degraeve, N. Collaert, G. Groeseneken*, and M. Goodwin**, IMEC, Leuven, Belgium *also Catholic Univ. Leuven, Belgium; **Texas Instruments affiliate at IMEC

We propose a model for NBTI based on disorder-controlled diffusion and drift in amorphous dielectrics. Our experimental study on FinFETs confirms all major predictions of the model: temperature dependence of the NBTI exponent, non-Arrhenius behavior of NBTI, log(t) and the electric field dependence of recovery. Experimental challenges with determining NBTI parameters are also highlighted.

4A.6 CHANGE OF ACCELERATION BEHAVIOR OF TIME-DEPENDENT DIELECTRIC BREAKDOWN BY THE BEOL PROCESS: INDICATIONS FOR HYDROGEN INDUCED TRANSITION IN DOMINANT DEGRADATION MECHANISM—T. Pompl, K.-H. Allers, R. Schwab, K. Hofmann, and M. Roehner, Infineon Technologies, Munich, Germany

One single modification in the back end of line (BEOL) process can change the acceleration behavior of time-dependent dielectric breakdown (TDDB). It is demonstrated that two competing degradation mechanisms exist in parallel, which follow time dependences according to the E-model and the 1/E-model. NBTI tests correlate well with TDDB results and are in agreement with a new continuous hydrogen reaction model.

Wednesday, April 20, 2:00 p.m., Room B, Parallel Session

4B PROCESS INTEGRATION RELIABILITY.

Co-Chairs: Vijay Reddy, Texas Instruments and
Carl Kyono, Freescale

4B.1 IMPACT OF PLASMA INDUCED DAMAGE ON pMOSFETs WITH TiN/Hf-SILICATE STACK—S.C. Song, S.H. Bae, B.H. Lee*, K. Matthews, J.H. Sim, B. Sassman, G. Bersuker and P. Zeitzoff, SEMATECH, Austin, TX, *IBM assignee

A comprehensive examination of plasma damage on TiN/Hf silicate gate stack pMOSFETs is presented. Plasma damage in terms of polarity dependency, dielectric thickness, and antenna configuration on TiN/Hf silicate pMOSFETs is characterized.

Wednesday, April 20, 2:25 p.m., Room B, Parallel Session

4C WIDE BAND GAP / COMP. DEVICES

Co-Chairs: Brian J. Skromme, Arizona State University and
Robert S. Okojie, NASA-Glenn Research Center

4C.1 CURRENT-VOLTAGE (I-V) CHARACTERISTICS AND RELIABILITY CONSIDERATIONS OF STRAINED SILICON ON RELAXED SILICON-GERMANIUM (SiGe) SUBSTRATE AT HIGH TEMPERATURE—J.R. Shih and K. Wu, TSMC, Hsin-Chu, Taiwan

The process induced reliability degradation of both strained Si nMOSFETs and pMOSFETs are fully characterized. It is shown that SiGe pMOSFETs exhibit apparent mobility and reliability degradation at high operating temperature.

4C.2 RELIABILITY ISSUES ASSOCIATED WITH OPERATING VOLTAGE CONSTRAINTS IN ADVANCED SiGe HBTs—C.M. Grens, J.D. Cressler, J.M. Andrews, Q. Liang, Georgia Inst. of Technology, Atlanta , GA, and A.J. Joseph, IBM Microelectronics, Essex Junction, VT

We present a comprehensive picture of voltage constraints as they relate to reliability issues in SiGe HBTs, addressing breakdown with respect to generation, geometry, and operational current density. New definitions for breakdown voltage are presented. Practical reliability implications of breakdown are explored using careful measurements and quasi-3D compact models.

4C.3 HOT ELECTRON STRESS DEGRADATION IN UNPASSIVATED GaN/AlGaN/GaN HEMTs ON SiC—G. Meneghesso, R. Pierobon, F. Rampazzo, G. Tamiazzo, E. Zanoni, University of Padova, Padova, Italy, J. Bernat, P. Kordos, Inst. of Thin Films and Interfaces, Juelich, Germany, A.F. Basile, A. Chini, and G. Verzellesi, Univ. of Modena and Reggio Emilia, Modena, Italy

A detailed characterization of pre- and post-hot-electron-stress performance of unpassivated GaN/AlGaN/GaN HEMTs on SiC substrates is presented, allowing the main degradation modes to be identified. The possible underlying physical mechanisms are also probed by means of two-dimensional numerical device simulations.

Wednesday, April 20, 2:00 p.m., Room C, Parallel Session

4D PRODUCT & CIRCUIT RELIABILITY II

Co-Chairs: Bill Abadeer, IBM and
Andreas Preussger, Infineon Technologies AG

4D.1 IMPACT OF MOSFET GATE-OXIDE RELIABILITY ON CMOS OPERATIONAL AMPLIFIER IN A 130-nm LOW-VOLTAGE CMOS PROCESS—J.-S. Chen and M.-D. Ker, National Chiao-Tung Univ., Hsinchu, Taiwan

The effect on the gate-oxide reliability of MOSFET on operational amplifier was investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. After stressing the gate-oxide of the MOSFET, the small-signal parameters of the amplifier with two-stage structure strongly decreased while those of the amplifier with folded-cascode structure were unchanged. The tested condition includes unity-gain buffer and comparator under different input frequencies and signals. Consequently, the gate-oxide breakdown event may cause the failure in two-stage operational amplifier. However, the gate-oxide reliability can be improved by stacked structure in analog circuit. Finally, simple equivalent device model of gate-oxide reliability for a CMOS analog circuit was investigated and simulated.

4D.2 RF RELIABILITY SUBJECT TO DYNAMIC VOLTAGE STRESS IN NMOS CIRCUITS—C. Yu and J.S. Yuan, Univ. of Central Florida, Orlando, FL

NMOS transistor degradation due to dynamic stress- 900 MHz inverter-like wave forms was evaluated experimentally. A compact model is developed to evaluate the degradation in radio frequency performance. A class-AB power amplifier is used as a circuit example to demonstrate the effect of dynamic stress on RF circuit performance.

4D.3 RELIABILITY IMPROVEMENT AND BURN IN OPTIMIZATION THROUGH THE USE OF DIE LEVEL PREDICTIVE MODELING—W.C. Riordan, R. Miller, and E.R. St. Pierre, Intel, Chandler, AZ

A die-level, predictive defect model is presented which identifies subpopulations of die with varying infant mortality. The model is shown to be twice as efficient in identifying unreliable material as traditional wafer or lot level methods. Applications include reduced burn in requirements while continuing to meet infant mortality goals.

4D.4 LIFETIME STUDY FOR A POLY FUSE IN A 0.35µm POLYCIDE CMOS PROCESS—J. Fellner, P. Boesmueller, and H. Reiter, austriamicrosystems AG, Unterpremstaetten, Austria

The investigations documented in this paper give comprehensive analyses of programming condition for Poly Fuse elements, which are based on a 2-layer approach. Optimal programming conditions are defined as well as drifts of the programming conditions and their impact on the Poly fuse reliability are monitored. TEM/SEM analysis gives corresponding physical explanations for the electrical effects seen for different programming conditions.

Wednesday, April 20, 4:05 p.m., Room C, Parallel Session

4E LATE PAPERS

Co-Chairs: TBD, and TBD,

4E.1 CHARACTERIZATION OF THERMOELECTRIC DEVICES IN ICs AS STIMULATED BY A SCANNING LASER BEAM—A. Glowacki and C. Boit, TUB Berlin University of Technology, Berlin, Germany

A parametric investigation of Seebeck Effect in passive and active devices with various resistivities is presented. With the contribution of conventional OBIRCH/TIVA in interconnects and contacts, this systematic approach based on device simulation represents the full variety of imaging phenomena, in constant current and constant voltage condition.

4E.2 NEW BALLASTING METHOD FOR METHOD FOR MOS OUTPUT DRIVERS AND POWER BUS CLAMPS—E.R. Worley, Conexant Systems, Newport Beach, CA

New layout styles for MOSFET output drivers and power bus ESD NFET clamps are shown, which provide ballasting with reduced layout area and drain capacitance than the traditional method of using a salicide, blocked drain resistor. Also, an N well ring is placed inside the P+ substrate tie ring of an NFET to increase channel to substrate resistance and improve snap-back conduction uniformity.

4E.3 TESTING TO ELIMINATE RELIABILITY DEFECTS FROM ELECTRONIC PACKAGES—I. Memis, Endicott Interconnect, Endicott, NY

Packaging is a critical part of all electronic devices and can be a source of the reliability problems experienced by systems using those devices. In many cases, the packaging defects are intermittent in nature and difficult to detect. IBM has developed a tester that has been used by IBM and Endicott Interconnect (EI) for 20 years on commercial products and has proven to be extremely effective in detecting these defects prior to component assembly. The LATEST tester, invented by IBM Manufacturing Research, has been applied to defects in printed circuits, multilayer ceramic and flex circuits. As packaging density increases, the use of this tester becomes critical because of the difficulty of producing "defect-free" product and the impact of defects on the reliability of the end-use product. This paper will cover the theory of the LATEST tester and the effectiveness of the test for printed circuits and flex products. It will also cover application methods and deployment. Comparisons to standard test systems will demonstrate the significant reliability improvement achieved with LATEST testing which makes its use imperative for mission critical applications.

Thursday, April 21, 8:00 a.m., Room A

5A BEOL DIELECTRICS

Co-Chairs: Amit P. Marathe, AMD and Stefan Hau-riege, LLNL

5A.1 A DETAILED, CD VARIATIONS-CORRECTED, INTERCONNECT DIELECTRICS BREAKDOWN CHARACTERIZATION—G.S. Haase, E.T. Ogawa, and J.W. McPherson, TI, Dallas, TX

A method is presented for electrical determination of the worst-case spacing between minimum-spaced metal leads, which is essential for accurate reliability analysis of sub-90nm interconnect dielectrics. A "Berman-like" dual ramp-rate breakdown at different temperatures, with SEM validation, yielded a temperature-independent field-acceleration parameter y=4.1±0.3 cm/MV and zero-field activation-energy of 0.14±0.02 eV. Extensive constant-voltage TDDB data confirmed these findings.

5A.2 POROSITY CONTENT DEPENDENCE OF TDDB LIFETIME AND FLAT BAND VOLTAGE SHIFT BY Cu DIFFUSION IN POROUS SPIN-ON LOW-k—S.-S. Hwang, H.-C. Lee, H.-W. Ro, D.-Y. Yoon, and Y.-C. Joo, Seoul National Univ., Seoul, Korea

TDDB and C-V measurements under BTS were accomplished on low-k dielectrics which consisted of same matrix (PMSSQ) but different porogen contents. It was observed that TTF decreased, Weibull slope(ß) and VFB increased abruptly between 20% and 30% porosity. Mechanisms of Cu diffusion in low-k with various porosity contents are discussed.

5A.3 PSEUDO-BREAKDOWN PHENOMENON AND BARRIER INTEGRITY IN Cu/POROUS ULTRA LOW-k DAMASCENE INTERCONNECTS—Z. Chen, K. Prasad, Nanyang Tech. Univ., Singapore, N. Jiang, L.J. Tang, N. Babu, S. Balakumar, Institute of Microelectronics, Singapore, and C.Y. Li, Chartered Semiconductor, Singapore

Pseudo-breakdown phenomenon and time-dependent dielectric breakdown were studied to investigate the sidewall barrier integrity for Cu/porous ultra low-k interconnects. The Pseudo-breakdown behavior could be eliminated and better interconnect reliability could be achieved by using a a-SiC:H/Ta bialyer barrier structure.

5A.4 NEW APPROACH OF 90 nm LOW-k INTERCONNECT EVALUATION USING A VOLTAGE RAMP DIELECTRIC BREAKDOWN (VRDB) TEST—O. Aubel, M. Kiene, AMD, Dresden, Germany, and W. Yao, AMD, Sunnyvale, CA

We have developed a new model to extrapolate breakdown voltage distributions to Lifetime requirements. The calculation shows extreme voltage acceleration in combination with a very low Temperature dependence. The area-scaling correlation and the very high sample size of actual 90 nm Integrated circuits allows a good calculation of a minimum mean breakdown voltage necessary to meet the Lifetime requirements.

5A.5 IMPACT OF BURIED CAPPING LAYER ON TDDB PHYSICS OF ADVANCED INTERCONNECTS—K.Y. Yiang, W.J. Yoo, National Univ. of Singapore, Singapore, Ahila Krishnamoorthy, and L.J. Tang, Institute of Microelectronics, Singapore

In Cu/SiOC interconnects, a thin (100-Å) buried capping layer (BCL) extends the extrapolated lifetime (at 105ºC, 0.5MV/cm) beyond 10 years. Thicker BCL initiates Ta barrier rupture due to thermomechanical stress and degrades lifetime performance. For the first time, the distinctive failure mechanisms of structures with and without BCL are identified.

5A.6 ROLE OF DIELECTRIC AND BARRIER INTEGRITY IN RELIABILITY OF SUB-100 nm COPPER LOW-k INTERCONNECTS—Z. Tokei⁽¹⁾, J. Van Aelst⁽¹⁾, C. Waldfried⁽²⁾, O. Escorcia⁽²⁾, P. Roussel⁽¹⁾, G.P. Beyer⁽¹⁾, and K. Maex^(1,3) (1) IMEC, Leuven, Belgium; (2) Axcelis Technologies, Rockville, MD; (3) Katholieke Univ., Leuven, Belgium.

The voltage acceleration of ILD breakdown of Cu/Low-K interconnects is strongly linked to the barrier integrity, while the overall dielectric quality determines the failure distribution characteristics and ultimately the reliability margin. Integration of low-k materials with minimal damage is necessary for maintaining reliability margin for the 65nm node and beyond.

5A.7 INVESTIGATION OF CVD SiCOH LOW-k TIME-DEPENDENT DIELECTRIC BREAKDOWN AT 65 nm NODE TECHNOLOGY—F. Chen⁽¹⁾, K. Chanda, J. Gill⁽¹⁾, M. Angyal, J. Demarest, D. Hunt⁽¹⁾, M. Shinosky⁽¹⁾, L. Economikos, M. Hoinkis, S. Lane, D. McHerron, M. Inohara, J. Therrien⁽¹⁾, S. Boettcher, D. Dunn, M. Fukasawa, B.C. Zhang, K. Ida, T. Ema, G. Lembach, K. Kumar, Y. Lin, H. Maynard, K. Urata, T. Bolom, K. Inoue, J. Smith, Y. Ishikawa, M. Naujok, P. Ong, A. Sakamoto, and J. Aitken⁽¹⁾, IBM System and Technology Group, Hopewell Junction, NY (1) IBM System and Technology Group, Essex Junction, VT

The TDDB degradation of CVD SiCOH low-K at 65 nm node technology was critically studied. SiCOH TDDB was found to be sensitive to all aspects of integration. By combining all the beneficial process steps together, a superior SiCOH TDDB performance at 65nm technology node was demonstrated. The projected TDDB lifetime of SiCOH film was far beyond the reliability target even on some extremely large test structures.

Thursday, April 21, 8:00 a.m., Room B, Parallel Session

5B ASSEMBLY & PACKAGING

Co-Chairs: Jeffrey T. Coffin, IBM Microelectronics and
Rajen C. Dias, Intel

5B.1 IDENTIFICATION OF NEW MECHANISM OF EPOXY UNDERFILL VOID FORMATION IN ELECTRONIC PACKAGES—S.L.B. Dal, Intel Technology Philippines, Cavite, Philippines and N.T. Zamora, Intel, Chandler, AZ

A new mechanism for underfill void formation is identified involving a flux thermal decomposition product and an epoxy-amine underfill material. Data gathered from thermal analyses correlated well with the physical evidence from simulation experiments. The investigation increased understanding of this common packaging issue and can be used in material evaluations.

5B.2 INFLUENCE OF PROCESS PARAMETERS AND BUMP GEOMETRY ON THE RESIDUAL STRESS DISTRIBUTION IN A CHIP-ON-FOIL BONDING PROCESS—P. Suter, R. Bauknecht, T. Graf, Inst. of Electronics, HTA Luzern, Horw, Switzerland, H. Duran and I. Venter, Philips Semiconductors, Zurich, Switzerland,

A chip-on-foil inner-lead bonding process for display driver circuits was analyzed by means of finite-element simulation and experimental validation. Using the developed model, bonding process parameters and bump arrangement could be optimized with respect to residual stress and a significantly higher reliability for the package was achieved.

5B.3 A STUDY OF ELECTROMIGRATION FAILURE IN Pb-FREE SOLDER JOINTS—M. Ding, G. Wang, B. Chao and P.S. Ho, UT Austin, Austin, TX, P. Su, T. Uehling, and D. Wontor, Freescale, Austin, TX

Pb-free solder EM tests of joints with two Cu and Ni stacks was performed. The lifetime data was collected at various temperatures to characterize the resistance of two solder types to EM. A difference in EM failure mechanism is observed between the solder joints. The solder joints with the Cu UBM showed a temperature dependent failure.

Thursday, April 21, 10:05 a.m., Room B, Parallel Session

5C TRANSISTORS II

Co-Chairs: Anand Krishnan, Texas Instruments and
Muhammed Ashraful Alam, Purdue

5C.1 A NEW DRAIN VOLTAGE ENHANCED NBTI DEGRADATION MECHANISM—N.K. Jha, P.S. Reddy and V.R. Rao, Indian Institute of Technology, Bombay, India

In this work, we studied the implications of drain bias on NBTI degradation. We show using detailed experimental results that non-uniform generation of interface states along the channel length and subsequent lateral diffusion of generated hydrogen species contribute to the NBTI degradation process.

5C.2 RANDOM CHARGE EFFECTS FOR PMOS NBTI IN ULTRA SMALL GATE AREA DEVICES—M. Agostinelli, S. Pae, W. Yang, C. Prasad, D. Keneke, S. Ramey, E. Snyder*, S. Kashyap, and M. Jones, Intel, Hillsboro, OR   * AMI, Pocatella, ID,

The modeling of PMOS NBTI degradation of ultra small gate area devices is vital for the accurate modeling of the cache cell minimum operating voltage Vmin. Recent data and simulation has indicated that random fluctuations in PMOS NBTI device degradation are present under stress.

5C.3 THE CONTRIBUTION OF HfO₂ BULK OXIDE TRAPS TO DYNAMIC NBTI IN PMOSFETs—B. Zhu, J.S. Suehle*, E. Vogel*, and J.B. Bernstein, Univ. of MD, College Park, MD *NIST, Gaithersburg, MD

NBTI of HfO₂ and SiO₂ devices are studied and compared. The pulsed stress frequency responses of DV_th and acceleration parameters are quite different for them. Bulk traps in the HfO₂ film are used to explain these differences. Furthermore, caution must be taken when extrapolating the device lifetime of HfO₂ devices.

***11:20 a.m., Room B, begin plenary session

5C.4 NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) CHARACTERISTICS OF BULK FINFETs—S.-Y. Kim, Kyungpook National Univ., Daegu, Korea, T. Park, Seoul National Univ. Seoul, Korea, J.-S. Lee, Uiduk Univ., Gyongju, Korea, D. Park, Samsung Electronics Co., Kyungki-Do, Korea, K.-N. Kim, and J.-H. Lee, Kyungpook National Univ., Daegu, Korea

Negative Bias Temperature Instability of bulk FinFET was investigated for the first time. The bulk FinFET showed less NBTI degration with back bias. The NBTI with fin body width was similar. Less NBTI degradation was observed in the bulk FinFET with longer channel length. Crystal orientation effect was also shown.

5C.5 RELIABILITY INVESTIGATION UPON 30nm GATE LENGTH ULTRA-HIGH ASPECT RATIO FINFETs—W.-S. Liao, S.-S. Chen, W.-T. Shiau, and K. Liao, UMC, Hsinchu, Taiwan

Three dimension (3D) vertical double gate (FinFET) devices with an ultra-high aspect ratio (Si-fin height/width=H/W >7) and gate nitrided oxide (N/O) of 14Å have been successfully developed. Detailed reliability characterizations including V_bd, Q_bd, NMOS HCI DC and AC lifetimes as well as PMOS NBTI lifetimes indicate robust properties for future industrial applications.

Thursday, April 21, 8:00 a.m., Room C, Parallel Session

5D HIGH VOLTAGE DEVICES

Co-Chairs: Prasad Chaparala, National Semiconductor Corp.
and Peter Moens, AMI Semiconductor Belgium

5D.1 (Invited) Short and long term safe operating area considerations in Ldmos transistors— P.L. Hower, Texas Instruments, Manchester, NH and S. Pendharkar, Texas Instruments, Dallas, TX*

The safe operating area of lateral DMOS transistors is becoming increasingly important as this component continues to find increased utility for mixed-signal output driver applications. Both short ( < 3 ms) and long term SOA limits and the responsible physical mechanisms are described. The resulting impact on device designs is discussed

5D.2 (ESREF best paper invited) EVIDENCE FOR SOURCE SIDE INJECTION HOT CARRIER EFFECTS ON LATERAL DMOS TRANSISTORS—S. Aresu⁽²⁾, W. De Ceuninck^(1,2), G. Van den bosch⁽³⁾, G. Groeseneken^(3,4), P. Moens⁽⁵⁾, J. Manca^(1,2), D. Wojciechowski^(5), and P. Gassot⁽⁵⁾ (1) Limburgs Univ. Centre, Diepenbeek, Belgium; (2) IMEC, Diepenbeek, Belgium; (3) IMEC, Heverlee, Belgium; (4) Catholic Univ. Leuven, Leuven, Belgium; (5) AMI Semiconductor, Oudenaarde, Belgium

The hot carrier degradation behavior of lateral integrated DMOS transistors is studied in detail. It has been demonstrated that two degradation mechanisms are present: electron mobility reduction due to interface trap formation and injection and trapping of hot electrons at the source side of the channel.

5D.3 HOT CARRIER DEGRADATION OF LATERAL DMOS TRANSISTOR CAPACITANCE AND RELIABILITY ISSUES—N. Hefyene, C. Anghel, R. Gillon*, and A.M. Ionescu, Swiss Federal Institute of Tech., Lausanne, Switzerland * AMI, Semiconductor Belgium, Oudenaarde, Belgium,

A novel experimental evaluation of the hot-Carrier impact on DMOSFET AC and DC characteristics and their correlation is reported through an original analysis, able to identify and localize HC-degradation mechanisms. We demonstrate that capacitance characterization is mandatory for accurate estimation of HC effect on the dynamic characteristics of DMOS transistors.

5D.4 ELECTRON TRAPPING AND INTERFACE TRAP GENERATION IN DRAIN EXTENDED PMOS TRANSISTORS—P. Moens, F. Bauwens, M. Nelson*, and M. Tack, AMI Semiconductor Belgium, Oudenaarde, Belgium *AMI Semiconductor, Pocatello, ID

Hot carrier behaviour of a p-type lateral DeMOS is investigated for the first time using charge pumping method. In an early stage of hot carrier stress, electron injection and trapping occurs. Afterwards, Nit formation in the spacer oxide is becoming the dominant mechanism. In this way, the abnormal degradation of Ron is explained.

5D.5 HOT-CARRIER RELIABILITY IN SUBMICROMETER 40V LDMOS TRANSISTORS WITH THICK GATE OXIDE—J.F. Chen, K.-M. Wu, K.-W. Lin, Y.-K. Su, National Cheng Kung Univ., Tainan, Taiwan, and S. L. Hsu, TSMC, Hsin-Chu, Taiwan

The hot-carrier reliability in thick gate oxide LDMOS transistors is presented for the first time and two distinct behaviors are found. First, higher Vgs stressing results in a greater degradation because of the Kirk effect. Second, AC lifetime is much longer than DC lifetime because of the recovery in degradation.

5D.6 ELECTRICAL CHARACTERISTICS AND RELIABILITY OF THE EXTENDED DRAIN VOLTAGE NMOS DEVICES WITH THE MULTI-RESURF JUNCTION—V.A. Vashchenko, D. Brisbin, P. Lindorfer, P. Chaparala and P. Hopper, National Semiconductor, Santa Clara, CA

The experimental validation of the multi-RESURF and diluted junction methodology for improvement of the characteristics of the lateral extended drain NMOS devices is presented. Electrical and hot carrier degradation characteristics are discussed. Significant improvement in the device electrical characteristics is shown, while Hot Carrier Degradation found as a limiting factor.

5D.7 RELIABILITY ASSESSMENT OF DEEP TRENCH ISOLATION STRUCTURES—P. Moens, P. Coppens, J. Baele, F. Bauwens, S. Boonen, H. De Vleeschouwer, F. De Pestel and M. Tack, AMI Semiconductor Belgium, Oudenaarde, Belgium

An extensive investigation of the reliability of deep trench isolation structures upon reverse bias stress is performed. By using the charge pumping technique, it is shown that the degradation of the trench is primarily originating from Dit formation at the inner trench corners. The reliability is improved by introducing cut corners.

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Poster Session

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

AP ASSEMBLY & PACKAGING

Co-Chairs: Jeffrey T. Coffin, IBM Microelectronics and
Rajen C. Dias, Intel

AP01 A STUDY OF THE RELIABILITY OF MOSFETs IN TWO STACKED THIN CHIPS FOR 3D SYSTEM IN PACKAGE—A. Ikeda, Y. Sugimoto, T. Kuwada, S. Kajiwara, T. Fujimura, K. Iwasaki*, H. Ogi*, A. Hamaguchi*, H. Kuriyaki, R. Hattori, and Y. Kuroki, Kyushu Univ., Fukuoka, Japan *Hara-seiki Industry Co. Ltd., Minamata, Japan

For highly reliable system in package, the electrical characteristics of MOSFETs in two stacked chips were investigated. The mobility after chip stacking was decreased for nMOSFETs and increased for pMOSFETs. It could be caused by the piezoresitance effect under compressive stress in the lower chip by upper chip mounting.

AP02 FAILURE ANALYSIS OF INTERMITTENT PIN-TO-PIN SHORT CAUSED BY PHOSPHOROUS PARTICLE IN MOLDING COMPOUND OF SEMICONDUCTOR DEVICES—N. Wang, J. Wu and S. Daniel, Cypress Semiconductor, San Jose, CA

"Soft" x-rays revealed two kinds of particles in LSI package that are housed in phosphorus based molding compound. Optical and electron microscopy and EDS were applied to find the nature of the particle and FIB was used to find shorting path between pins. The shorting path formation was discussed in the article.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

BE BEOL DIELECTRICS

Co-Chairs: Amit P. Marathe, AMD and Stefan Hau-riege, LLNL

BE01 ANALYSIS OF ELECTRIC FIELD DISTRIBUTION AND ITS INFLUENCE IN ASYMMETRIC INTERCONNECT STRUCTURE—T.M.Z. Lin and W.M. Hsu, TSMC, Hsin-Chu, Taiwan

The distribution and impact of electric field which results in dielectric breakdown in asymmetry copper interconnect structure has been studied based on the finite element method. It has been demonstrated that the concentration point of electric field distribution in asymmetric via-involved structures was quite different than that in traditional line-to-line symmetric structure. Backend time-dependent dielectric breakdown test and failure-mode analysis, showed worse TDDB performance in asymmetric via-involved structure in support

BE02 ELECTRO-OPTICAL RELIABILITY CHARACTERIZATION OF ADVANCED Cu/LOW-k INTERCONNECTS—C. Guedj⁽¹⁾, J.F. Guillaumond^(1,2), F. Mondon⁽¹⁾, L. Arnaud⁽²⁾, V. Arnal⁽¹⁾, G. Reimbold⁽¹⁾, and J.Torres⁽²⁾ (1) CEA-Leti, Grenoble, France; (2) STMicroelectronics, Crolles, France

Conventional reliability characterizations of Cu/Low-lines generally use electrical measurements in dark conditions. In this paper, we found that such interconnects are sensitive to light, and this light-induced leakage currents (LILC) change dramatically during bias-temperaturestress experiments, in agreement with the evolution of SILC. Hence this electro-optical probing method is interesting for characterizing the reliability of advanced Cu-Low K interconnects.

BE03 STABILITY STUDIES AND ELECTRICAL CHARACTERIZATION OF HIGH-k (Ta₂O₅ AND Al₂O₃) MIM CAPACITORS—S. Bruyere, E. Deloffre*, C. Besset, S. Dubois, and S. Boret, STMicroelectronics, Crolles, France *also IMEP/ENSERG, Grenoble, France

For RF and analog advanced applications, high k dielectric MIM capacitors are introduced with severe specifications in term of capacitance variations with voltage, temperature. In this paper, capacitance linearity, leakage current and stability studies will be discussed for Ta₂O₅ 5fF/µm² MIM capacitor. Also, a new methodology is developed to extract Voltage linearity coefficients of high-k MIM capacitance (VCCs) through C(V) hysteresis cycles. Very good stability of VCCs is reported on Ta₂O₅ MIM capacitor in worst case stress configurations, which guarantees excellent performances in analog ICs.

BE04 FAST RELIABILITY EVALUATION OF BACKEND DIELECTRICS USING LIFETIME PREDICTION TECHNIQUES AT WAFER LEVEL—C. Hong, L. Milor, Georgia Inst. of Technology, Atlanta, GA, M.Z Lin, W.M. Hsu, and Y. Peng, TSMC, Hsin-Chu, Taiwan

In this paper, two methods of predicting device lifetime for fast reliability evaluation are demonstrated. These methods are based on correlation techniques using breakdown signature parameters. The first method uses voltage data from ramped voltage stress test as a breakdown signature parameter and the second method utilizes near-time-zero leakage current data from TDDB test.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

CD WIDE BAND GAP / COMP. DEVICES

Co-Chairs: Brian J. Skromme, Arizona State University and Robert S. Okojie, NASA-Glenn Research Center

CD01 HOT CARRIER RELIABILITY IN GaAs PHEMT MMIC POWER AMPLIFIERS—Y.C. Chou, R. Lai, R. Grundbacher, G. P. Li*, M. Yu, L. Callejo, D. Leung, Q. Kan, D. Eng, T. Block, and A. Oki, Northrop Grumman Space Technology, Redondo Beach, CA *Univ. of California at Irvine, Irvine, CA

The effects of hot carrier reliability on GaAs PHEMTs and MMIC power amplifiers (PAs) are investigated for RF-drive conditions. Using a long-term lifetest (up to 6000 hours), an empirical model for hot carrier reliability is developed to predict the long-term RF performance of GaAs PHEMT power amplifiers.

CD02 EFFECT OF NITRIDATION ON GATE OXIDE RELIABILITY IN 4H-SiC MOS DEVICES—S. Krishnaswami, M. Das, A. Agarwal, and J. Palmour, Cree Inc., Durham, NC

In silicon MOS, nitridation has been shown to improve reliability of the gate oxide due to the greater strength of the Si-N bond. This paper presents high-temperature time dependent dielectric breakdown (TDDB) results from both 4H-SiC MOS capacitors and MOSFETs with thermal oxides grown under different conditions.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

DI DIELECTRICS

Co-Chairs: Masaaki Niwa, Panasonic and Barry P. Linder, IBM

DI01 DIRECT TUNNELING STRESS-INDUCED LEAKAGE CURRENT IN NMOS DEVICES WITH ULTRATHIN GATE OXIDES—P. Samanta, T.Y. Man, A.C.K. Chan, M. Chan, The Hong Kong Univ. of Science and Tech., Hong Kong, Q. Zhang, and C. Zhu, National Univ. of Singapore, Singapore

Stress-induced leakage current (SILC) generation in metal gated capacitors with 2-3 nanometer silicon dioxide during constant current and voltage stress in direct tunneling (DT) regime is studied. The results show that SILC generation mechanism is dominated by the trapped hole assisted tunneling, which is distinctly different from that in Fowler-Nordheim SILC.

DI02 A COMPREHENSIVE SOLUTION FOR ULTRA-THIN OXIDE RELIABILITY ISSUE INCLUDING A NOVEL EXPLANATION OF POWER-LAW EXPONENT VARIATION—T.K. Kang, J. Shieh, O. Lo, J.-P. Chen, C.-L. Lin, and K.C. Su, UMC, Hsin-Chu City, Taiwan, ROC

An analysis of ultra-thin oxide reliability that includes the validation of power law model (TBD ~V-n), area scaling (TBD ~A-1/ß), and process optimization is proposed. Based on the quantitative hydrogen-based model and modified AHI model, we have proposed a novel explanation on ultra-thin oxide PMOS degradation behavior with different DPN pressure and enhance substrate bias. A proper area range for ß determination and process optimization for n improvement are identified.

DI03 A NEW MODEL FOR THE POST-BREAKDOWN CONDUCTANCE OF MOS DEVICES BASED ON THE GENERALISED DIODE EQUATION—E. Miranda, Univ. Autònoma de Barcelona, Bellaterra, Spain

A new analytic model for the post-breakdown conductance of MOS devices with sub-5 nm gate oxides is presented. The model arises from the solution of the generalised diode equation, namely a diode-type equation with series resistance. The expression for the conductance-voltage characteristic is found invoking the mathematical properties of the Lambert W function. We show that this new approach improves a previous one, the quantum point contact model, especially in the low bias range where the contact effect between electrodes seems to play a crucial role.

DI05 DIRECT OBSERVATION OF TRAP BEHAVIORS DURING DEGRADATION AND BREAKDOWN EVOLUTION IN HIGHLY STRESSED SiO₂ FILMS BY CONDUCTIVE ATOMIC FORCE—L. Zhang and Y. Mitani, Toshiba, Kawasaki, Japan

Trap behaviors pre- and post-FN-stress-induced breakdown (BD) in SiO2 films were directly observed by CAFM. The negative charges after BD were found to be located near the cathode-oxide interface. A lateral propagation of degradation both electrically and physically was also found to occur prior to BD with similar lateral distribution to that of post-BD.

DI06 EXPONENTIAL DEPENDENCE OF PERCOLATION RESISTANCE ON GATE VOLTAGE AND ITS IMPACTS ON PROGRESSIVE BREAKDOWN—V.L. Lo⁽¹⁾, K.L. Pey^(1,2), C.H. Tung⁽²⁾, D.S. Ang⁽¹⁾, L.J. Tang⁽²⁾ (1) Nanyang Technological Univ., Singapore; (2) Institute of Microelectronics, Singapore

Novel observations on the evolution of percolation resistance (Rperc) during progressive gate oxide breakdown are presented. Most importantly, the exponential dependence of Rperc on the applied gate voltage provides new physical insights into the mechanisms behind progressive gate oxide breakdown commonly observed in ultrathin gate MOSFETs.

DI07 DEVICE DEGRADATION MODEL FOR STACKED-ONO DIELECTRIC STRUCTURE WITH USING SONOS AND MOS TRANSISTORS—J.-H. Yi, Y.-H. Son, S.-D. Lee*, J.H. Ahn*, , H. Shin, Y.-J. Park, and H.S. Min, Seoul National Univ., Seoul, Korea *Hynix Semiconductor, Kyoungki, Korea

With using two different gate dielectric structures of stacked-ONO and single-oxide, device degradation in SONOS has been investigated. With comparing the electrical characteristics under the FN stress, it is found that the anode hot holes make a cause to degrade anode oxide and give the gate polarity-dependent asymmetric device degradation.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

ES ESD

Co-Chairs: Gianluca Boselli, Texas Instruments and
Warren R. Anderson, Intel Massachusetts, Inc.

ES02 DESIGN ON POWER-RAIL ESD CLAMP CIRCUIT FOR 3.3-V I/O INTERFACE BY USING ONLY 1-V/2.5-V LOW-VOLTAGE DEVICES IN A 130-nm CMOS PROCESS—M.D. Ker, W.-Y. Chen, and K.-C. Hsu, National Chiao-Tung Univ., Hsin-Chu, Taiwan

A 3.3-V high-voltage-tolerant power-rail ESD clamp circuit in a 1-V/2.5-V technology is proposed. A special ESD detection circuit is designed to improve ESD robustness of the stacked NMOS by substrate-triggered technique. Experimental results have proven the excellent effectiveness and ultra-low leakage current of this new proposed power-rail ESD clamp circuit.

ES03 SIGNIFICANCE OF INCLUDING SUBSTRATE CAPACITANCE IN THE FULL CHIP CIRCUIT MODEL OF ICs UNDER CDM STRESS—M.S.B.Sowariraj, A.J.T. Mouthaan, C. Salm, Univ. of Twente, Enschede, Netherlands, P. de Jong, T. Smedes and F.G. Kuper*, Philips, Nijmegen, Netherlands *also with Univ. of Twente, Enschede, Netherlands

Historically, CDM circuit models only include the capacitors formed by the IC circuit design on the package. This paper emphasizes the need to include the die attachment plate capacitance. A simple method to include this capacitor and its discharge path through the circuit during CDM stress is also presented.

ES04 DESIGN AND CHARACTERIZATION OF A NOVEL HIGH VOLTAGE POWER SUPPLY ESD PROTECTION—K. Reynders, P. Moens, D. Wojciechowski and M. Tack, AMI Semiconductor, Oudenaarde, Belgium

This paper presents an active clamp circuit built around a high voltage VDMOS which is designed to survive bipolar snapback. For low currents it operates as "active clamp" and for high currents in bipolar snapback. The snapback current level is higher than 250mA for (transient) latch-up safety during normal operation.

ES05 ESD PROTECTION WINDOW TARGETING USING LDMOS-SCR DEVICES WITH pWELL-nWELL SUPER-JUNCTION—V.A. Vashchenko and M. ter Beek, National Semiconductor, Santa Clara, CA

A methodology implementing a partly diluted super-junction structure for achieving ESD protection of high voltage pins in a low voltage technology is presented. The methodology was applied to the case of turn-on voltage increase of an extended drain SCR ESD protection device in a 5V CMOS process.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

FA FAILURE ANALYSIS

Co-Chairs: David P. Vallett, IBM and
William K. Lo, Credence Systems

FA01 NOVEL ELECTRICAL RE-CONNECTION OF VFBGA (VERY THIN FINE PITCH BALL GRID ARRAY) PACKAGE FOR ADVANCED BACKSIDE FAULT ISOLATION—L. Qian, Intel Products Shanghai Ltd., Shanghai, China

In non-volatile memory, e.g. flash, bit-line to bit-line induced failure is becoming more and more complicated with the aggressive FAB shrinking. 3 failure models were presented. Bit-line to bit-line resistance was traditional with all FAB processes since 0.25 µm. Bit-line to bit-line capacitor was observed with recent popular 0.13µm FAB process. Bit-line to bit-line diode was foreseen in future 0.9µm or smaller FAB process and close to Si limitation. Physical defect modes and unique behaviors have been described.

FA02 STUDY OF SILICON-NITRIDE INDUCED DAMAGE ON THIN GATE OXIDE—W. Dong, J. Zhou, S. Liao, C. Niou, and W.T.K. Chien, SMIC, Shanghai, China

One gate oxide integrity issue was analyzed through electrical and physical method. Physical failure analysis, such as TEM and parallel lapping, provides important evidence of cause analysis. Also, one possible explanation, that high stress induced defects, was suggested for process improvement.

FA04 FAILURE ANALYSIS OF PIXEL SHORTING PROBLEM OF POLYMER LIGHT EMITTING DIODE (PLED) DISPLAYS—L. Wu, A. Johnson, D. Kolosov, I. Parker, and J. Trujillo, DuPont Displays, Santa Barbara, CA

A failure analysis process combining electrical characterization, optical microscopy, SEM/FIB, and other analytical methods to identify the root cause of pixel shorts in polymer light emitting diode displays is presented. This paper will discuss the FA process, the characterization data, and the identified failure mechanisms in detail.

FA05 PHYSICAL MECHANISM OF HIGH RESISTANCE OF TUNGSTEN PLUG AS A ROOT CAUSE OF LOW YIELD AND RELIABILITY ISSUE IN DEEP-SUB-MICRO Si TECHNOLOGY—W. Zhang, Y.X. Li, Y.L. Lee, S.H. Mew, K.T. Tan, Systems on Silicon, Singapore

A new failure mechanism is proposed and verified addressing one yield loss and reliability issue due to high tungsten plug resistance. It is suggested F-containing residual introduced during via etch was not completely removed by post-etch cleaning and resulted in fluorides. Process was optimized and via performance was improved without extra process cost.

FA06 INVESTIGATION OF LOCALIZED BREAKDOWN SPOTS IN THIN SiO₂ USING SCANNING CAPACITANCE MICROSCOPY—S.D. Wang, M.N. Chang*, C.Y. Chen*, and T. F. Lei, National Chiao Tung Univ., Hsin-Chu, Taiwan *National Nano Device Labs, Hsin-Chu, Taiwan,

Scanning capacitance microscopy (SCM) was employed to observe oxide breakdown. The localized breakdown spots obviously exhibit low differential capacitance signals and approximately range from 6 nm to 13.5 nm in lateral direction. According to contact-mode atomic force microscopy (AFM) image, the surface morphology has little effect on the SCM signal.

FA07 JUNCTION LEAKAGE INDUCED BY SILICON DISLOCATION IN A 0.13 MICRON LOGIC PROCESS—R. Chen, J.Y.C. Lin, W. Dong, A. Guo, S. Liao, C. Niou, and K.Chien, SMIC, Shanghai, China

One mechanism of SRAM single bit fail is confirmed by electrical and physical method in this paper. Failure analysis found silicon dislocation in LDD area. Device simulation result and junction delineation provide evidence that the dislocation drill through the LDD area into substrate.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

HK HIGH k DIELECTRICS

Co-Chairs: Masaaki Niwa, Panasonic and Barry P. Linder, IBM

HK01 EFFECTS OF POST METALLIZATION ANNEALING ON THE ELECTRICAL RELIABILITY OF ULTRA-THIN HfO₂ FILMS WITH MoN AND WN GATE ELECTRODE—S. Chatterjee, Y. Kuo, J. Lu, J.Y. Tewg, Texas A&M Univ., College Station, TX, and P. Majhi, SEMATECH, Austin, TX

The electrical reliability aspects, e.g., leakage current and charge trapping, are studied for HfO₂ dielectric with MoN and WN gate electrodes. The generation of oxide traps can be obtained considering the total contribution of charge trapping and SILC. The time-to-breakdown for both SBD and HBD increases with PMA temperature.

HK02 EFFECTS OF OPTIMIZED NITROGEN TAILORING IN HIGH-k DIELECTRICS ON IMPURITY PENETRATION AND STRESS INDUCED DEVICE DEGRADATION—C.Y. Kang, S.J. Rhee, C.H. Choi, M.S. Akvar, H.S. Kim, M. Zhang, T. Lee, I. Ok, F. Zhu, and J.C. Le, UT Austin, Austin, TX

The effects of TSN HfSiON gate dielectrics on the charge trapping and time dependent threshold voltage instability is presented. TSN HfSiON structure was found to be useful in confining nitrogen near the top interface, which is effective in blocking metallic impurity penetration, and in improving the bottom interface quality and thickness control.

HK03 BREAKDOWN AND CONDUCTION MECHANISMS OF ALD HfSiON DIELECTRIC WITH TaN GATE USING CARRIER SEPARATION ANALYSIS—S.J. Doh, J.H. Lee, J.P. Kim, J.-H. Lee, Y.-S. Kim, H.-J. Lim, H.-S. Jung, S.K. Han, M.J. Kim, N.-I. Lee, H.-K. Kang, S.G Park, and S.B. Kang, Samsung Elect. Co., Ltd., Yongin-City, Korea

We evaluated breakdown and conduction mechanisms of ALD HfSiON with TaN gate. The degradation and breakdown of the dielectric is accelerated by the electron trap generation from the band edge of TaN gate and the conduction band edge of Si substrate. The conduction mechanism of the electron and hole is FN tunneling.

HK04 INFLUENCE OF GATE MATERIAL AND STRESS VOLTAGE ON POST BREAKDOWN LEAKAGE CURRENT OF HIGH k DIELECTRICS—R. Duschl, M. Kerber, U. Schroeder, T. Hecht, S. Jakschik, C. Kapteyn and S. Kudelka, Infineon Technologies AG, Munich, Germany

The breakdown behaviour of Al₂O₃ dielectrics is investigated as a function of electrode material, stress voltage and thickness. Two stable BD phases were found even for metal electrodes which are attributed to finite threshold energy for hard break formation. This results in a limitation of post BD current at product conditions and therefore opens up possibilities for target relaxation.

HK05 THRESHOLD VOLTAGE INSTABILITY OF HfSiO DIELECTRIC MOSFET UNDER PULSED STRESS—R. Choi, R. Harris, B.H. Lee*, C.D. Young, J.H. Sim, K. Matthews, M. Pendley and G. Bersuker, SEMATECH, Austin, TX *IBM Assignee

Effects of on-time, off-time, and rise/fall time of AC stress on Vth shift in the HfSiO gate dielectric NMOSFETs have been studied. The results suggest charge redistribution occurs during on-time due to the applied field, making relaxation harder in the sample stressed

HK06 IMPLICATION OF POLARITY DEPENDENCE DEGRADATION ON nMOSFET WITH POLYSILICON/Hf-SILICATE GATE STACK—R. Choi, B.H. Lee*, C.D. Young, J.H. Sim, K. Mathews, G. Bersuker, and P. Zeitzoff, SEMATECH, Austin, TX *IBM Assignee,

Negative bias stress on gate of nMOSFET causes more damages than positive bias stress in terms of interface states density and accordingly, subthreshold swing degradation. Similar situation as negative bias stress on gate occurs at the edge of drain when gate is off and drain bias is on. This drain to gate stress causes asymmetric degradation of the channel and subthreshold swing increase. It is more prominent in MOSFET with small gate length. It is believed to be due to high geometric ratio of the stressed region to channel. Therefore, it must become a serious challenge to the further device scaling.

HK07 COMPARISON OF HOT CARRIER STRESS AND CONSTANT VOLTAGE STRESS IN Hf-SILCIATE NMOS TRANSISTORS WITH POLY AND TiN GATE STACK—J.H. Sim, SEMATECH, UT Austin, B.H. Lee*, S.C. Song, SEMATECH, C.D. Young**, R. Choi, H.R. Harris**, and G. Bersuker, SEMATECH, Austin, TX *IBM assignee; **AMD assignee

Based on the comparison of CVS and HCS dependence of the V_th/g_m/I_d,_sat parameters, we showed a feasibility to separate the reversible charge trapping induced degradation from the permanent damage using a negative bias. In the case of the poly gate electrode, the stress bias dependant positive charge, attributed to the hole generation/trapping process, may complicate the evaluation of the CVS and HCS. Accumulation of HCS induced degradation has been shown with TiN gate device, while the degradations of poly gate device have been dominated by the charge trapping that does not generate the permanent damage.

HK08 EFFECTS OF HIGH-k POST-DEPOSITION CLEANING IN IMPROVING CMOS BIAS INSTABILITIES AND MOBILITY A POTENTIAL ISSUE IN RELIABILITY OF DUAL METAL GATE TECHNOLOGY—M.S. Akbar, N. Moumen, J. Barnett, B.-H. Lee, and J.C. Lee, UT Austin, Austin, TX

The effects of H₂O and HCl post-clean after Hf-silicate deposition in improving bias instability, reliability and mobility of CMOS devices have been demonstrated. It was found that HCl post-treatment reduced charge trapping, thus improved bias instabilities, but had no effect on interface traps. High pressure H₂ anneal improved interface states significantly, with no effect on bulk traps at all.

HK09 DOMINANT SILC MECHANISMS IN HfO₂/TiN GATE NMOS AND PMOS TRANSISTORS—S.A. Krishnan, J.J. Peterson, C. Young, G. Brown, R. Choi, R. Harris^(a), J.H. Sim, B.H. Lee, P. Zeitzoff, P. Kirsch^(b), J. Gutt, H.J. Li^(c), K. Matthews, J.C. Lee*, and G. Bersuker, SEMATECH, Austin, TX assignments from (a) AMD, (b) IBM, (c) Infineon; *UT Austin, Austin, TX

Low stress voltage SILC characteristics of the HfO₂/TiN gate stack were investigated. SILC dependence on the stress time and polarity was found to closely correlate with the threshold voltage in both nMOS and pMOS transistors suggesting that major stress-induced changes in both parameters are primarily determined by reversible electron trapping in pre-existing defects, although some trap generation is seen to occur during the initial stages of stress.

HK10 SIGNIFICANT IMPROVEMENT IN RELIABILITY OF HfSiON GATE INSULATOR—M. Inoue, J. Yugami, F. Fujita, K. Shiga, M. Mizutani, K. Nomura, J. Tsuchimoto, Y. Ohno, and M. Yoneda, RENESAS, Itami-shi, Japan

Instability during positive-bias-temperature (PBT) and channel-hot-carrier (CHC) stresses in nFET is studied for various HfSiON with interface layer. Significant improvement is observed for HfSiON/SiON and PDA-HfSiON equivalent to SiON, while HfSiON/chemical-oxide shows large DVth. The result is discussed in terms of electron-trapping efficiency in HfSiON layer.

HK11 EFFECT OF HIGH PRESSURE DEUTERIUM ANNEALING ON ELECTRICAL AND RELIABILITY CHARACTERISTICS OF MOSFETs WITH HIGH-k GATE DIELECTRIC—H. Park, M.S. Rahman, M. Chang, B. Lee^(*,a), M. Gardner^(*,a), C.D. Young*, and H. Hwang, Gwangju Inst. of Science & Tech., Gwangju, Korea *International SEMATECH, Austin, TX; (a) IBM assignee; (b) AMD assignee

To completely passivate interface states of high-k gate dielectric, we have investigated high pressure annealing. Comparing with forming gas annealed sample, high pressure(5-20 atm) annealing of nMOSFET at 400°C shows 10-15% improvements of linear drain current and maximum transconductance. High pressure D₂ annealed samples exhibit longer hot carrier lifetime than FG annealed

HK12 CHARGE TRAPPING BY OXYGEN-RELATED DEFECTS IN HfO₂-BASED HIGH-k GATE DIELECTRICS—K.Yamabe^(1,5), M. Goto⁽¹⁾, K. Higuchi⁽¹⁾, A. Uedono^(1,5), K. Shiraishi^(1,5), S. Miyazaki^(2,5), K. Torii⁽⁴⁾, M. Boero⁽¹⁾, T. Chikyow⁽⁵⁾, S. Yamasaki⁽⁶⁾, H. Kitajima⁽⁴⁾, T. Arikado⁽⁴⁾, and K. Yamada^(3,5) (1) Univ. Tsukuba, Tsukuba, Japan; (2) Hiroshima Univ., Hiroshima, Japan; (3) Wased Univ., Tokyo, Japan; (4) Selete, Tsukuba, Japan; (5) NIMS, Tsukuba, Japan; (6) AIST, Tsukuba, Japan

Time dependent leakage currents under constant voltage stresses are investigated by the carrier separation method using field effect transistor structures with HfO₂-based high-k gate dielectric films. The experimental results were explained in terms of the close relationship the electron/hole trapping centers and oxygen-related defects in the high-k dielectric films, respectively.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

HV HIGH VOLTAGE DEVICES

Co-Chairs: Prasad Chaparala, National Semiconductor Corp.
and Peter Moens, AMI Semiconductor Belgium

HV01 RELIABILITY FAILURES DUE TO CHARGE INJECTION IN SOI UNDER HIGH VOLTAGE CONDITIONS—H.J. Bruggers, I.M. Emmerik-Weijland, and R.T.H. Rongen, Philips Semiconductors, Nijmegen, Netherlands

A new degradation phenomenon for a HV-PDMOST, manufactured in SOI, has been investigated. When stressing the component above 400 V, a narrow-band-leakage (quasi breakdown) between 30 and 60 V has been observed. This leakage, which can be destructive, is suppressed by optimizing doping levels and component design in the drift region of the transistor.

HV02 COMPREHENSIVE STUDY OF POSTPROCESSED COPPER HEAT SINKS ON SMART POWER DRIVERS FOR THERMAL SOA IMPROVEMENT—G. Van den bosch, E. Driessens, T. Webers, B. Elattari, D. Wojciechowski⁽¹⁾, P. Gassot⁽¹⁾, P. Moens⁽¹⁾, G. Groeseneken⁽²⁾, IMEC, Leuven, Belgium (1) AMI semiconductor Belgium, Oudenaarde, Belgium; (2) also at Catholic Univ., Leuven, Belgium

We performed an extensive simulation and experimental study on the effect of a copper cover layer on thermal management in large power drivers. Substantial reduction in temperature can only be expected with very thick copper layers. Heat sink structures have been postprocessed by electroplating and evaluated by energy capability (EC) measurements. A recorded 25% improvement in EC for realistic heat sink design enables similar driver area reduction in EC critical applications.

HV03 EFFECT OF LAYOUT ORIENTATION ON THE PERFORMANCE AND RELIABILITY OF HIGH VOLTAGE NLDMOS IN STANDARD SUBMICRON LOGIC STI CMOS PROCESS—B. Wang, H. Nguyen, A. Horch, Y. Ma, T. Humes, and R. Paulsen, Impinj, Seattle, WA

In this work, we investigated the typical layout geometry dependence of BVDSS and on-state current characteristics for N-LDMOS devices fabricated in logic 0.18 µm and 0.25 µm STI processes. For the first time, a dependence on layout orientation and its effect on HCI reliability were also reported.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

IT INTERCONNECTS

Co-Chairs: Ennis T. Ogawa, Texas Instruments and
Glenn B. Alers, Novellus Systems

IT01 DEGRADATION OF ELECTROMIGRATION LIFETIME BY POST-ANNEALING FOR Cu/LOW-k INTERCONNECTS—Y. Kakuhara and K. Ueno, NEC Electronics Corp., Kanagawa, Japan

The effect of post-annealing on EM reliability for Cu/Low-k interconnects is investigated by annealing packaged samples. The EM lifetime was degraded by annealing only in the low failure distribution. The degradation was suppressed by applying deeper plasma pre-clean etch for the vias, so it is considered that the degradation is related to the Cu quality at the via interface.

IT02 DETERMINATION OF THE ACCELERATION FACTOR BETWEEN WAFER LEVEL AND PACKAGE LEVEL ELECTROMIGRATION TEST—X.Federspiel, Philips Semiconductors, Crolles, France, D. Ney, and V. Girault, STMicroelectronics, Crolles, France

We built a numeric electromigration model based on Korhonen equation. The analysis of simulated lifetime on 2 order of magnitude of current density predicts that error on Black's law parameters Ea and n may occur. We recommend taking into consideration temperature gradients and stressing effect to correctly extrapolate lifetime.

IT03 INFLUENCE OF DIFFUSION BARRIER ON RELIABILITY IDENTIFICATION OF DIFFUSION PATHS IN Cu/POROUS LOW k INTERCONNECT—J.F. Guillaumond^(1,2), L. Arnaud⁽²⁾, C. Guedj⁽²⁾, V. Arnal⁽²⁾, W.F.A. Besling⁽³⁾, G. Reimbold⁽²⁾, M. Dupeux⁽⁴⁾, and J.Torres⁽¹⁾ (1) STMicroelectronics, Crolles, France; (2) CEALeti, Grenoble, France; (3) Philips Semiconductor, Crolles, France; (4) LTPCM, Saint Martin d'Heres, France

The electromigration reliability of Cu / ultra low k interconnects is found to strongly depend on the metal barrier thickness and its deposition process. The lifetime decreases with the liner thickness, and different aging mechanisms occur between the ALD and PVD splits. A surface treatment is proposed to improve the liner efficiency and to simultaneously increase the metal reliability.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

MY MEMORY

Co-Chairs: Guoqiao Tao, Philips Semiconductors and
Hanmant Belgal, Intel

MY01 METHOD FOR ENDURANCE OPTIMIZATION OF THE HIMOS FLASH MEMORY CELL—T. Yao, A. Lowe, T. Vermeulen, N. Bellafiore, AMI Semiconductor Belgium, Oudenaarde, Belgium, J. Van Houdt, D. Wellekens, IMEC Leuven, Belgium

Negative oxide charge located at the Split-point is the main cause of the threshold voltage window closure in Source Side Injection Flash EEPROM cells under 105 Write/Erase cycles. The trapping and detrapping behavior of this charge are studied. Finally, a method for reducing it is proposed.

MY02 A VOLTAGE ACCELERATION LIFETIME MODEL TO PREDICT POST-CYCLING LTDR CHARACTERISTICS OF SPLIT-GATE FLASH MEMORIES—L.-C. Hu, A.-C. Kang*, T.I. Wu*, E. Chen*, J.R. Shih*, H.W. Chin*, Y.-F. Lin*, K. Wu*, Y.-C. King, National Tsing-Hua Univ., Hsin-Chu, Taiwan, ROC *TSMC, Hsin-Chu, Taiwan, ROC,

A fast test methodology to predict post-cycling low temperature data retention (LTDR) lifetime of split-gate flash memories based on word-line stress to accelerate the charge gain effect in the trap-assist-tunneling (TAT) regime has been developed. Lifetime tests using word-line stress conditions can be completed in a much shorter period, providing efficient accurate lifetime prediction for thicker gate.

MY03 A HIGHLY RELIABLE NAND STRUCTURE FLASH MEMORY CAPABLE FOR LOW VOLTAGE OPERATION—Y.T. Lin, C.S. Lai, Chang-Gung Univ., Tao-Yuan, Taiwan, S.S. Chung, National Chiao Tung Univ., Hsin-Chu, Taiwan, E. Yang, S. Pittikoun, S.-M. Tzeng, Powerchip Semiconductor, Hsin-Chu, Taiwan, T. Chen, R. Shen, and C.C.-H. Hsu, eMemory, Hsinchu, Taiwan

A new flash cell called buried bit-line AND (BiAND) is proposed. Buried bit-line AND flash can achieve low voltage programming/erase. Cell reliability for different schemes, i.e., high voltage Fowler-Nordheim (HV F-N) and Bi F-N operation schemes, has been compared. Results show that BiAND scheme gives much better endurance and data retention characteristics.

MY04 DIELECTRIC ENGINEERING IN NANOCRYSTAL MEMORY DEVICES FOR IMPROVED PROGRAMMING DYNAMICS—J.J. Lee, W. Bai, and D.-L. Kwong, UT Austin, Austin, TX

This paper presents the results of the dielectric engineering in a silicon nanocrystal (Si NC) memory with high-k dielectrics. Si NC memory devices with the engineered control barrier have been fabricated and characterized based on the theoretical investigation of the programming instability in Si NC memory under the Fowler-Nordheim (F-N) programming regime.

MY06 EFFECT OF STI SHAPE AND TUNNELING OXIDE THINNING ON CELL VTH DISTRIBUTION IN THE FLASH MEMORY—J.D. Lee, J.H. Kim, W. Lee, S.H. Lee, H.Y. Lim, J.D. Lee, S.W. Nam, H.D. Lee, and C.L. Song, Samsung Electronics Co., Ltd, Yongin-City, Korea

We studied factors which affected cell Vth variation in the flash memory. Our simulation and experimental results clearly showed that the shape of Shallow Trench Isolation and tunnel oxide thickness in the STI edge were the main factors for cell V_th variation. A smaller oxidation activation energy resulted in the better thinning and cell V_th variation.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

PC PRODUCT & CIRCUIT RELIABILITY

Co-Chairs: Bill Abadeer, IBM and
Andreas Preussger, Infineon Technologies AG

PC01 HOW MUCH MISMATCH SHOULD BE SIMULATED IN THE HIGH DENSITY SRAM SENSE AMPLIFIER DESIGN—T. Peng, Cypress Semiconductor Corp., Nashua, NH

Device mismatch in static ram (SRAM) has a strong impact to the speed yield. In this paper, a rigorous statistical model of the mismatch settings for the simulations of the sense amplifier (SA) in SRAM is presented. The model comprehends the memory density, the circuit architecture, and the mismatch delay sensitivity.

PC02 INVESTIGATION INTO THE CORRELATION OF WAFER SORT AND RELIABILITY YIELD USING ELECTRICAL STRESS TESTING—A. Flynn and S. Millar, Xilinx Ireland, Dublin, Ireland

In this paper we present our initial findings of implementing stress tests (EVS/DVS) at wafer sort on a mature 0.25 µm CMOS product and its correlation to product reliability. We also present data which shows that EVS/DVS fails can be identified by observing the increments in standby current after stress tests.

PC03 FAST WLRC APPLICATIONS IN FOUNDRY FABRICATION—S. Tseng, W.T.K. Chien, W. Wang, A. Zhao, and E. Gong, SMIC, Shanghai, PR China

New reliability test methods and structures are needed and applied in advanced microelectronic fabrication. In this paper, we report new test methods and structures in integrated circuit (IC) reliability test. This work provides in-depth discussions on the double-point gate oxide integrity (GOI) test, fast I-ramp electromigration (EM) test, and an innovative test pattern to verify the probe contact resistance (PCR) and to improve WLRC (Wafer Level Reliability Control) test effectiveness, accuracy, and stability.

PC04 NOVEL TEST CHIP FOR STATISTICAL EVALUATION OF DEFECT DENSITY AND RELIABILITY OF CONTACTS AND VIAS—A. Cabrini, D. Cantarelli*, P. Cappelletti*, R. Casiraghi*, D. Iezzi*, C. Lombardi*, A. Maurelli*, M. Pasotti*, P.L. Rolandi*, and G. Torelli, Univ. of Pavia, Pavia, Italy *STMicroelectronics, Agrate Brianza MI, Italy

Resistive contacts and VIAs are becoming a relevant cause of failures in high density CMOS, affecting both process yield and product reliability. This paper presents a new test chip specifically conceived for allowing a full investigation on statistical base of interconnect elements, including electrical behaviour, reliability and failure analysis.

PC05 HOT CARRIER EFFECT ON RF POWER AMPLIFIERS—E. Xiao, UT at Arlington, Arlington, TX

This paper, for the first time, investigates hot carrier (HC) effect on RF power amplifiers in 0.16 µm CMOS technology. The 0.16 µm NMOSFET devices are stressed, and aged model parameters are extracted experimentally. The aged parameters are used to evaluate HC effect on a CMOS class AB RF amplifier working at 2.45 GHz for wireless communications. It is shown that both output power and the power added efficiency are degraded significantly.

PC06 ESTIMATING DPPM DURING THE PROTO-TYPE TO PRODUCT RAMP PHASE—T.J. Anderson, Texas Instruments, Dallas, TX

A process allowing one to estimate the early failure rate and subsequent defective PPM for a product's use ispresented. Keys points for early technology implementation are a limited sample size, identifying and assessing the impact of a failure distribution, determining a defect Pareto, de-rating to Product use, Test Screen modifications or Process iterations needed for further improvements and any applicable burn in duration.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

PI PROCESS INTEGRATION RELIABILITY

Co-Chairs: Vijay Reddy, Texas Instruments and
Carl Kyono, Freescale

PI01 GETTERING EFFECT OF HIGH-DOSE ARSENIC IMPLANTATION AND BORON DIFFUSION ON GATE OXIDE INTEGRITY IN TRENCH ISOLATED HIGH VOLTAGE SILICON-ON INSULATOR PROCESS—D.H. Lu, S. Jimbo, N. Fujishima , S. Wakimoto, and M. Ogino, Fuji Electric Advanced Tech. Co., Ltd., Nagano, Japan

High dose arsenic implantion is introduced between active silicon-on-insulator and buried oxide in bonded and etched-back SOI wafers along with surface boron diffusion to improve gate oxide integrity in fully trench isolated high-voltage SOI process.

PI02 RELIABILITY OF MIM HAO CAPACITOR FOR 70 nm DRAM—K. Hong, D.-S. Kil, H.-K. Woo, J. Kim, H.-S. Song, K.-S. Park, S.-J. Yeom, H.-S. Yang, J.-S. Roh, H.-C. Sohn, J.W. Kim, and S.-W. Park, Hynix Semiconductor Inc., Ichon, Korea

Package level reliability characterization of MIM hafnium based capacitor dielectrics is given. It is demonstrated that package level EFR stress does not degrade the MIM characteristics.

PI03 COPPER VIA CHAIN UNDER ETCHING PROCESS IMPROVEMENT—J. Ji, M. Zhang, W. Dong, A. Guo, S. Liang, S. Liao, C. Niou, and K. Chien, SMIC, Shangha, China

It is demonstrated that via underetching frequently occurs at the end of a Cu via chain. A model is developed to explain this phenomenon and drive root cause elimination.

PI04 STRESS MIGRATION RELATED RELIABILITY CONCERNS—J.-Y. Ma, S.F.C. Tseng, K.W.T. Chien, and V.W.W. Ruan, SMIC, Shanghai, PR China

Stress migration failures due to missing tungsten via are eliminated through root cause process experiments. To improve the cycle time for stress migration characterization, a self-heated test structure and test methodology is proposed.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

SE SOFT ERRORS

Co-Chairs: Norbert Seifert, Intel and Ken Rodbell, IBM

SE01 CANCER RADIOTHERAPY EQUIPMENT AS A CAUSE OF SOFT-ERRORS IN ELECTRONIC EQUIPMENT—J.D. Wilkinson, C. Bounds, T.Brown, B. Gerbi*, and J. Peltier, Medtronic, Minneapolis, MN *Univ. of MN, Minneapolis, MN

This study investigates the undesired generation of soft errors in electronics close to cancer radiotherapy linear accelerators. The SER is dominated by interaction of thermal neutrons with ¹⁰B in the BPSG used as a dielectric material in some of the ICs of the nearby electronic.

SE02 A NEW NEUTRON FACILITY FOR SINGLE-EVENT EFFECT TESTING—A.V. Prokofiev, S. Pomp, J. Blomgren, O. Byström, C. Ekström, O. Jonsson, D. Reistad, U. Tippawan*, D. Wessman, V. Ziemann, and M. Österlund, Uppsala Univ., Sweden *also with Chiang Mai Univ., Thailand

A new quasi-monoenergetic neutron beam facility for testing of single-event effects in electronics has been constructed at the Svedberg Laboratory (TLS) in Uppsala, Sweden. Key features include an energy range of 20 to 175 MeV, high fluxes and the possibility of large-area fields. Beam characterization measurements are reported.

SE03 UNFOLDING PROCEDURE FOR SER MEASUREMENTS USING QUASI-MONOENERGETIC NEUTRONS—M. Olmos, A. Prokofiev*, and R. Gaillard, iRoC Technologies, Grenoble, France *Uppsala Univ., Uppsala, Sweden

This work presents an unfolding algorithm for SER measurements using quasi-monoenergetic neutrons. The purpose of the algorithm is to correct SER results for the contribution of the low-energy tail in the neutron spectrum. Corrected SER results are compared with measurements at the LANSCE and TRIUMF neutron sources.

Tuesday, April 19, 7:00 p.m., San Jose Marriott Ballroom

TR TRANSISTORS

Co-Chairs: Anand Krishnan, Texas Instruments and
Muhammed Ashraful Alam, Purdue University

TR01 CHANNEL SOFT BREAKDOWN ENHANCED EXCESS LOW-FREQUENCY NOISE IN ULTRA-THIN GATE OXIDE PD ANALOG SOI DEVICES—S. Chiang, M.F. Lu, M.C. Chen, and S. Huang-Lu, UMC, Hsin-Chu, Taiwan

The impact of soft breakdown location on drain current noise in partially depleted SOI MOSFETs with ultrathin oxide (1.6nm) is investigated. The origin of this excess noise is believed to be related to SBD enhanced electron valance-band tunneling induced floating

TR02 IMPACT OF SUBSTRATE BIAS ON p-MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITY—S. Mahapatra, T.R. Dalei, P.B. Kumar, D. Vargheese, D. Saha, Indian Institute of Tech. Bombay, Powai, India, and M.A. Alam, Purdue Univ., W. Lafayette, IN

NBTI is studied in the presence of substrate bias. Increased NBTI seen under such condition is linked to increased interface-trap and bulk-trap generation, due to impact ionization and hot-hole generation in the substrate. Effect of oxide field, temperature, substrate bias and oxide thickness is studied.

TR03 MECHANISM OF ON-CURRENT AND OFF-CURRENT INSTABILITIES UNDER ELECTRICAL STRESS IN POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS—S. De Wang, T.Y. Chang, W.H. Lo, and T.F. Lei, National Chiao Tung Univ., Hsin-Chu, Taiwan, ROC

The On and Off-current instabilities of poly-Si TFTs have been investigated. The stress-induced defects were monitored by measuring the dependence of the Ion and Ioff variations on the drain and gate voltages. We proposed a comprehensive model for the device degradation in poly-Si TFTs under electrical stress.

TR04 A NEW FINDING ON NBTI LIFETIME MODEL AND AN INVESTIGATION ON NBTI DEGRADATION CHARACTERISTIC FOR 1.2 nm ULTRA THIN OXIDE—C.L. Chen, Y.M. Lin, C.J. Wang, and K. Wu, TSMC, Hsin-Chu, Taiwan

A new finding on 1.2 nm NBTI lifetime is proposed as E-model for low field region (<10MV/cm) and power law model for high field region (>10MV/cm). The mechanism of NBTI degradation is explained as the hydrogen diffusion model which supports the non-saturated degradation behavior and lifetime prediction model.

TR05 NEW OBSERVATIONS ON THE DAMAGE RELAXATION MECHANISMS IN p-MOSFETs UNDER DYNAMIC NBTI STRESSING—D.S. Ang and S. Wang, Nanyang Tech. Univ., Singapore

Unipolar dynamic NBTI stressing exhibits a unique two-stage relaxation mode, comprising an almost equal annihilation of interface states and positive charge in the first stage, followed by a more rapid annihilation of positive charge. This unique relaxation mode is observed in both ultra-thin oxynitride and silicon nitride gate stack.

TR06 THE ENERGY DRIVEN PARADIGM OF NFET HOT CARRIER EFFECTS—S.E. Rauch III, IBM, Hopewell Jct., NY

A new paradigm of nfet hot carrier behavior is proposed based upon available energy, rather than peak electric field as in the Lucky Electron Model. This new concept is shown, by both physical arguments and experiment, to be applicable for devices of 180 nm class

TR08 LOCALIZATION OF NBT HOT CARRIER-INDUCED OXIDE DAMAGES IN SOI pMOSFET's—C.S. Lai, S.C. Hung, Chang Gung Univ., Tao-Yuan, Taiwan, J.W. Lee, National Nano Device Lab., Taiwan, and S.S. Chung, National Chiao Tung Univ., Taiwan

The NBTI-like HC degradation of the SOI pMOSFET's was investigated. The hole trapping model was proposed to explain both the electron and hole component increases during stressing and the activation energy has also been extracted. It was observed that NBTI-like HC degradation was the worst case for SOI pMOSFET's.

TR09 PHYSICAL MECHANISM OF NBTI RELAXATION BY RF AND NOISE PERFORMANCE OF RF CMOS DEVICES—Z. Luo, Auburn Univ., Auburn, AL, and J. P. Walko, IBM, Essex Jct., VT

RF, dc, and flicker noise degradation and relaxation of RF CMOS devices after NBTI was reported for the first time. Results suggest the relaxation of the degradation involves both fixed charge and interface charge. As fixed charge drifts out of the oxide, some recombines to reduce the interface state density.

TR10 MOSFET ASYMMETRY AND GATE-DRAIN/SOURCE OVERLAP EFFECTS ON PERFORMANCE AND HOT CARRIER RELIABILITY—S. Aur, S.-H. Yang and T. Tran, Texas Instruments, Dallas, TX

The MOSFET gate-drain/source overlap is a critical factor in device performance. We have found that the MOSFET asymmetry can degrade reliability even worse if overlap is small. The MOSFET asymmetry, gate-drain/source overlap, performance trade-off and hot carrier reliability are studied in this paper on 90 nm technology.