Reliability mechanisms and VLSI circuit design

Over the years, technology scaling has revealed new challenges for VLSI processing, design, test and reliability engineering. A major enabling phenomenon for VLSI scaling has been the close collaboration within the industry between the process, test, design and reliability disciplines. This tutorial discusses examples of reliability mechanisms and how these have affected design of selected VLSI circuits.

Wayne F. Ellis

Wayne F. Ellis received the A.A.S. in Electrical Technology from Hudson Valley Community College in 1974. He joined the IBM East Fishkill facility where he worked as a layout technician on MOS logic chip designs capable of containing up to 120 NAND gates. He received the BSEE from Union College in 1985, and MSEE and Ph.D. in Materials Science from the University of Vermont in 1992 and 1993. From 1977 to the present he has worked at the IBM Microelectronics division labs in Essex Junction Vermont, in DRAM, eDRAM and eSRAM product and technology development. Dr. Ellis spent the fall semester 2002 at the University of Linkoping, Sweden as a Distinguished Visiting Professor in Information Technology, under the auspices of the Swedish and American Fulbright Associations. He is an Adjunct Professor at the University of Vermont and also serves on the Board of Directors for the Vermont Fulbright Association. He is currently working in 65 nm embedded SRAM development.