DRAM Reliability

As DRAM cells are scaled down aggressively, many challenges arise in addressing reliability issues upfront. Creating high cell capacitance, maintaining very low levels of leakage in the pass transistor along with acceptable gate overdrives, good retention characteristics, integrating high performance transistors in the periphery logic - are some of the technological challenges. Maintaining a low cost process with very high yield requirements are essential as memory designs rapidly evolve into multi-gigabit densities. This tutorial will highlight some of these challenges from a process integration perspective. Reliability challenges in meeting retention time requirements for low power designs will also be discussed and physical mechanisms that play a major role will be highlighted.

Chandra Mouli

Dr. Chandra Mouli is with Micron Technology Inc, Boise, Idaho. He is currently a Senior Fellow and Manager of the Device Analysis Group in R&D with responsibilities in the area of advanced device characterization and reliability analysis, test structure design and layout, process/device modeling - for all technologies under development in R&D. He received his undergraduate degree in Physics and MSEE from the Indian Institute of Science in Bangalore, India and Ph.D (EE) from the University of Texas at Austin in 1990. He was with Texas Instruments for couple of years before joining UT/Austin. He is a senior member in IEEE and has served in several technical committees for various conferences, including IEDM and SISPAD.