High-k Gate Dielectrics: Electrical Characterization

To meet the need for higher transistor speed while keeping power consumption under control, the semiconductor industry is working to introduce high-k gate dielectrics in leading-edge transistor manufacturing processes. However, these attempts are hampered by issues with high-k device performance, which were not fully anticipated at the start of high-k development. These issues may be of intrinsic material nature, process tool related, or related to material integration within the fabrication process. In addressing this question, the fundamental factors controlling the value of dielectric constants, along with the major factors determining integration of new materials into the mainstream manufacturing, are discussed in this presentation.

Gennadi Bersuker

Gennadi Bersuker completed his M.S. and Ph.D. in Physics at the Leningrad State University and Kishinev State University, respectively. After graduation, he joined Academy of Sciences, and then worked at Leiden University (The Netherlands) and the University of Texas at Austin. Since 1994, he has been working at SEMATECH on process induced charging damage, electrical characterization of Cu/low K interconnect, advanced CMOS process development and high-k gate stack. Gennadi Bersuker is a SEMATECH Fellow.