1. PRODUCTS & DIELECTRICS

Co-Chairs: Robert Kwasnick, Intel and Ben Kaczer, IMEC

1.1 PREDICTION OF LOGIC PRODUCT FAILURE DUE TO THIN-GATE OXIDE BREAKDOWN—Y.-H. Lee, N. Mielke, M. Agostinelli, S. Gupta, R. Lu, and W. McMahon, Intel, Santa Clara, CA

Models for predicting the oxide-breakdown reliability of high performance CPU logic products are developed from capacitor TDDB data and matched to actual failure rates in high-voltage lifetest. Such a calibration exercise is crucial for accurate reliability estimation. Once calibrated, a model is useful for assessing changes in use conditions or circuit design.

1.2 RECOVERY EFFECTS IN THE DISTRIBUTED CYCLING OF FLASH MEMORIES—N. Mielke, H.P. Belgal, A. Fazio, and Q. Meng, Intel, Santa Clara, CA

Damage from program/erase cycling partially recovers between cycles. The effect is temperature accelerated with an activation energy of 1.1eV. Between-cycle delays dramatically extend retention lifetime for the charge-detrapping mechanism. An accelerated reliability model is proposed which comprehends cycle count, cycle rate, cycling temperature, retention time, and retention temperature.

1.3 POST-BREAKDOWN CHARACTERISTICS OF EXTRINSIC FAILURE MODE FOR ULTRA-THIN GATE OXIDES—E. Wu, IBM, Essex Jct., VT/J. Sune, Univ. Autònoma de Barcelona, Bellaterra, Spain

Post-breakdown properties of extrinsic failure mode are thoroughly investigated in comparison with intrinsic mode. We show that regardless of first BD modes or how the percolation path is initiated, post-breakdown characteristics of intrinsic and extrinsic BD modes are essentially identical, thus suggesting that the same mechanism controls the post-BD phase. This important finding indicates that the post-BD methodology developed for intrinsic BD mode can also be applied to extrinsic BD mode methodology in circuit reliability modeling. A burn-in methodology is developed to take into account of gate oxide reliability in post-breakdown phase.

1.4 A COMPREHENSIVE STUDY OF LOW-k SiCOH TDDB PHENOMENA AND ITS RELIABILITY MODEL DEVELOPMENT—F. Chen, O. Bravo, K. Chanda, P. McLaughlin, T. Sullivan, J. Gill, J. Lloyd, E. Wu, R. Kontra, and J. Aitken, IBM, Essex Jct., VT

The TDDB degradation of CVD low-k dielectric at 65nm technology node under both static and dynamic bias-temperature stresses over a wide range of fields and temperatures were critically studied. Interrelation of field and temperature dependence between TDDB thermal activation energy and field acceleration parameter was identified. Based on the extensive long-term TDDB (longer than 9 months) test results, a new field-acceleration model: ?E model, was developed for reliability lifetime projection with the assumption of unchanged leakage conduction mechanism at use conditions.

Tuesday, March 28, 2:00 p.m., Room A, Parallel Session

2A DIELECTRICS

Co-Chairs: Ben Kaczer, IMEC and
Tanya Nigam, Cypress Semiconductor

2A.1 VOLTAGE SCALING AND STATISTICAL PROPERTIES OF POST-BREAKDOWN FOR ULTRA-THIN-OXIDE PFETS IN INVERSION MODE—E. Wu, IBM, Essex Jct., VT/J. Sune, Univ. Autònoma de Barcelona, Bellaterra, Spain

We report an extensive study of voltage scaling and statistic properties of post-breakdown for ultra-thin-oxide PFETs in inversion mode. We demonstrate that both the first BD and time-to-circuit-failure distributions follow Poisson area scaling even though the TFAIL distributions are non-Weibull. Unlike NFET inversion, which is dominated by a singe-spot progressive BD mode, multiple competing progressive BD spots are found to dominate the post-BD phase in PFET inversion case. The voltage acceleration of TBD(1st) and TRES are found to be similar, also due to the role of competing BD spots.

2A.2 PRECISE AND SIMPLE METHOD FOR DETECTION OF INITIAL DEFECTS IN 1.2 nm GATE DIELECTRICS BASED ON NONLINEAR CONDUCTIONS—H. Suto, T. Muratomi, K. Ebihara, M. Kanno, T. Gocho, and N. Nagashima, Sony Corp., Atsugi-shi Kanagawa, Japan

A precise method to detect initial defects on gate dielectrics is proposed. This method proved to be a powerful tool for choosing the best process conditions to suppress initial defects and predicting the reliabilities. Detailed studies of the gate leakage currents through initial defects and breakdown spots are also discussed.

2A.3 A COMPREHENSIVE STUDY OF FN DEGRADATION FOR DRIVER MOSFETs IN NONVOLATILE MEMORY CIRCUIT—H. Aono, E. Murakami, T. Mizuno, H. Sato, K. Haraguchi, M. Kato, and K. Kubota, Renesas Technology Corp., Ibaraki, Japan

A degradation mode by FN stress is investigated comprehensively . We demonstrate that this degradation really occurs in driver MOSFETs in actual circuits after E/W operation. We also exhibit that this degradation has strong correlation with total injected gate and substrate current and propose a hot-hole induceddegradation mechanism.

2A.4 VOLTAGE ACCELERATION OF TBD AND ITS CORRELATION TO THE POST BREAKDOWN CONDUCTIVITY OF N- AND P-CHANNEL MOSFETs—M. Rohner, A. Kerber, and M. Kerber, Infineon Technologies, Munich, Germany

The gate oxide breakdown behaviour of advanced n- and p-channel CMOS devices was thoroughly investigated from the time range of electrical overstress events (µs) to package level test conditions (10⁶s). The voltage acceleration follows the power-law-model over 12 decades in time. In addition the current -voltage driven wear out was studied for linear and non-linear driver elements. It was found that the evolution of the post breakdown conductivity strongly depends on the current limitation and the associated voltage drop across the driving stage. The post breakdown evolution can be described by the voltage acceleration.

2A.5 EXPLAINING `VOLTAGE-DRIVEN' BREAKDOWN STATISTICS BY ACCURATELY MODELING LEAKAGE CURRENT INCREASE IN THIN SiON AND SiO₂/HIGH-k STACKS—R. Degraeve, P. Roussel, M. Cho, T. Kauerauf, B. Kaczer, and G. Groeseneken, IMEC, Leuven, Belgium

The properties of the hard BD distribution in the presence of a digital soft BD are demonstrated. We show how information on the digital soft BD distribution can be extracted from the leakage current increase preceding the hard BD. By generalizing this interpretation the time dependence of conventional stress-induced leakage current (SILC) in ultra-thin dielectrics is analytically modeled.

Tuesday, March 28, 4:30 p.m., Room A, Parallel Session

2B COMPOUND DEVICES 1

Co-Chairs: Robert S. Okojie, NASA-Glenn Research Center and
Brian J. Skromme, Arizona State University

2B.1 (invited) EFFECTS OF DISLOCATIONS AND STACKING FAULTS ON THE RELIABILITY OF SiC PiN DIODES—R.E. Stahlbush, K.X. Liu, and M.E. Twigg, Office of Naval Research, Washington, D.C.

Compared to silicon, SiC has a larger bandgap, higher breakdown field and higher thermal conductivity making superior power devices possible. A major problem impeding reliable PiN diodes is stacking faults (SF) formation during operation. The origins of the SFs, their electrical effect, and progress to reduce SFs will be discussed.

2B.2 GaN-ON-Si FAILURE MECHANISMS AND RELIABILITY IMPROVEMENTS—S. Singhal, J.C. Roberts, P. Rajagopal, T. Li, A.W. Hanson, B. Therrien, J.W. Johnson, I.C. Kizilyalli, K.J. Linthicum, Nitronex Corp., Raleigh, NC

Highlights of a DC reliability data set are presented and failure analysis is perfomed on degraded devices. The results reveal a permanent Schotkky Barrier Height (SBH) shift. A gate anneal is inserted into the process flow and results show no SBH shift and a dramatic improvement in the large-periphery DC-HTOL results. This is believed to be the first example of a failure analysis effort and subsequent reliability improvement on GaN devices.

2B.3 IMPACT OF AlN INTERLAYER ON RELIABILITY OF AlGaN/GaN HEMTs—R. Coffie, Y. C. Chen, I. Smorchokov, M. Wojtowicz, Y. C. Chou, M. Aumer, Heying, and A. Oki, Northrop Grumman Corp., Redondo Beach, CA

Reliability investigation of AlGaN/GaN HEMTs was performed on a wafer grown by MOCVD on 3 SiC substrates. The POUT degradation strongly depends on AlGaN barrier layer thickness across the wafer.Devices with thicker AlGaN degrade faster than devices with thinner AlGaN. No gate metal diffusion was observed. Furthermore, results from 2-T lifetest show the observed POUT degradation is thermally activated and the higher the channel temperature, the faster the POUT degradation.

Tuesday, March 28, 2:00 p.m., Room B, Parallel Session

2C INTERCONNECT

Co-Chairs: Tony Oates, TSMC and Amit Marathe, AMD

2C.1 VIA PROCESSING EFFECTS ON ELECTROMIGRATION IN 65 nm TECHNOLOGY—K.-D. Lee, Y.-J. Park, T. Kim, and B. Hunter, Texas Instruments, Dallas, TX

We investigate the key factors controlling electromigration (EM) in 65 nm technology node. For UP EM (EM forup-directional electron flow at the cathode via), via barrier coverage strongly affects EM reliability for dual-damascene (DD) interconnects. A critical dimension of upper metal patterns caused a shadow effect for the PVD barrier process, which resulted in non-conformal barrier deposition inside the via and a significant degradation in UP EM reliability. The UP EM reliability has been improved with the enhanced barrier coverage inside via and optimized for performance with the reduced overall barrier deposition. For DN EM (EM for down-directional electron flow at the cathode), the via bottom interface turns out to be a key factor controlling EM reliability. The early DN EM failures, in which thin void growth along the via bottom interface fails the interconnect in a short time frame, can be due to poor process controls (i.e., excessive via clean) resulting in a fast diffusion path at the interface. In 65 nm node, UP and DN EM have different via processing effects and need optimization for reliability enhancement.

2C.2 IDENTIFICATION AND ANALYSIS OF DOMINANT ELECTROMIGRATION FAILURE MODES IN COPPER/LOWk DUAL DAMASCENE INTERCONNECTS—S.-C. Lee and A.S. Oates, TSMC, Hsinchu, Taiwan

Dual - damascene Cu / low-k interconnects frequently exhibit multiple via electromigration failure modes. Here we show that accurate reliability estimation requires testing methodologies with sensitivity to early failures levels below ~1%. We use multi - link , or via chain, test structures to ensure that failure modes for Cu / low-k that dominate reliability are correctly identified.

2C.3 MINIMUM VOID SIZE AND 3-PARAMETER LOGNORMAL DISTRIBUTIONS FOR EM FAILURES IN Cu INTERCONNECTS—B. Li, C. Christiansen, J. Gill, R. Filippi, T. Sullivan, and E. Yashchin, IBM, Essex Jct., VT

Broad EM failure time distributions were observed in Cu interconnects for various structures without sufficient liner and via redundancy, due to the sensitivity to void size, shape and location. Traditional 2-paramterter lognormal model cannot properly reflect this type of distribution features and results in prohibitively conservative lifetime projection. A 3-parameter lognormal distribution is more appropriate and can produce more accurate lifetime projections.

2C.4 DIRECT MEASUREMENT OF ELECTROMIGRATION INDUCED STRESS IN INTERCONNECT STRUCTURES—C.J. Wilson, A.B. Horsfall, A.G. O'Neill, N.G. Wright, S.J. Bull, University of Newcastle, Newcastle, UK, J.G. Terry and A.J. Walton, Univ. of Edinburgh, Edinburgh, UK,

We demonstrate the first direct experimental measurement of electromigration-induced stress in aluminum interconnects using a series of micro-rotating stress sensors. These initial results show a compressive stress gradient along the line, corresponding with that predicted by conventional mass transport theory. The technique is scalable to the end of the ITRS roadmap.

2C.5 IN-SITU FORMATION OF A COPPER SILICIDE CAP FOR TDDB AND ELECTROMIGRATION IMPROVEMENT—K. Chattopadhyay, B. van Schravendijk, T.W. Mountsier, G.B. Alers, M. Hornbeck, H.J. Wu, R. Shaviv, G.Harm, D. Vitkavage, E. Apen, Y. Yu, and R. Havemann, Novellus Systems, San Jose, CA

Self-aligned barrier processes are being investigated as an alternative to standard dielectric barrier processes for the 65 nm technology nodes and beyond. Variations in the dielectric barrier process can modulate the copper-dielectric interface and the SiC / low k interface to improve dielectric and electromigration reliability. For the first time in this paper we will show that optimization of both the self aligned barrier and the SiC film can improve the adhesion between both the Cu and the dielectric layer on top resulting in a 10-1000x increase in time-dependent dielectric breakdown lifetime. Surface analysis of the interfacial layer also suggests formation of a thin copper silicide layer.

2C.6 OXIDATION OF Ta DIFFUSION BARRIER AND ITS EFFECT ON THE RELIABILITY OF Cu INTERCONNECTS—W.-C. Baek, J.P. Zhou, J. Im, P.S. Ho, UT Austin, Austin, TX

Oxidation of Ta diffusion barrier and its possible effect on the structural integrity and reliability of Cu interconnects was studied. The oxidation of Ta barrier, especially at via bottom, can increase the resistance of via-chain test structures during high temperature storage test. Ta barrier oxidation at via sidewall can weaken barrier properties, causing Cu out-diffusion and degrading via-to-line BTS behaviors

Tuesday, March 28, 2:00 p.m., Room C, Parallel Session

2D ESD/LATCHUP

Co-Chairs: Kiran Chatty, IBM and
Christian Russ, Infineon Technologies

2D.1 ESD MM FAILURES RESULTING FROM TRANSIENT REVERSE CURRENTS—J. Whitfield, C. Gill, J. Yang, H. Xu, C. Zhan, B. Baumert, and M. Zunino, Freescale Semiconductor, Tempe, AZ

We report on Machine Model (MM) failures resulting from transient reverse current. The MM waveform oscillates between positive and negative voltage, causing reverse recovery current and current crowding failure on diode fingers. The unipolar nature of TLP measurement and HBM cannot capture this failure mechanism.

2D.2 EXPERIMENTAL EVALUATION AND DEVICE SIMULATION OF DEVICE STRUCTURE INFLUENCES ON LATCHUP IMMUNITY IN HIGH-VOLTAGE 40-V CMOS PROCESS—S.-F. Hsu, M.-D. Ker, G.-L. Lin, and Y.-N. Jou, National Chiao-Tung Univ., Hsinchu, Taiwan

The dependencies of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been investigated with silicon test chips and verified with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be easily applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-µm 40-V CMOS

2D.3 INVESTIGATION OF EXTERNAL LATCHUP ROBUSTNESS OF DUAL AND TRIPLE WELL DESIGNS IN 65 nm BULK CMOS TECHNOLOGY—D. Kontos, K. Domanski*, R. Gauthier, K. Chatty, M. Muhammad, C. Seguin, R. Halbach, C. Russ*, D. Alvarez*, IBM, Essex Jct., VT         *Infineon Technologies, Munich, Germany

The effect of design parameters on the robustness of internal and external latchup structures was investigated. Dual well internal latchup structures demonstrated higher triggering current than triple well ones for overshoot test while the trend was reversed for undershoot test. Evaluation of external latchup showed worst case to be for triple well structures under negative-mode test.

2D.4 THE INFLUENCE OF A NOVEL CONTACTED POLYSILICON-FILLED DEEP TRENCH (DT) BIASED STRUCTURE AND ITS VOLTAGE BIAS STATE ON CMOS LATCHUP—S.H. Voldman, IBM, Essex Jct., VT

A novel contacted polysilicon-filled deep trench structure is constructed which allows independent biasing of the typically floating-poly deep trench structure. The paper will describe the issue of the deep trench structure with the floating polysilicon.

2D.5 OPTIMIZATION AND ELIMINATION OF PARASITIC LATCHUP IN ADVANCED SMART POWER TECHNOLOGIES—R. Zhu, V. Khemka, A. Bose, and T. Roggenbauer, Freescale Semiconductor, Tempe, AZ

This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 µm smart power technology. The impact of logic ground isolation from the substrate and the presence of P+ and N+ buried layers below the logic wells is quantified.

2D.6 STUDY OF DESIGN FACTORS AFFECTING TURN-ON TIME OF SILICON CONTROLLED RECTIFIERS (SCRs) IN 90 nm AND 65 nm BULK CMOS TECHNOLOGIES—J. Di Sarro, K. Chatty*, R. Gauthier*, and E. Rosenbaum, Univ. of Illinois, Urbana-Champaign, IL          *IBM, Essex Jct., VT,

In this work, we explore the effect of design factors on the turn-on time of SCRs in 90nm and 65nm bulk CMOS technologies. We show that an SCR in 65nm technology with an anode (P+) to cathode (N+) spacing of 0.30µm can achieve a turn-on time of 500ps with proper design.

Wednesday, March 29, 8:00 a.m., Room A, Parallel Session

3A HIGH k 1

Co-Chairs: Ajit Shanware, Texas Instruments and
Gennadi Bersuker, Sematech

3A.1 DETECTION OF ELECTRON TRAP GENERATION DUE TO CONSTANT VOLTAGE STRESS ON HIGH-k GATE STACKS—C.D. Young, S. Nadkarni, D. Heh, H.R. Harris, R. Choi, J.J. Peterson, J.H. Sim, S.A. Krishnan, J. Barnett,E. Vogel, B.H. Lee, P. Zeitzoff, G.A. Brown, and G. Bersuker, SEMATECH, Austin, TX

Constant voltage stress (CVS) combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO₂/HfO₂/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-? gate stacks occurs primarily within the interfacial SiO₂ layer (IL) on the as-grown precursor defects most likely caused by the overlaying HfO₂ layer. These results point to the IL as a major focus for reliability improvement of high-k

3A.2 LARGE-SCALE TIME CHARACTERIZATION AND ANALYSIS OF PBTI IN HfO₂/METAL GATE STACKS—J. Mitard^(1,2), X. Garros⁽²⁾, L.P. Nguyen^(1,2), C. Leroux⁽²⁾, G. Ghibaudo⁽³⁾, F. Martin⁽²⁾, and G. Reimbold^{(2)         (1)}STMicroelectronics, Crolles, France;          ⁽²⁾CEA-LETI/D2NT, Grenoble, France;          ⁽³⁾IMEP, Grenoble, France

Positive Bias Temperature Instabilities are investigated with a time resolved measurement technique in HfO₂/metal gate stacks. This technique allows us to evidence and quantify mechanisms, namely fast and slow traps, newly stress-generated slow traps and positive charges. We explain how to take into account these mechanisms for an accurate lifetime extrapolation.

3A.3 INTRINSIC THRESHOLD VOLTAGE INSTABILITY OF THE HfO₂ NMOS TRANSISTORS—G. Bersuker, J. Sim, C.S. Park, C. Young, S. Nadkarni, R. Choi, and B.H. Lee, Sematech, Austin, TX

Threshold voltage instability in the HfO₂ NMOS transistors was studied using CVS and pulsed IV measurements at low temperatures. The proposed model suggests that the electron trapping occurs via two processes: fast process of the resonant tunneling of the injected electron into the pre-existing defects, and much slower process of the temperature-activated migration of the trapped electron to the unoccupied traps. The extracted characteristics of the traps are consistent with those of the oxygen vacancies in the monoclinic hafnia.

3A.4 DETERMINATION OF TIME TO BREAKDOWN OF 0.8-1.2 nm EOT HfSiON GATE DIELECTRICS WITH POLY-Si AND METAL GATE ELECTRODES—S. Inumiya, K. Torii, and Y. Nara, Semiconductor Leading Edge Technologies, Tsukuba, Japan

The abrupt jump in Ig under positive bias stress for ultra-thin HfSiON was hardly observed, whereas abrupt jumps in Ig under negative stress voltage were easily observed by using small area devices. Instead of Ig, we could determine the Tbd by the abrupt jump in Isub under positive bias in carrier separation measurement using nMOS.

3A.5 MECHANISM OF GRADUAL INCREASE OF GATE CURRENT IN HIGH-k GATE DIELECTRICS AND ITS APPLICATION TO RELIABILITY ASSESSMENT—K. Okada, T. Horikawa⁽¹⁾, H. Satake, H. Ota⁽¹⁾, A. Ogawa, T. Nabatame, and A. Toriumi^(1,2), MIRAI-ASET, Tsukuba, Japan         ⁽¹⁾MIRAI-ASRC-AIST, Tsukuba, Japan;         ⁽²⁾Univ. of Tokyo, Tokyo, Japan

Mechanism of the `gradual increase' of gate current which makes it difficult to detect the breakdown in EOT-scaled high-k gate dielectrics has been clarified to be multiple occurrence of soft breakdown. Based on this mechanism, new reliability assessment method without the experimental detection of the 1st breakdown has been proposed.

3A.6 IMPACT OF CRYSTALLINE PHASE OF NI-FULL-SILICIDE GATE ELECTRODE ON TDDB RELIABILITY OF HFSION GATE STACKS.—T. Onizawa, M. Terai, A. Toda, M. Oshida, N. Ikarashi, T. Hase, S. Fujieda, and H. Watanabe, NEC, Sagamihara, Japan

We investigated the TDDB reliability of phase-controlled Ni-full-silicide/HfSiON n-FETs. The reliability of the NiSi-electrode n-FETs was comparable to that of poly-Si-electrode FETs. However, the reliability of the Ni3Si-electrode FETs was degraded, which we relate to a higher strain, not to Ni diffusion.

3A.7 DECOUPLING OF COLD CARRIER EFFECTS IN HOT CARRIER RELIABILITY OF HfO₂ GATED NMOSFETS—H. Park^(1,3), R. Choi⁽²⁾, S.C. Song⁽²⁾, M. Chang⁽¹⁾, C.D. Young⁽²⁾, G. Bersuker⁽²⁾, B.H. Lee⁽²⁾, J.C. Lee⁽³⁾, and H. Hwang⁽¹⁾         (1)Gwangju Institute of Science & Technology, Gwangju, Korea;         (2)SEMATECH, Austin, TX;          (3)Univ. of Texas at Austin, Austin, TX

To understand hot carrier effects on high-k dielectrics without cold carrier trapping, we have investigated hot carrier induced damage with channel and substrate hot carrier stresses. Comparing substrate hot carrier stress, channel hot carrier stress showed significant cold carrier injection during hot carrier injection. Using a relaxation bias, we are able to evaluate hot carrier induced permanent trap generation by decoupling cold carrier trapping.

Wednesday, March 29, 8:00 a.m., Room B, Parallel Session

3B SER

Co-Chairs: Ron Lacoe, the Aerospace Corp. and
Paul Dodd, Sandia National Labs

3B.1 A COMPARATIVE STUDY ON THE SOFT-ERROR RATE OF FLIP-FLOPS FROM 90-nm PRODUCTION LIBRARIES—T. Heijmen, P. Roche, G. Gasiot, and K.R. Forbes, Philips Research Labs, AE Eindhoven, The Netherlands

Experimental alpha- and neutron-induced SER data of five flip-flops from 90-nm standard-cell libraries are presented. Dependencies on cell type, data and clock state, and voltage are discussed. In general, alpha-SER shows a strong VDD-saturation and exceeds neutron-SER. Model simulations demonstrate the impact of process variations.

3B.2 INVESTIGATION OF THERMAL NEUTRON INDUCED SOFT ERROR RATES IN COMMERCIAL SRAMs WITH 0.35 µm TO 90 nm TECHNOLOGIES—M. Olmos, R. Gaillard, R. Gahler, A. Hillenbach, J. Beaucour, S.J. Wen, and S. Chung, iRoC Technologies, Grenoble, France

Measurement of soft error rates (SER) of ten commercial SRAMs of 0.35 µm to 90 nm technologies have been completed at the ILL thermal neutron facility. Results establish the sensitivity of old and recent SRAMs showing the impact of 10B concentrations in BPSG and p-type regions. 10B results are also compared to high-energy neutron SER.

3B.3 RADIATION-INDUCED SOFT ERROR RATES OF ADVANCED CMOS BULK DEVICES—N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra, and J. Maiz, Intel, Hillsboro, OR

We are reporting on radiation-induced failure rates of advanced CMOS bulk devices. Specifically we investigated the SER trend of SRAM devices, sequentials and combinational logic. Our data show that whereas the SRAM SER has been decreasing, the logic SER trends are nearly flat and multi-bit SER has been increasing steeply.

3B.4 IMPROVING FPGA DESIGN ROBUSTNESS WITH PARTIAL TMR—B. Pratt, M. Caffrey*, P. Graham*, K. Morgan, M. Wirthlin, Brigham Young Univ., Provo, UT          *Los Alamos National Labs, Los Alamos, NM,

This paper describes an efficient approach of applying mitigation to an FPGA design to protect against Single Event Upsets (SEUs). This approach applies mitigation selectively to FPGA circuit structures depending on the importance of structure within the design. A software tool is also introduced which automatically classifies circuit structures based on this concept and applies Triple Modular Redundancy (TMR) selectively based on the classification of the circuit structure.

Wednesday, March 29, 10:05 a.m., Room B, Parallel Session

3C ASSEMBLY & PACKAGING

Co-Chairs: Shekhar Khandekar, PMC-Sierra and Sidarth, AMD

3C.1 GOLD-ALUMINUM INTERMETALLIC FORMATION KINETICS—R.C. Blish, II, AMD, Sunnyvale, CA, S. Li, H. Kinoshita & S. Morgan, Spansion, Inc., Sunnyvale, CA

Al-rich InterMetallic Compounds (IMC) grow laterally with an activation energy of 1.0 eV while Au-rich phases beneath the ball show an activation energy and lifetime which is a strong function of wire composition. We find the Au₄Cu_xAl_1-x phase (x < 1) on both sides of the failing interface.

3C.2 GEOMETRY EFFECTS ON THE ELECTROMIGRATION OF EUTECTIC Sn/Pb FLIP-CHIP SOLDER BUMPS—D. Eaton, J. Rowatt, and W. Dauksher, Avago Technologies, Fort Collins, CO

We investigated geometrical effects on the electromigration of eutectic Sn/Pb solder bumps. Two passivation opening and two UBM diameters were tested. The t50 values depend only slightly on passivation opening diameter but greatly on UBM diameter, consistent with a model that voiding begins directly beneath the passivation opening and progresses outward.

3C.3 KINETIC ANALYSIS OF CURRENT ENHANCED INTERMETALLIC GROWTH AND ITS EFFECT ON ELECTROMIGRATION RELIABILITY FOR SOLDER JOINTS—H.-L. Chao, S.-H. Chae, X. Zhang, M. Ding, K.-H. Lu, J. Im, and P.S. Ho, UT Austin, Austin TX

A kinetic analysis was formulated for electromigration induced intermetallics evolution of a Cu-Sn diffusion couple. Simulation results are consistent with experimental data in time dependency of intermetallic growth. This leads to high concentration of vacancy accumulation and formation of Kirkendall voids at Cu₆Sn₅ side of the Cu₃Sn/CuSn₅ interface. Solder failure due to crack growth driven by void formation together with local stresses induced by intermetallics is discussed.

3C.4 A PTH RELIABILITY MODEL CONSIDERING MULTIPLE PTHs IN A PWB AND THEIR STRESS DISTRIBUTIONS ALONG PTH BARRELS—J. Xie and R. Kang, BUAA, Beijing, China

A model that considers stress distributions along PTH barrels and multiple PTHs is developed. It verifies the maximum stress location of PTHs at barrels' middle sections, which agrees with FEM and experimental results. The model also provides an explanation on the strain distribution factor used in the existing IPC methodology.

3C.5 X-RAY INSPECTION-INDUCED LATENT DAMAGE IN DRAM—A. Ditali, M. Ma, M. Johnston, Micron Technology, Inc., Boise, ID

DRAM subjected to X-ray inspection may incur latent damage. Though dose levels in X-ray inspection systems are considered inconsequential for device failure, the degree of latent damage must be carefully considered. This paper discusses X-ray inspection system induced vulnerabilities of DRAMs. We propose a procedure for attenuating X-ray radiation levels while preserving good quality images.

Wednesday, March 29, 8:00 a.m., Room C, Parallel Session

3D PRODUCTS & CIRCUITS 1

Co-Chairs: Robert Kwasnick, Intel and
Yuan Chen, JPL

3D.1 SRAM OPERATIONAL VOLTAGE SHIFTS IN THE PRESENCE OF GATE OXIDE DEFECTS IN 90 nm SOI—V. Ramadurai, N. Rohrer, and C. Gonzalez, IBM, Essex Jct., VT

In this paper the effect of gate oxide breakdown on the voltage response (VDD_MIN) of a 6-T SRAM cell has been studied. A new cell reliability model was developed to explain both monotonic and non-monotonic operational voltage shifts through product reliability stress.

3D.2 IMPACT OF NBTI INDUCED STATISTICAL VARIATION TO SRAM CELL STABILITY—G. La Rosa, W.L. Ng*, S. Rauch, R. Wong, J. Sudijono*, IBM Semiconductor Research and Development Center, East Fishkill, NY         *Chartered Semiconductors, East Fishkill, NY

This work investigates the impact of NBTI on the SRAM cell stability. A correlation between the NBTI degradation of the pull up transistors and the corresponding SRAM I_CRIT shift is established and its relation to SNM quantified. We propose, for the first time, a methodology to define an NBTI target directly related to the SRAM cell stability and its dependence on SRAM design and the adopted CMOS technology as well as an acceptable EOL failure count. It is found that a more appropriate SRAM stability sensitive pMOSFET NBTI Vt_SAT target cannot be limited to the Vt_SAT mean shift, but needs as well a quantification of the allowed variance and initial SRAM I_CRIT distribution.

3D.3 OXIDE BREAKDOWN AFTER RF STRESS: EXPERIMENTAL ANALYSIS AND EFFECTS ON POWER AMPLIFIER OPERATION—L. Larcher, D. Sanzogni*, R. Brama, A. Mazzanti, and F. Svelto*, Univ. di Modena e Reggio Emilia, Reggio Emilia, Italy          *Università di Pavia, Pavia, Italy

This paper investigates oxide breakdown under RF stress by using a power amplifier for experiments. We show that RF voltage peaks for safe device operation are much larger than DC limits, and that oxide degradation physics is triggered by the rms value of oxide field, and not by its maximum.

3D.4 LIFETIME ENHANCEMENT UNDER HIGH FREQUENCY NBTI MEASURED ON RING OSCILLATORS—T. Nigam* and E.B. Harris, Agere Systems, Santa Clara, CA          *Currently at Cypress Semiconductor, San Jose, CA

Circuit level degradation is studied using ring oscillators operating at frequencies up to 3GHz. The NBTI lifetime is enhanced by four decades as compared to DC stress. Therefore, the reliability margins available to designers are significantly higher than previously accepted for circuits with high activity ratios.

Wednesday, March 29, 10:05 a.m., Room C, Parallel Session

3E PRODUCTS & CIRCUITS 2

Co-Chairs: Vijay Reddy, Texas Instruments and
Joey Bernstein, Univ. of Maryland

3E.1 (invited) FIELD DEGRADATION OF MEMORY COMPONENTS DUE TO HOT CARRIERS—W. Bornstein, R. Dunn, and T. Spielberg, IBM, Hopewell Jct., NY

Over the past three years we experienced two independent component field incidents due to hot carriers on procured memory devices. We report root cause failure analysis, stresses performed, failure modeling, and pertinent application conditions. We will show how application voltages and duty cycle play a critical role in hot carrier degradation.

3E.2 AMBIENT USE-CONDITION MODELS FOR RELIABILITY ASSESSMENT—C. Gu, R.F. Kwasnick, N.R. Mielke, E.M. Monroe, and C.G Shirley, Intel, Santa Clara, CA

This paper provides a model formulation and method for computing the acceleration factor (AF) for realistic time-varying temperature and temperature/humidity ambients. We derive specific models of ambients (outdoor, indoor, and inside a vehicle) in terms of this formulation based on NOAA data and usage studies.

3E.3 APPROACH TO EXTRAPOLATING RELIABILITY OF CIRCUITS OPERATING IN A VARYING AND LOW TEMPERATURE RANGE—Y. Chen, M. Mojaradi, JPL, Pasadena CA, L. Westergard, C. Billman, AMI, Pocatello, ID, S. Cozy, T. Johnson, and E. Kolawa, JPL, Pasadena CA,

We present an approach to extrapolating circuit reliability to use conditions with a varying and low temperature range. The approach integrates the impact of the statistical nature of transistor lifetime on circuit reliability to give a more realistic circuit reliability projection. Even though the approach is demonstrated for low temperature applications by focusing on hot carrier aging failure mechanism, it can be applied and easily extended to other failure mechanisms for any varying temperature operating conditions.

3E.4 (invited) FLASH MEMORY FIELD FAILURE MECHANISMS—P. Muroke, Nokia, Finland

This paper presents a study of Flash memory field failures encountered in Mobile Phone applications. Summary of failure analyses carried out by the Flash manufacturers over past four years is given. Failure mechanism distributions are presented followed by discussion of EFR control, monitoring and improvement areas.

Wednesday, March 29, 2:00 p.m., Room A, Parallel Session

4A HIGH k 2

Co-Chairs: Ajit Shanware, Texas Instruments and
Gennadi Bersuker, Sematech

4A.1 IMPACT OF NITROGEN INCORPORATION IN SiO_x/HfSiO GATE STACKS ON NEGATIVE BIAS TEMPERATURE INSTABILITY—M. Aoulaiche, M. Houssa, T. Conard, G. Groeseneken, S. De Gendt, and M.M. Heyns, IMEC, Leuven,

The impact of nitrogen incorporation in SiOx/HfSiO/TaN stacks on NBTI is investigated. Nitrided stacks (in NH₃ or by decoupled plasma nitridation) show much more NBTI degradation compared to non-nitrided stacks. The additional degradation is shown to mainly arise from slow states generation, resulting most likely from hole trapping at nitrogen-related defects. Gate stacks without nitrogen incorporation are predicted to reach 10 years lifetime at operating voltage, unlike the nitrided-stacks.

4A.2 IMPACT OF NITROGEN ON PBTI CHARACTERISTICS OF HfSiON/TiN GATE STACKS—S.A. Krishnan, M. Quevedo, H.-J. Li, P. Kirsch, R. Choi, C. Young, J.J. Peterson, B.H. Lee, G. Bersuker, and J.C. Lee, SEMATECH, Austin, TX

Impact of nitrogen on charge trapping induced PBTI characteristics in HfSiON/TiN gate stacks is investigated. While thickness is found to be the primary knob to reduce charge trapping, plasma nitrogen reduces PBTI effects in thick (2.7 nm) HfSiON films. The thin films (1.8 nm) show significantly lower V_TH shift than the thick films and seem to be insensitive to N content. Thermal nitridation exacerbates PBTI effects, in comparison with plasma nitridation.

Wednesday, March 29, 2:50 p.m., Room A, Parallel Session

4B HIGH VOLTAGE DEVICE

Co-Chairs: Peter Moens, AMI Semiconductor and
S Pendharker, Texas Instruments

4B.1 SUBSTRATE CURRENT INDEPENDENT HOT CARRIER DEGRADATION IN NLDMOS DEVICES—D. Brisbin, P. Lindorfer, P. Chaparala, National Semiconductor, Santa Clara, CA

This paper presents anomalous hot carrier degradation results obtained from high voltage (20V) lateral DMOS device whose drain drift implant dose was varied. The first anomalous result was that changes in the drain drift implant dose had no apparent impact on linear drain resistance hot carrier results, though, maximum substrate current increased by over three times. The second result is that at low gate stress bias conditions hole trapping was observed leading to an increase in measured drain current rather than expected degradation. Charge pumping and simulation results are presented to explain the hot carrier degradation mechanisms.

4B.2 INVESTIGATION OF HOT CARRIER DEGRADATION MODES IN LDMOS BY USING A NOVEL THREE-REGION CHARGE PUMPING TECHNIQUE—C.C. Cheng, K.C. Du, T. Wang, National Chiao-Tung Univ., Hsin-Chu, Taiwan, T.H. Hsieh, J.T. Tzeng, Y.C. Jong, R.S. Liou, S.C. Pan, and S.L. Hsu, TSMC, Hsin-Chu, Taiwan

Hot carrier induced oxide degradation in n-LDMOS is investigated by using a three-region charge pumping technique. This technique allows us to locate oxide damage area in various stress modes and gain insight into trap creation properties. Our characterization shows that max. I_g stress causes the largest drain current and subthreshold slope degradation because of both interface trap (N_it) generation in the channel region and bulk oxide charge (Q_ox) creation in the bird's beak region. The charge pumping result is confirmed by numerical device simulation.

4B.3 (invited) HOT CARRIER DEGRADATION IN A CLASS OF RADIO FREQUENCY n-CHANNEL LDMOS TRANSISTORS—S. Manzini, STMicroelectronics, Cornaredo, Italy

The hot carrier degradation of a class of n-channel LDMOS transistors, designed for a radio frequency power amplifier, is investigated. A static degradation model is developed and extended to any dynamic (periodic) stress. Experimental data and model predictions show that these devices, operating at unusually high drain voltage, are suitable to the specific application.

4B.4 ANALYSIS OF THE BACK-GATE EFFECT ON THE ON-STATE BREAKDOWN VOLTAGE OF SMARTPOWER SOI DEVICES—S. Schwantes, J. Furthaler, B. Schauwecker, F. Dietz, M. Graf, and V. Dudek, Atmel Germany, Heilbronn, Germany

This paper discusses the impact of the back gate bias on the on-state drain breakdown voltage of high-voltage SOI MOSFETs. For the first time an analytical model of the breakdown voltage covering the reasonable back gate voltage range is presented. It is shown that the back gate potential impacts on the breakdown behaviour by modulating the carrier distribution in the drift region, the base transport factor of the parasitic bipolar transistor and the drift region resistance.

4B.5 SNAPBACK BREAKDOWN DYNAMICS AND ESD SUSCEPTIBILITY OF LDMOS—Y. Chung, H. Xu, R. Ida, and B. Baird, Freescale Semiconductor, Tempe, AZ

Snapback breakdown characteristics of RESURF LDMOS devices are of extreme dV/dt dynamics and highly localized. The local active region absorbs the snapback induced discharge current. As the discharge current is proportional to the gate width, the larger LDMOS can be greatly susceptible to the first snapback breakdown during ESD stress.

4B.6 SUBSTRATE MAJORITY CARRIER INDUCED NLDMOS FAILURE AND ITS PREVENTION IN ADVANCED SMART POWER TECHNOLOGIES—R. Zhu, V. Khemka, A. Bose, and T. Roggenbauer, Freescale Semiconductor, Tempe, AZ

This paper provides in-depth discussions on majority carrier conduction induced high voltage NLDMOS failure in advanced smart power technologies. Techniques to suppress and eliminate the majority carrier current have been provided. Trade-off between the majority current conduction, NLDMOS device area and SOA has also been discussed.

Wednesday, March 29, 2:00 p.m., Room B, Parallel Session

4C PROCESS INTEGRATION RELIABILITY

Co-Chairs: Jeff Peterson, Intel/Sematech and
Kin P. Cheung, Rutgers University

4C.1 (invited) ADVANCED PLASMA AND ADVANCED GATE DIELECTRIC - A CHARGING DAMAGE PRESPECTIVE—K.P. Cheung, Rutgers Univ., Piscataway, NJ

Advanced plasma systems used in modern IC processing are so well engineered that when charging damage occurs, it rarely reach the extreme level that produce oxide breakdown. Wear-out of advanced gate dielectric, which is the main concern of charging damage, is also extremely difficult to quantify. This paper explore the issues unique to this combination.

4C.2 ON THE RECOVERY OF SIMULATED PLASMA PROCESS INDUCED DAMAGE IN HIGH-k DIELECTRICS—B. O'Sullivan*, L. Pantisano, P. Roussel, R. Degraeve, G. Groeseneken*, S. DeGendt, M. Heyns, IMEC, Leuven, Belgium          *also with Katholieke Univ., Leuven, Belgium

This work presents a detailed analysis of the ability of high-k materials to recover from plasma damage, as simulated by Fowler-Nordheim stress, by forming gas and high temperature RTA annealing. The annealing response of HfSiON and HfO₂ is correlated with structural differences, trap generation rate, centroids and defect de-passivation. We show that plasma damage can be successfully recovered for HfO₂ by high temperature annealing.

4C.3 ULTRA-THIN GATE DIELECTRIC PLASMA CHARGING DAMAGE IN SOI TECHNOLOGY—W. Lai, D. Harmon, T. Hook, IBM, Essex Jct., VT, V. Ontalus, IBM, Hopewell Jct., NY, and J. Gambino, IBM, Essex Jct., VT

The charging damage to SOI devices with 1.1 nm gate oxide is examined. Antennas with various metal areas and spatial separations are attached to the gate and diffusion nodes. Serious damage is observed if the nodes antennas are placed further than ~1000 um apart, even when the antennas are identical.

4C.4 IMPACT OF THIN WSix INSERTION IN TUNGSTEN POLYMETAL GATE ON GATE OXIDE RELIABILITY AND GATE CONTACT RESISTANCE—M.G. Sung, K.-Y. Lim, H.-J. Cho, S.R. Lee, S.-A. Jang, H.-S. Yang, K. Kim, N.-J. Kwak, H.-C. Sohn and J.W. Kim, Hynix Semiconductor, Kyoungki-do, Korea

By inserting thin WSix layer in tungsten poly gate stack we can effectively relieve the hard mask stress, which contribute to the better gate oxide reliability. This insertion also could prevent the formation of Si-N dielectric layer atop of poly-Si, which could lower the contact resistance between poly and tungsten.

4C.5 OXIDE THINNING IN SHALLOW TRENCH ISOLATION—G. Ghidini, R. Bottini, D. Brazzelli, N. Galbiati, I. Mica, A. Morini, A. Pavan, M.L. Polignano, and M.E. Vitali, STMicroelectronics, Agrate Brianza, Italy

Residual stress during STI formation reduces oxidant diffusion causing a not uniform oxide growth on STI edge. This effect increases with time and it is evident for oxide thickness above 7nm for which the oxidation rate is parabolic. Hump effect but also oxide lifetime reduction of HV gate oxides used in Flash memory pump applications is found in correspondence. High temperature diluted steam oxidation allows reducing the impact of stress on oxide growth. For a thick gate oxide the temperature of the diluted steam oxidation should be at least 900ºC for which a reduction of dislocation generation is also found.

4C.6 A NEW FAILURE MECHANISM OF MLC NOR FLASH MEMORY CAUSED BY AGGRAVATED DRAIN DISTURB DUE TO CO-SALICIDATION PROCESS—B.Y. Lee, J.H. Han, J.I. Han, S.-P. Sim, W.H. Kwon, H.K. Lee, Y.M. Park, S.B. Jeon, K.S. Kim, J.H. Kim, W.H. Lee, C.-K. Park, and K. Kim, Samsung Electronics Co., Yongin-City, Korea

We report a new failure mode of multi-level cell (MLC) NOR flash memory induced by anomalously increased drain disturb. The aggravated disturb, occurring in ppm level, is shown to be induced by an abnormal lateral encroachment of cobalt salicide on the drain side of the NOR flash cell. The failure mode, which becomes more critical as the NOR flash cell scales down, can be alleviated by optimizing the thickness of cobalt salicidation and controlling the defect density induced by spacer etch and ion implantation on the drain side.

4C.7 IMPACT OF METAL WET ETCH ON DEVICE CHARACTERISTICS AND RELIABILITY FOR DUAL METAL GATE/HIGH-k CMOS—Z. Zhang, M.M. Hussain, S.H. Bae, S.C. Song, and B.H. Lee, SEMATECH, Austin, TX

This paper presents the impact of metal wet etch on metal gate/high-k device characteristics and reliability. While the metal wet etch slightly degraded the electron mobility, it did not affect hole mobility. It also did not affect fast transient charge trapping, and in fact, improved NBTI and PBTI.

4C.8 RELIABILITY QUALIFICATION OF CoSi₂ ELECTRICAL FUSE FOR 90 nm TECHNOLOGY—C. Tian, B. Park, C. Kothandaraman, J. Safran, D. Kim, N. Robson, and S.S. Iyer IBM, Hopewell Jct., NY

The reliability of CoSi₂/p-poly Si electrical fuse programmed by electromigration for 90nm technology will be presented. Both programmed and unprogrammed fuse elements were shown to be stable through extensive reliability evaluations. A qualification methodology is demonstrated to define an optimized reliable electrical fuse programming window by combining fuse resistance measurements, physical analysis, and functional sensing data. This methodology addresses the impact on electrical fuse reliability caused by process variation and device degradation (e.g., NBTI) in the sensing circuit and allows adequate margin to ensure electrical fuse reliability over the chip lifetime.

Wednesday, March 29, 2:00 p.m., Room C, Parallel Session

4D MEMS

Co-Chairs: Jeremy Walraven, Sandia National Labs and
Cosme Furlong, Worchester Polytechnic Institue

4D.1 (invited) RELIABILITY IN MEMS PACKAGING—T.-R. Hsu, San Jose State Univ., San Jose, CA

Cost effective packaging and robust reliability are two critical factors for successful commercialization of MEMS and microsystems. While packaging contributes to the production cost of these products, reliability addresses consumers' expectations on sustainable performance of the products. There are a number of factors that contribute to the reliability of MEMS and microsystems; packaging, in particular, in bonding and sealing, material characterization relating to operating and environmental conditions, the techniques for mitigating intrinsic stresses/strains induced by fabrications and testing for reliability are a few of these factors. This paper will offer in-depth descriptions of these factors with proposed approaches for improving the reliability

4D.2 RELIABILITY BASED MEMS SYSTEM MODELING AND OPTIMIZATION—N. Liu and S. Manoochehri, Stevens Institute of Technology, Hoboken, NJ

A methodology for reliability-based system modeling, analysis and optimization of micro-electromechanical systems (MEMS) design is presented that accounts for stochastic variations in device geometry parameters and operating conditions. The optimization objective function considers minimization of several uncertainty factors on the overall system performance while satisfying target requirements specified. A probabilistic sufficiency factor approach is proposed in the form of constraints on micro-fabrication processes andmaterials system that combines safety factor and probability of failure. The design problem is decomposed into two analysis systems; uncertainty effects analysis and performance sensitivity analysis. Each analysis system can be partitioned into several subsystems according to the different functions they perform. The entire problem has been treated as a multi-disciplinary design optimization (MDO) for maximum robustness and performance achievement. The probabilistic sufficiency factor approach represents a factor of safety relative to a target probability of failure. It is known that the probabilistic sufficiency factor with a design constrains boundary is much more accurate and reasonable, which accelerates the convergence of reliability-based design optimization. In this study, the analysis results are provided as optimized device geometry parameters governing the resonant frequency and the trans-conductance values for the example of the selectedmicro resonator device.

4D.3 RELIABILITY ISSUES IN RF-MEMS SWITCHES SUBMITTED TO CYCLING AND ESD TEST—A. Tazzoli, V. Peretti, R. Gaddi, A. Gnudi, E. Zanoni, and G. Meneghesso, Univ. of Padova, Padova, Italy

In this work we have carried out an extensive electrical characterization in order to identify the dynamic response of RF-MEMS switches driven in different conditions (bias and actuation time) and we have studied, for the first time to our knowledge, the effects of TLP-ESD events on RF-MEMS switches identifying a very critical ESD sensitivity.

4D.4 STABLE AND RELIABLE Q-FACTOR IN RESONANT MEMS WITH GETTER FILM—A. Conte, M. Moraja, and G. Longoni, SAES Getters S.p.A., Lainate, Italy

One of the most important issues of resonant MEMS is obtaining reliable and stable values of Q-factor which are strongly influenced by the internal pressure of the MEMS packaging. Using patterned getter film, total pressures down to 10-4 mbar with corresponding high and stable Q-factors have been achieved.

4D.5 ELECTRICAL BREAKDOWN RESPONSE FOR MULTIPLE-GAP MEMS STRUCTURES—F.W. Strong^(1,2), J.L. Skinner⁽²⁾, A.A. Talin⁽²⁾, P.M. Dentinger⁽²⁾, and N.C. Tien^{(1)          (1)}Univ. of California, Davis, CA;          ⁽²⁾Sandia National Labs, Livermore, CA,

We compare electrical breakdown tests of planar MEMS devices with ANSYS® simulations to show how dividing the electric field strength between multiple air gaps affects the maximum holdoff voltage, and allows switching of high voltages using only the short actuation distances of MEMS microswitches.

Wednesday, March 29, 4:30 p.m., Room C, Parallel Session

4E MEMORY 1

Co-Chairs: Alessandro Spinelli, Politecnico di Milano and
Hanmant Belgal, Intel

4E.1 RELIABILITY PREDICTION OF DIRECT TUNNELING RAM WITH SiON AND HfSiON TUNNEL DIELECTRICS BASED ON TRANSISTOR LEAKAGE CURRENT MEASUREMENTS—R. Degraeve⁽¹⁾, B. Govoreanu⁽¹⁾, D. Wellekens⁽¹⁾, M. Rosmeulen⁽¹⁾, T. Kauerauf^(1,2), J. Van Houdt⁽¹⁾, G. Groeseneken^{(1,2)          (1)}IMEC, Leuven, Belgium;          ⁽²⁾Catholic Univ. Leuven, Leuven, Belgium

The reliability of Direct-Tunneling RAM, its statistics and dependence on degradation conditions and area are determined based on a detailed analysis of leakage path generation in small transistors with SiON and SiON/HfSiON as tunnel dielectric. We show that DTRAM has on the average sufficient reliability, but the distribution of retention times is very wide. Medium-k HfSiON as tunnel dielectric enhances reliability performance, making this dielectric better suited for DTRAM applications.

4E.2 ANALYSIS OF THERMAL VARIATION OF DRAM RETENTION TIME—M.H. Cho, Y.I. Kim, D.S. Woo, S.W. Kim, M.S. Shim, Y.J. Park, W.S. Lee, and B.I. Ryu, Samsung Electronics, Hwasung-City, Korea

Variation of DRAM retention time induced by thermal stress was investigated. Thermal activation energies of subthreshold leakage, junction leakage and GIDL current were compared with that of 1/tREF for a thermally degraded DRAM cell. Variable retention time may depend on the variation of GIDL current.

4E.3 RESISTANCE DRIFT OF ALUMINUM OXIDE MAGNETIC TUNNEL JUNCTION DEVICES—P. Ku and Y. Chung, Freescale Semiconductor, Tempe, AZ

This paper reports a systematic study on the MTJ drift and recovery characteristics. It is shown that during stress, the MTJ device resistance decreases and after stress, large degree of the drift is relaxed to its pre-stress conditions but some permanent changes are also noticed, which implies both elastic and inelastic process involved. Multiple types of traps in the system is proposed to explain the elastic and inelastic processes observed.

Posters By Topic Section

Wednesday, March 29, 7:00 p.m., Computer History Museum

AP ASSEMBLY & PACKAGING

Co-Chairs: Shekhar Khandekar and Sidarth, AMD

AP01 UNDERSTANDING MECHANISM OF FILM ATTACH MATERIAL VOID FORMATION IN ELECTRONIC PACKAGES—A. Labiano, Intel Technology Philippines, Cavite, Philippines

This paper presents an understanding of void formation in film attach materials resulting from the interaction with the process parameters during package assembly. This study comprehends the experiments done to determine the contributing factors to void formation and was useful in the assessment of new materials for new generation packages.

AP02 HI/REL DOUBLE SIDED PACKAGE FOR Si/SiC POWER MODULE—B. Borowy, L. Casey, and G. Davis, SatCon Technology, Boston, MA and J. Connell, Advanced Thermal Technologies, Waltham, MA

In this paper we present the design, and preliminary results, of a new hi-rel package for a hybrid Si/SiC power device package with minimal mechanical and electrical parasitics and contrast this new packaging technology with conventional COTS power device packaging using Insulated Metal Substrates (IMS), conventional wire bonds and lug terminations.

Wednesday, March 29, 7:00 p.m., Computer History Museum

CD COMPOUND DEVICES

Co-Chairs: Robert S. Okojie, NASA-Glenn Research Center and
Brian J. Skromme, Arizona State University

CD01 HIGH BRIGHTNESS InGaN LEDs DEGRADATION AT HIGH INJECTION CURRENT BIAS—S. Levada, M. Meneghini, E. Zanoni, S. Buso, G. Spiazzi, S. Podda*, G. Mura*, M. Vanzi*, and G. Meneghesso, Univ. of Padova, Padova, Italy          *Univ. of Cagliari, Cagliari, Italy

The effects of the high current and high temperature stress conditions on high brightness Indium-Gallium Nitride LEDs have been studied. Constant and pulsed bias was investigated over devices with and without heat sink to identify the influence of the self-heating and the current flow on devices reliability. Several degradation modes have been identified such as increase of reverse and generation/recombination current, increase of the series resistance, decrease of the optical emitted power.

Wednesday, March 29, 7:00 p.m., Computer History Museum

DI DIELECTRICS

Co-Chairs: Ben Kaczer, IMEC and
Tanya Nigam, Cypress Semiconductor

DI01 COMPREHENSIVE THICKNESS-DEPENDENT POWER-LAW OF BREAKDOWN IN CMOS GATE OXIDES—A. Hiraiwa and D. Ishikawa, Hitachi, Ltd., Tokyo, Japan

The voltage acceleration of breakdown lifetime follows the power law irrespective of the MOS-type and voltage polarity. The exponent of all the cases decreases when the thickness is reduced. The exponent of NMOS under inversion is much larger than the others and suggests hole-involvement in the breakdown.

DI02 EFFECTS OF NANO-SCALE SCHOTTKY BARRIER OF CONDUCTOR-LIKE BREAKDOWN PATH ON PROGRESSIVE BREAKDOWN IN MOSFET—V.L. Lo, K.L. Pey, C.H. Tung*, and D.S. Ang, Nanyang Technological Univ., Singapore          *Institute of Microelectronics, Singapore,

Nano-scale Schottky barrier associated with a conductor-like breakdown (BD) path in gate dielectric is characterized. The Schottky barrier governs the leakage current conduction during normal operations, in which the growth of the BD path will be significantly slowed down at nominal operating voltages, leading to a longer progressive BD reliability.

DI03 NEW EXTENSIVE MVHR BREAKDOWN MODELS FOR ULTRA-THIN GATE OXIDE—G. Ribes^(1,3), S. Bruyere⁽¹⁾, D. Roy⁽¹⁾, M. Denais⁽¹⁾, J-M. Roux⁽¹⁾, C. Parthasarathy⁽¹⁾, V. Huard⁽²⁾, and G. Ghibaudo⁽³⁾,          ⁽¹⁾STMicroelectronics, Crolles, France;          ⁽²⁾Philips, Crolles, France;          ⁽³⁾IMEP/ENSERG, Grenoble, France

We propose a new breakdown model called Multi-Vibrational Hydrogen Release applicable to advancedgate dielectrics. For the first time, polarization, gate bias, temperature, and oxide thickness effects are well explained by a unique model. In addition the model predicts some process related effects such as poly doping and breakdown of high-k dielectrics.

DI04 BREAKDOWN VOLTAGE PREDICTION OF ULTRA-THIN GATE INSULATOR IN ELECTROSTATIC DISCHARGE (ESD) BASED ON ANODE HOLE INJECTION MODEL—A. Kinoshita, Y. Mitani, K. Matsuzawa, H. Kawashima, C. Sutoh, J. Kurihara, T. Hiraoka, I. Hirano, M. Muta, M. Takayanagi, and N. Shigyo, Toshiba, Yokohama, Japan

A prediction model for the breakdown voltage of ultra-thin gate insulator in electrostatic discharge (ESD) is proposed. The time-dependent-dielectric-breakdown characteristics under DC stress suc-cessfully predicts ESD oriented dielectric breakdown on the basis of the anode hole injection model. The proposed model redistributes experimental breakdown voltages and number of pulses to break-down in extensive gate voltages and gate insulator thicknesses. In conclusion, the present model is quite effective for the prediction of ESD reliability in highly scaled ULSI devices.

DI05 ACCURATE CHARACTERIZATION ON INTRINSIC GATE OXIDE RELIABILITY USING VOLTAGE RAMP TESTS—S.C. Fan, J.-C. Lin, and A.S. Oates, TSMC, Hsinchu, Taiwan

The key parameters for oxide reliability estimates, such as voltage acceleration factor, area scaling factor, and temperature dependence were extracted from ramp-voltage VBD tests. For ramp voltage tests on oxides with thickness from 1.6 to 28 nm, the voltage acceleration factors and the area scaling factors are consistent with the anode hole injection and the percolation models. The correlation between ramp-voltage VBD tests and constant voltage TDDB was established.

DI06 CHARGE PUMPING AT RADIO FREQUENCIES: METHOHDOLOGY, TRAP RESPONSE AND APPLICATION—G.T. Sasse and J. Schmitz, Univ. of Twente, AE Enschede, The Netherlands

In this paper the RF charge pump technique is discussed. It is explained how RF charge pump measurements are performed accurately and a physical model for the trap response at radio frequencies is given. The merits of the technique for extracting the interface state density on leaky dielectrics are discussed.

Wednesday, March 29, 7:00 p.m., Computer History Museum

ES ESD

Co-Chairs: Kiran Chatty, IBM and
Christian Russ, Infineon Technologies

ES01 THE DYNAMIC CURRENT DISTRIBUTION OF A MULTI-FINGERS GGNMOS UNDER HIGH CURRENT STRESS AND HBM ESD ZAPPING EVENTS—J.H. Lee, K.M. Wu, S.C. Huang, and C.S. Tang, TSMC, Hsinchu, Taiwan

The direct substrate potential (DSBP) measurement is introduced to investigate the dynamic current distribution of the multi-fingers GGNMOS under the high current stress event, from DSBP measurement result, some new phenomena are observed that are never found and discussed before.

ES02 THE IMPACT OF INNER PICKUP ON ESD ROBUSTNESS OF MULTI-FINGER NMOS IN NANOSCALE CMOS TECHNOLOGY—M.-D. Ker⁽¹⁾, and H.-C. Hsu^{(1,2)          (1)}National Chiao-Tung Univ., Hsinchu, Taiwan;          ⁽²⁾SoC Technology Center, Hsinchu, Taiwan

The impact of pickup structure on ESD robustness of multi-finger MOSFET devices in the nanoscale CMOS process is investigated in this work with 1.2-V and 2.5-V devices in a 130-nm CMOS process. The multi-finger MOSFET device without the pickup structure inserted into its source region can sustain a much higher ESD level and more compact layout area for I/O cell are recommended.

ES03 DEPENDENCE OF LAYOUT PARAMETERS ON CABLE DISCHARGE EVENT (CDE) ROBUSTNESS OF CMOS DEVICES IN A 0.25-µm SALICIDED CMOS PROCESS—M.-D. Ker and T.-X. Lai, National Chiao-Tung Univ., Hsinchu,

The long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of NMOS and PMOS devices has been experimentally investigated in details. From the measured results, the CDE robustness of CMOS devices is much worse than its HBM ESD

ES04 SOI POLY-DEFINED DIODE FOR ESD PROTECTION IN HIGH SPEED I/Os—V. Chen, Univ. of Illinois at Urbana-Champaign, Urbana, IL, A. Salman, S. Beebe, AMD, Sunnyvale, CA, E. Rosenbaum, Univ. of Illinois at Urbana-Champaign, Urbana, IL, S. Mitra, C. Putnam, and R. Gauthier, IBM, Essex Jct, VT

We present a model for the bias-dependent capacitance of poly-defined SOI ESD protection diodes. We also present a biasing circuit that minimizes the diode capacitance under normal operating conditions and maximizes the ESD failure current. The capacitance reduction is more than a factor of 2 with proper biasing.

ES05 SELF-PROTECTING ARRAYS FOR OPEN DRAIN CIRCUITS—V.A. Vashchenko and P.J. Hopper, National Semiconductor, Santa Clara, CA

A new ESD protection strategy for NMOS and NLDMOS arrays has been described and experimentally evaluated. The problem of ESD protection of analog circuits has been addressed at the device/array level. Contrary to conventional rail-based or local clamp approaches this new concept provides for a self-protection capability into the array itself. The self-protecting capabilities of the NMOS array is achieved by embedding a local SCR region with reversible snapback capabilities and with a stronger dependence of the snapback voltage upon gate bias. Example of SPA arrays realized in 5V NMOS process and a 50V NLDMOS process have been demonstrated.

Wednesday, March 29, 7:00 p.m., Computer History Museum

FA FAILURE ANALYSIS

Co-Chairs: Mike Bruce, AMD and Steven Kasapi, Credence

FA01 INFRARED RAY EMISSION (IREM) BASED POST-SILICON POWER DEBUG FLOWS DEVELOPED FOR CHIP POWER PERFORMANCE—Y.-C. Chen, D. Bockelman, D. Lu, M. Ma, and I. Wan, Intel, Hillsboro, OR

Pre-silicon power modeling, post-silicon power validation, and power debugs design efforts have significantly increased to meet speed performance, reliability deliverables and design robustness for manufacturing. IREM based power debug flow has been developed to isolate marginal circuits with excessive static and dynamic power consumption. Three root cause analysis cases are presented to demonstrate the success of this novel post-silicon debug flow.

FA02 APPLICATION OF ELECTRICAL DIAGNOSIS AND C-AFM TO ISOLATE ON BOARD AC SCAN FAIL—L.F. Wen, C.H.Chen, TSMC, Hsinchu, Taiwan

With the migration from deep submicron process to today's nanometer-scale process, speed-related defect begin to dominate the yield loss. The path delay now is the predominant failure, especially when device is on board test. Traditional localization approaches, such as EMMI, OBIRCH, TIVA, MCT etc is hard to detect subtle delays or isolate them correctly. In this paper, we succeeded in applying electrical diagnosis and C-AFM skill to isolate on board AC scan fail. This technique is effective of scan-based AC tests, particularly those exhibiting delay faults.

FA03 45 nm NODE CATEGORIZED VIA CHAIN RESISTANCE AND IMAGE BY OPTICAL BEAM INDUCED RESISTANCE CHANGES (OBIRCH) METHOD—Y. Matsubara and T. Watanabe, Semiconductor Leading Edge Technologies, Tsukuba-shi, Japan

Via chain resistance categorized by OBIRCH image was investigated using samples having 140nm pitch and 200nm pitch via chain interconnect. Via chain resistance is increased as increasing of number of defects in the case of line edge roughness failure. Line end shortening and via filling failure strongly impact on total resistance of via chain test structure was identified by image. The concurrent failure mode between open and short failure can be revealed by the image features and the categorized resistance.

FA04 IMPACT OF UNTREATED THICKER CVD TiN FILM AT A VIA GLUE LAYER ON RC PERFORMANCE IN 0.15 µm CMOS TECHNOLOGY—K.S. Lee, N.S. Kim, J. Liu, J.W. Shin, W.K. Chin, Y. Li, Y.S. You, J. Tan, H.G. Yoon, and S.H. Han, Systems on Silicon Mfg. Co. Pte. Ltd., Singapore

In this work, it is reported that the mechanism was intensively studied on abnormal high Via Rc and the promising solution was proposed for the dramatic improvement Rc in 0.15um CMOS devices. We found out that Via Rc is very sensitive to CVDTiN plasma treatment efficiency and also a slight CVDTiN thickness fluctuation could significantly increase the amount of untreated CVDTiN film, leading to Via Rc increase.Plasma treatment optimization in CVDTiN is of ultimate importance to ensure Via Rc robustness in 0.15um CMOS technology and beyond.

FA05 CATASTROPHIC DEGRADATION OF ORGANIC OPTICAL THIN FILM COMPONENTS—Y. Gigase, Altran-Europe, Brussel, Belgium

This paper discusses the catastrophic degradation of polarizers used in LCD display projectors. These polarizers are made of a stack of thin organic films. The degradation is initialized under the influence of UV light, which releases radicals. Those radicals modify the film so that it absorbs more visible light. Due to this absorption the temperature increases, which accelerates the degradation till the film is destroyed. The proposed model is formulated mathematically and verified by experiments. It can be used for other components that degrade in analogous ways, like laser diodes.

FA06 SURFACE TRANSPORTATION OF CHEMICAL SPECIES IN SPRAY-CLEANING AND GATE OXIDE INTEGRITY—L. Shen, E. De Backer, P. Verpoort, J. De Greve, AMI Semiconductor, Oudenaarde, Belgium

This paper discusses spray-cleaning and its potential impacts on gate oxide integrity. It is demonstrated for the first time that the surface transportation behavior of chemical species in a spray-cleaning vividly reflects on a microscopic scale well inside the failure patterns of gate oxide at a wafer level.

Wednesday, March 29, 7:00 p.m., Computer History Museum

HK HIGH k

Co-Chairs: Ajit Shanware, Texas Instruments and
Gennadi Bersuker, Sematech

HK01 TRANSIENT CURRENTS IN HfO₂ AND THEIR IMPACT ON CIRCUIT AND MEMORY APPLICATIONS—C.M. Compagnoni, A.S. Spinelli, A. Bianchini, A.L. Lacaita, S. Spiga, and M. Fanciulli, DEI Politecnico di Milano, Milano, Italy

In this work we investigate transient currents in HfO₂ dielectrics, considering their dependence on electric field, temperature and gate stack composition. We show that transient currents remain an issue even at very low temperatures and changing the HfO₂/ SiO₂ bilayer properties and we assess their possible impact on the reliability of precision circuit and memory applications.

HK02 FAST V_th INSTABILITY IN HfO₂ GATE DIELECTRIC MOSFETS AND ITS IMPACT ON DIGITAL CIRCUITS—C. Shen, T. Yang, M.-F. Li, G. Samudra, Y.-C. Yeo, C.X. Zhu, National Univ. of Singapore, Singapore, S.C. Rustagi, M.B. Yu, and D.-L. Kwong, Institute of Microelectronics, Singapore

Fast component of V_th instability in MOSFET with HfO₂ gate dielectric is systematically measured and characterized. A charge trapping/de-trapping model is used to simulate the Vth instability with overall agreement with the experiments. Experimental and modeling data provide and predict the fast V_th shift under both static and dynamic stress conditions. These data are incorporated into HSpice circuit simulation to evaluate the impact of V_th shift on the performance of digital circuit in realistic situations. Considering the properties of the fast V_th instability, circuit performance can be optimized by circuit design in addition to process improvements. This should be included to the guideline of process development and circuit design for future CMOSFET digital systems.

HK03 GATE DIELECTRIC INTEGRITY ALONG THE ROAD MAP OF CMOS SCALING INCLUDING MULTI-GATE FET, TiN METAL GATE, AND HfSiO HIGH-k GATE DIELECTRIC—T. Pompl, Infineon Technologies, Munich, Germany, H.C. Mogul, Texas Instruments, Dallas, TX, M. Kerber, Infineon Technologies, Munich, Germany, G. Haase, E. Ogawa, J.W. McPherson, Texas Instruments, Dallas, TX, W. Xiong, T. Schulz, International SEMATECH, Austin, TX, K. Schrufer, Infineon Technologies, Munich, Germany, and R. Cleavelin, Texas Instruments, Dallas, TX,

Dielectric integrity was investigated for different gate stacks of TiN and poly-silicon together with SiO₂ and HfSiO dielectrics in order to identify the key topics on the road map of CMOS scaling by using vertical multi-gate device architectures. Multi-gate architectures show state of the art gate dielectric reliability, whereas metal gate and high-k introduce different dependencies on gate polarity for NFET and PFET.

HK04 CARRIER RECOMBINATION IN HIGH-K DIELECTRICS AND ITS IMPACT ON TRANSIENT CHARGE EFFECTS IN HIGH-K DEVICES—C.Y. Kang, UT Austin, Austin, TX, SEMATECH, Austin, TX, R. Choi, S.C. Song, C.D. Young, G. Bersuker, B.H. Lee, SEMATECH, Austin, TX, and J.C. Lee, UT Austin, Austin, TX

In this paper, transient charge trapping and detrapping characteristics in high-k CMOSFETs were systematically studied. Transient charge recombination within the high-k layer was found to be the main reason for the input signal dependence in high-k devices. Detrapping characteristics for nMOSFETs and pMOSFETs were closely related with the transient hole and electron trapping,

HK05 IMPROVING CARRIER MOBILITY AND RELIABILITY CHARACTERISTICS OF HIGH-k NMOSFET BY USING STACKED Y₂O₃/HfO₂ GATE DIELECTRIC—F. Zhu, C.Y Kang, S.J. Rhee, C.H Choi, S.A. Krishnan, M. Zhang, H.S. Kim, T. Lee, I. Ok, G. Thareja, and J.C. Lee, UT Austin, Austin, TX

To overcome the issues of mobility degradation and charge trapping in the high-k MOSFET, a stacked Y₂O₃(top)/HfO₂(bottom) multi-metal gate dielectric with TaN gate has been developed. Compared to the HfO₂ reference, the new dielectric shows similar scalability, but superior device performance and reliability characteristics. Channel mobility, fast transient charge trapping, bias temperature instability, and stress induced leakage current have been shown to improve for Y₂O₃/HfO₂ device.

HK06 RELIABILITY CHARACTERISTICS OF METAL/HIGH-k PMOS WITH TOP INTERFACE ENGINEERED BAND OFFSET DIELECTRIC (BOD)—H.R. Harris, S. Krishnan, H.-C. Wen, H. Alshareef, A. Rao, L. Solis, P. Majhi, R. Choi, B.H. Lee, G. Bersuker, and G.A. Brown, SEMATECH, Austin, TX

To achieve low threshold voltage, the top interface is engineered with an Al dielectric. The transistor structure shows a >200mV reduction in threshold voltage in PMOS devices. It is shown that the Al dielectric does not contribute to reliability concerns associated with PMOS devices.

HK07 RELIABILITY OF SUB 30 nm BT(BODY-TIED)-FINFET WITH HfSiON/POLY SILICON GATE STACK FOR SYMMETRIC V_th CONTROL—E.S. Cho, C.-H. Lee, A. Fayrushin, H.B. Park, and D. Park, Samsung Electronics, Yongin-City, Korea

In this paper, a symmetric threshold of W_fin=10nm FinFET has been achieved by using HfSiON dielectric (V_tn=0.25V / V_tp= -0.28V) since the threshold voltage control (>|0.2V|) of 10nm FinFET is problematic because the body is fully depleted. Fermi level pinning and low boron segregation effects of HfSiON are the main mechanisms determining appropriate threshold voltages. And the reliability issues(Shift of J_G, G_M and I_CP according to stress and hot carrier life time) of HfSiON and Gnox dielectric with various fin width have been also evaluated for the first time.

HK08 GENERALIZED MODELS FOR OPTIMIZATION OF BTI IN SiON AND HIGH-k DIELECTRICS—A. Haggag, M. Moosa, S. Kalpat, N. Liu, M. Kuffler, H.-H. Tseng, T.-Y. Luo, J. Schaeffer, D. Gilmer, S. Samavedam, R. Hegde, B.E. White Jr., and P.J. Tobin, Freescale Semiconductor, Austin, TX

A generalized reliability model of BTI is presented where it is shown that gate stacks with similar interfacial layer lie on the same NBTI vs E-field universal curve and those with similar bulk layer lie on the same PBTI vs E-field universal curve. From these universal curves, an optimal gate stack can be derived for which NBTI=PBTI.

Wednesday, March 29, 7:00 p.m., Computer History Museum

IT INTERCONNECT

Co-Chairs: Glenn Alers, Novellus Systems and Amit Marathe, AMD

IT01 EFFECTS OF Al DOPING ON ELECTROMIGRATION PERFORMANCE OF NARROW SINGLE DAMASCENE Cu INTERCONNECTS—S. Yokogawa and H. Tsuchiya, NEC Electronics Corp., Kawasaki, Japan

We report the effects of Al doping from seed layer to Cu on electromigration in narrow single-damascene lines. To investigate the dependencies of Al concentration, the seed layer thickness was changed from 40 to 90nm. The effects of Al doping on incubation time, drift velocity, and critical product are discussed.

IT02 DETERMINATION OF IRMS RULES FOR 65 nm NODE DESIGN FOUNDATIONS AND THERMAL EFFECT OF DUMMIES—D. Ney, STMicroelectronics Crolles, France, X. Federspiel, Philips, Crolles, France, V. Girault, STMicroelectronics Crolles, France, O. Thomas, and P. Gergaud, Univ. Aix Marseille III, Marseille, France,

We propose in the present paper Root Mean Square (RMS) current rules to limit Joule heating in the back end of line (BEOL) of 65nm node circuits. These rules are based on a new analytical thermal resistance model previously determined for 130 and 90nm node BEOL. To confirm the validity of this model through technologies, Joule heating measurements at 110°C were performed on copper lines embedded with SiOC dielectric for the 65nm node technology.

IT03 EFFECTS OF WIDTH SCALING, LENGTH SCALING, AND LAYOUT VARIATION ON ELECTRO-MIGRATIONIN IN DUAL DAMASCENE COPPER INTERCONNECTS—M.H. Lin^(1,2), K.P. Chang⁽¹⁾, K.C. Su⁽¹⁾, T. Wang^{(2)          (1)}United Microelectronics Corp, Hsinchu City, Taiwan          ⁽²⁾National Chiao-Tung Univ., Hsinchu City, Taiwan

Two scenarios for width scaling were shown. One is the w<1µm region, in which MTF shows weak width dependence. The other is the w>1µm region, in which MTF shows strong width dependence. A theory was proposed to explain the observed behavior. Blech effect in a dual damascene process and its temperature dependence using a three-level interconnect structure was demonstrated under long time testing.

IT04 STUDY OF Cu MIGRATION INDUCED FAILURE OF INTER-LAYER DIELECTRIC—S.-S. Hwang, S.-Y. Jung, J.-K. Jung, and Y.-C. Joo, Seoul National Univ., Seoul, KOREA

The FDM simulation of the Cu ion migration and TDDB of Cu in SiO₂ were carried out. Through the simulation and TDDB results, it was discussed that the dielectric failure is not cause by the conduction path formed by Cu ions.

IT05 ANALYSIS OF ELECTROMIGRATION VOIDING PHENOMENA IN Cu INTERCONNECTS—L. Arnaud⁽¹⁾, J.F. Guillaumond^(1,2), N. Claret⁽¹⁾, C. Cayron⁽³⁾, C. Guedj⁽¹⁾, M. Dupeux⁽⁴⁾, V. Arnal⁽²⁾, G. Reimbold⁽¹⁾, G Passemard⁽²⁾, and J. Torres^{(2)          (1)}CEA-LETI, Grenoble, France;         ⁽²⁾STM, Crolles, France;          ⁽³⁾CEA-LITEN, Grenoble, France;          ⁽⁴⁾LTPCM, Saint Martin d'Heres, France

Electromigration induced voiding has been analyzed in Cu interconnects with different sidewall Cu diffusion barriers. A PVD process provided lifetime results which suggest failures limited by void growth mechanism. In situ Scanning Electron Microscopy shows the steps of void growth. Electron backscattering diffusion analysis shows that grain boundaries joining the line sidewall are preferential sites for void nucleation. Results of CVD process are consistent with failures limited by void nucleation.

IT06 SIMULATION OF ELECTRICAL AND MECHANICAL PROPERTIES OF AIR-BRIDGE Cu INTERCONNECTS—H. Park, M. Kraatz, J. Im, B. Kastenmeier*, and P.S. Ho, UT Austin, Austin, TX          *SEMATECH, Austin, TX

Air-bridge type Cu interconnects in which air gaps are formed in metal line and/or via level have been modeled and their effective dielectric constants and stress levels have been investigated. The results indicate that fully-dense SiCOH dielectric is a suitable material for fabricating air-bridge interconnects in comparison with oxide or porous MSQ dielectric.

IT07 POROSITY-INDUCED ELECTRIC FIELD ENHANCEMENT AND ITS IMPACT ON CHARGE TRANSPORT IN POROUS INTER-METAL DIELECTRICS—C. Hong and L. Milor, Georgia Tech, Atlanta, GA

Free volumes or pores in porous ultra-low-k dielectrics enhance the local electric field in the neighborhood. In this paper, this enhanced local electric field is shown to facilitate the transport of charged species such as copper ions, electrons, or holes. This leads to the conclusion that porosity in dielectrics can degrade the insulating property and enhance the dielectric breakdown mechanism.

IT08 MULTIMODAL ANALYSIS OF STRESS INDUCED DEGRADATION OF 90 nm NODE INTERCONNECTS—X.Federspiel and M. Gregoire, Philips, Crolles, France

The resistance increase of vias was characterized in the temperature range 175 - 250°C. We found that degradation mechanism was bimodal. The intrinsic contribution is minimized by high thermal budget process or by removing barrier at via bottom. We showed that it was diffusion controlled mechanism with activation energy of 1eV.

IT09 IMPROVED BIPOLAR ELECTROMIGRATION MODEL—L. Doyen, X. Federspiel, Philips, Crolles, France and D. Ney, STMicroelectronics Crolles, France

Wafer-level electromigration tests were performed under low frequency bipolar current. We propose an improvement to the existing healing models to take into account the probability of failure at both sides of test lines. We calculated the scaling factor between single and double failure modes, and determined healing coefficient to 0.8+/-0.18.

IT10 SIZE EFFECTS AND TEMPERATURE DEPENDENCE OF STRESS-INDUCED VOIDING—M. Hommel and S. Penka, Infineon Technologies AG, Muenchen, Germany

The stress-induced voiding behavior of via structures with different geometries was tested. A variation of via sizes, aspect ratios, and widths of connected metal lines was studied. The resistance drift and its temperature dependence showed sensitivity to the structure size. This can be explained by the size-dependence of mechanical stress.

IT11 IDENTIFICATION AND LAYOUT MODIFICATION OF COPPER/LOW k INTERCONNECT DIELECTRIC RELIABILITY ASSESSMENT BY USING RVDB TEST—T.M.Z. Lin, W.M. Hsu, S.R. Lin, R.C.J. Wang, C.C. Chiu, and K. Wu, TSMC, Hsinchu, Taiwan

Recent study had demonstrated that the pathways of leakage current and dielectric breakdown formation in symmetric line-to-line structure and asymmetric via-involved structure were considerably different. Reliability improvements for the dominant failure modes and leakage conduction mechanisms of these two common interconnect structures in copper/low-k dielectrics system were investigated by using wafer-level ramped voltage to dielectric breakdown (RVDB) test. This work interpreted the identification of these dominant leakage conduction pathways relying on corresponding interconnect process improvements including conductive barriers and dielectric barriers/etch stop layers. Also, based on the finite element method (FEM), some layout modification to eliminate the "metal lineend effect" for reliability test structure in RVDB or TDDB test methodology had been proposed to well characterize the intrinsic behavior of interconnect dielectrics.

IT12 IDENTIFICATION OF A NOVEL BTS FAILURE MECHANISM IN A COPPER/ULTRA-LOW k INTEGRATION USING A STOPLESS TRENCH ETCH PROCESS—L. Smith, W. Engbrecht, K. Neuman, R. McGowan, and K. Pfeifer, SEMATECH, Austin, TX

We have discovered a novel failure mode in M2-M2 bias temperature stress (BTS) testing, in which the failure is mediated by shorting between the M2 and M1 metal layers. This mode may be important whenever the trench etch/ash process creates anomalous M2-M1 minimum spacings.

Wednesday, March 29, 7:00 p.m., Computer History Museum

MY MEMORY

Co-Chairs: Alessandro Spinelli, Politecnico di Milano and
Hanmant Belgal, Intel

MY01 INSIGHT OF STRESS EFFECT ON THE ONO STACK LAYER IN A SONOS-TYPE FLASH MEMORY CELL—C.C. Yeh*, W.J. Tsai, Y.Y. Liao, T. Wang*, T.C. Lu, T.F Ou, M.S. Chen, Y.J. Chen, E.K. Lai, Y.H. Shih, W.C. Ting, J. Ku, and C.-Y. Lu, Macronix, Hsin-Chu, Taiwan         *also with National Chiao-Tung Univ., Hsin-Chu, Taiwan

The stress effect on the ONO stack layer in a two-bit SONOS-type memory cell is investigated. Our results show that P/E cycles induced stress will generate extra nitride, oxide, and interface traps in the ONO stack layer. Besides, these stress created traps are unstable and will be annealed by additional thermal treatment. Storage electrons escape from stress-created nitride and oxide traps and the trap annealing effects are root causes of charge loss in a SONOS cell.

MY02 INVESTIGATION OF CHARGE LOSS IN CYCLED NBIT CELLS VIA FIELD AND TEMPERATURE ACCELERATIONS—W.J. Tsai, N.K. Zous, H.Y. Chen, L. Liu, C.C. Yeh*, S. Chen, W.P. Lu, T. Wang*, J. Ku, and C.-Y. Lu, Macronix, Hsin-Chu, Taiwan
*also with National Chiao-Tung Univ., Hsin-Chu, Taiwan

In nitride storage flash memories, the high-VT state retention loss induced by field and temperature acceleration is compared between single cells and products. Our result reveals that the charge loss path is the same no matter which accelerating methods is used. The traps created at the bottom oxide during P/E cycling provide such leak paths. In addition, the annealing of interface states would play a role in the VT loss during high-temperature bake.

MY03 IMPROVEMENT OF DATA RETENTION TIME PROPERTY BY REDUCING VACANCY-TYPE POINT DEFECT IN DRAM CELL TRANSISTOR—K. Okonogi, K. Ohyu, T. Umeda*, H. Miyake, and S. Fujieda**, ELPIDA Memory, Sagamihara, Japan          *Univ. of Tsukuba, Tsukuba, Japan,         **NEC Corp, Sagamihara, Japan

Data retention times of 0.11µm DRAM were successfully improved by reduction of the vacancy-type defect density, especially, the reduction in the number of tail-bits was achieved. An additional annealing process stimulating generation of the interstitial silicon could effectively reduce the vacancy-type defects. EDMR analysis clearly showed decrease of the defects to half.

MY04 RELIABILITIES OF MgO TUNNELING BARRIER FOR MRAM APPLICATION—C. Yoshida, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Stoh, M. Aoki, S. Umehara, M. Satoh, and K. Kobayashi, Fujitsu Lab Ltd., Atsugi, Japan

We investigated the reliability of MgO and AlO_x tunneling barrier, for MRAM application. It is found that MgO tunneling barrier has the hydrogen tolerance compared with AlOx tunneling barrier. It also demonstrated that MgO-barrier MTJ has longer lifetime, over 10 years, than AlO_x -barrier MTJ by TDDB data

MY05 ENDURANCE AND RETENTION CHARACTERISTICS OF SONOS EEPROMs OPERATED USING BTBT INDUCED HOT HOLE ERASE—P.B. Kumar, Indian Institute of Technology, Bombay, India, E. Murakami, S. Kamohara, Renesas Technology, Tokyo, Japan, and S. Mahapatra, Indian Institute of Technology, Bombay, India,

This work focuses on the reliability of SONOS EEPROMs operated using channel hot electron injection (CHEI) for programming, and band-to-band tunneling induced hot hole injection (HHI) for erase. Studying the endurance under different erase conditions shows that optimization of erase bias can achieve fast, single-cycle erase, with good endurance. However, HHI is seen to degrade the interface (bottom oxide) quality, starting from the first erase pulse. Post-cycling retention loss (in programmed state) is affected more by this degradation, than by lateral charge migration.

MY06 TEMPERATURE DEPENDENCE OF ENDURANCE CHARACTERISTICS IN NOR FLASH MEMORY CELLS—W.H. Lee, C.-K. Park, and K. Kim, Samsung Electronics, Yong-In, S. Korea

A temperature dependence of endurance characteristics in NOR flash cells is presented. The window closing is accelerated after 100 K cycling due to a degraded program speed at 85°C compared to that measured at 25°C. A transition of interface trap creation from channel region to the drain overlap region is suggested as an origin for the endurance degradation at high temperature. Also process conditions exhibiting these properties will be summarized.

MY07 A NEW PHENOMENON AND ITS MECHANISM OF RETENTION TIME EVOLUTION IN THE EMBEDDED DRAM TECHNOLOGY WITH HIGH-k DIELECTRICS (Ta₂O₅) MIM CAPACITOR AFTER HIGH TEMPERATURE OPERATION LIFE TEST—J.R. Shih, R.F. Tsui, K. Liu, Y.S. Tsai, H.W. Chin, and K. Wu, TSMC, Hsinchu, Taiwan

A new phenomenon of FBC reduction and retention time increase in the embedded DRAM with high-K dielectric Ta₂O₅ MIM capacitors has been observed and well characterized. It is found although the GIDL currents of transfer pMOSFETs will be increased after long-term stress, the leakage current reduction of MIM capacitor due to charge trapping after BI can cover GIDL current increase and dominates the product reliability behavior.

Wednesday, March 29, 7:00 p.m., Computer History Museum

PC PRODUCT & CIRCUITS

Co-Chairs: Robert Kwasnick, Intel and
Vijay Reddy, Texas Instruments

PC01 CIRCUIT PERFORMANCE DEGRADATION OF SAMPLE-AND-HOLD AMPLIFIER DUE TO GATE-OXIDE OVERSTRESS IN A 130-nm CMOS PROCESS—J.-S. Chen and M.-D. Ker, National Chiao-Tung Univ., Hsinchu, Taiwan

The effect of MOSFET gate-oxide reliability on MOS switch is investigated with the sample-and-hold amplifier in a 130-nm CMOS process. The sample-and-hold amplifier with the open-loop configuration is used to verify the impact of MOS switch gate-oxide reliability on the sample-and-hold amplifier. After overstress on the MOS switch of the sample-and-hold amplifier, the circuit performances on the time domination and frequency domination have been measured to verify the impact of MOS switch gate-oxide reliability on circuit performance.

PC02 HOT CARRIER-INDUCED DEGRADATION ON HIGH-k TRANSISTORS AND LOW NOISE AMPLIFIER—C. Yu and J.S. Yuan, Univ. of Central Florida, Orlando, FL

HC-induced DC and RF degradations in 60 nm high-k nMOSFETs are examined experimentally. The normalized circuit performance degradations can be predicted from normalized transistors parameters. Good agreement between the analytical predictions and simulation results is obtained.

Wednesday, March 29, 7:00 p.m., Computer History Museum

PI PROCESS INTEGRATION RELIABILITY

Co-Chairs: Jeff Peterson, Intel & Sematech and
Kin P. Cheung, Rutgers University

PI01 ENHANCED GOI DEGRADATION AND RELIABILITY IMPROVEMENT OF NITROGEN AND INDIUM CO-IMPLANT FOR ADVANCED DUAL-GATE OXIDE APPLICATION—J.S. Wang, N.-C. Wu, T. Wang, J. Hsieh, J. Chen, H.K. Hsu, D. Chen, T. Fong, and L. Mei, ProMOS Technologies, Hsinchu, Taiwan

Indium and nitrogen implant were used to form the NMOSFET retrograde channel and low-threshold thin-oxide devices respectively. Enhanced GOI degradation was observed for nitrogen and indium Co-implant oxides. Fluorine impurities were used to heal the implant-induced damage and recover the oxide reliability.

PI02 EFFECT OF CHEMICAL MECHANICAL POLISH PROCESS ON LOW-TEMPERATURE POLY-SIGE THIN FILM TRANSISTORS—M.-S. Shieh, C.-Y. Chen, Y.-J. Hsu, S.-D. Wang, and T.-F. Lei, National Chiao Tung Univ., Hsinchu,

The improvement of polycrystalline silicon germanium thin-film transistors (poly-SiGe TFTs) using NH3 passivation and chemical mechanical polishing (CMP) process was examined. Experimental results indicated that NH₃ passivation could effectively improve the turn on characteristics. Moreover, the TFTs fabricated on polished poly-SiGe film exhibit higher carrier mobility, better subthreshold swing, lower threshold voltage, and higher on/off current ratio due to the smooth poly-SiGe interface.

PI03 PROCESS INDUCED INSTABILITY AND RELIABILITY ISSUES IN LOW-TEMPERATURE POLY-SI THIN-FILM TRANSISTORS—M.H. Cho, Y.I. Kim, D.S. Woo, S.W. Kim, M.S. Shim, Y.J. Park, W.S. Lee, and B.I. Ryu, Samsung Electronics Co., Yongin-City, Korea

We investigated the impact of plasma process on the device's performance and reliability degradation of low-temperature poly-Si thin-film transistors (LTPS TFTs). LTPS TFTs with different antenna areas were used to study the effects of the plasma etching process on the devices. The larger TFT antenna area, the more performance instability occurs. The reliability of LTPS TFTs with large antenna areas was found to be degraded from high voltage stress and hot carrier stress.

PI04 A NOVEL HIGH RELIABILITY ILD STACK—J.J. Naughton and M.A. Nelson, AMI Semiconductor, Pocatello, ID

In this work a thick multi-layer dielectric stack with low stress, low CMP defectivity, and soft error immunity has been developed. This was accomplished by sequencing PECVD and SACVD films with a critically placed densification step.

PI05 STUDY ON THE RETENTION TIME OF BODY TIED FINFET DRAM WITH <100> CHANNEL DIRECTIONAL WAFER—C. Lee, K. Kim, E.S. Cho, S. Ko, C.K. Kim, H.H. Park, D. Kim, C.-H. Lee, and D. Park, Samsung, Yongin-City, Japan

A negative word line (NWL) bias scheme is adapted to the body tied finFET DRAM. But, increased gate induced drain leakage (GIDL) degrade data retention time. The retention time of <100> channel directional wafer (CW) was compared to that of <110> CW. Using <100> CW to the finFET DRAM, increased on current and reduced GIDL current improve the data retention time.

PI06 INVESTIGATION INTO THE DEPENDENCY OF PLASMA INDUCED DAMAGE ON THE STRUCTURAL MOS GEOMETRY WITH A FAST WLR STRESS AND MEASUREMENT SEQUENCE—A. Martin, C. Schlünder, P.-E. Oswald, Infineon Technologies, München, Germany

In this work various MOS antenna transistor geometries and antenna ratios were assessed to find the most sensitive PID monitor. It is demonstrated that a narrow device is most suitable for a PID detection stress method. For this investigation a new fast stress and measurement sequence for PID detection (JEDEC proposal) on wafer level was used, which yields excellent results for the PID detection.

Wednesday, March 29, 7:00 p.m., Computer History Museum

SE SER

Co-Chairs: Ron Lacoe, The Aerospace Corp. and
Paul Dodd, Sandia National Labs

SE01 ELIMINATION OF SINGLE EVENT LATCHUP IN 90nm SRAM TECHNOLOGIES—H. Puchner, R. Kapre, S. Sharifzadeh, J. Majjiga, R. Chao, D. Radaelli, and S. Wong, Cypress, San Jose, CA

We present a comprehensive review of design as well as process options to completely eliminate soft error induced single event latchup (SEL) in modern CMOS based SRAM technologies. The detailed mechanism of latchup under a radiation environment is discussed and analyzed. EPI substrate starting material and the use of a triple well architecture are selected as process technology options to eliminate SEL. In addition to the process options we present a circuit option to quench out single event latchup.The option has been implemented on 90nm and validated on multiple experimental nuclear testing sites.

Wednesday, March 29, 7:00 p.m., Computer History Museum

TR TRANSISTORS

Co-Chairs: Giuseppe La Rosa, IBM and
Anand Krishnan, Texas Instruments

TR01 INVESTIGATION OF HOT CARRIER DEGRADATION IN GROOVED CHANNEL STRUCTURE N-MOSFET: SPHERE SHAPED RECESS CELL ARRAY TRANSISTOR (SRCAT)—J.Y. Seo, K.J. Lee, H. Kim, S.Y. Lee, S.S. Lee, W.S. Lee, Y.J. Kim, S.J. Hwang, and C.K. Yoon, Samsung Electronics, Hwasung-City, Korea

In this paper, The HC degradation of the SRCAT and the Pch/Rch have been investigated first. The SRCAT having lower degradation rate than the Pch/Rch can be explained by relaxation of Emax. An important result from this work is that the increasing effective channel length in sphere shape channel structure.

TR02 DYNAMIC NEGATIVE BIAS TEMPERATURE INSTABILITY CHARACTERISTICS AND COMPREHENSIVE MODELING IN PMOS BODY-TIED FINFETs—H. Lee, KAIST, Daejeon, Korea, C.-H. Lee, Samsung, Kyunggi-Do, Korea, D. Park, Samsung, Kyunggi-Do, Korea, and Y.-K. Choi, KAIST, Daejeon, Korea

This paper presents a novel approach to estimate the rising and falling behavior of Nth -order on-state current by DNBTI. For the first time, a modified DNBTI model in PMOS body-tied FinFETs was proposed and compared with experimental data. The DNBTI behaviors dependent upon stress bias, fin width, body temperature, and virtual floating body were analyzed.

TR03 DC AND AC NBTI STRESS IN pMOSFETs WITH PE-SiN CAPPING LAYER—C.-Y. Lu, H.-C. Lin, Y.-F. Chang, and T.Y. Huang, National Chiao Tung Univ., Hsinchu, Taiwan

DC and AC NBTI characteristics of pMOSFETs with compressive strain in the channel are investigated. In spite of the usefulness of channel strain in improving the drive current as previously reported, our results indicate that it may worsen the DC NBTI characteristics. In AC NBTI stress, neutralization of trapped holes in the oxide also contributes the recovery in V_th, and strong dependence on the frequency is observed for the SiN-capping devices.

TR04 DEGRADATION MECHANISM IN LOW-TEMPERATURE p-CHANNEL POLYCRYSTALLINE SILICON TFTs UNDER DYNAMIC STRESS—Y. Toyota, M. Matsumura, M. Hatano, T. Shiba, and M. Ohkura, Hitachi, Ltd., Japan

Pronounced device degradation due to trap states caused by electron-hole recombination and its temperature dependence are clarified. The rapid degradation at high temperature is caused by an increase in the number of trapped holes, to which NBT stress significantly contributes. Guidelines for highly reliable TFT circuits are then proposed.

TR05 INTERFACE-TRAP DRIVEN NBTI FOR ULTRATHIN (EOT~12Å) PLASMA AND THERMAL NITRIDED OXYNITRIDES—G. Gupta, S. Mahapatra, L.L. Madhav, D. Varghese, IIT Bombay, Mumbai, India, K. Ahmed, F. Nouri, Applied Materials, Santa Clara, CA

Generation and recovery of V_T is studied during and after NBTI stress under a wide range of stress conditions. By employing carefully designed experiments, it is conclusively shown that DV_T is due to DNIT for ultrathin oxide as well as thermal and plasma oxynitride p-MOSFETs. The time, E_OX and T dependence of NBTI generation and recovery can be explained within the R-D model framework.

TR06 PHYSICAL MODELING OF NEGATIVE BIAS TEMPERATURE INSTABILITIES FOR PREDICTIVE EXTRAPOLATION—V. Huard, Philips Semiconductors, Crolles, France, C.R. Parthasarathy, C. Guerin, and M. Denais, STMicroelectronics, Crolles, France

Based on new insights on measurement methodologies, interface traps creation and hole trapping as root causes of NBTI degradation are investigated in this paper. Physical modeling is proposed and the related extrapolation laws are discussed.

TR07 PARADIGM SHIFT FOR NBTI CHARACTERIZATION IN ULTRA-SCALED CMOS TECHNOLOGIES—M. Denais⁽¹⁾, A. Bravaix⁽³⁾, V. Huard⁽²⁾, C. Parthasarathy^(1,3), C. Guerin^(1,3), G. Ribes⁽¹⁾, F. Perrier⁽²⁾, M. Mairy⁽¹⁾, and D. Roy^{(2)          (1)}STMicroelectronics, Crolles, France;          ⁽²⁾Philips, Crolles, France;          ⁽³⁾L2MP-ISEN, Toulon, France

We propose a new framework to manage NBTI in ultra-scaled technology and beyond. This takes into account both the non-permanent degradation properties and the electrical parameter legitimacy in each electrical configuration. The universal recovery is characterized for a large range of stressing mode. We handle AC stress directly in advanced circuits to deal with AC stress directly in advanced circuits to deal with AC NBT effects.

TR08 NOVEL MODEL FOR HCI DEGRADATION AND IMPACT OF CONVENTIONAL AND NON-CONVENTIONAL SCALING—A. Haggag, M. Kuffler, D. Zhang, M. Sadaka, P. Grudowski, and M. Moosa, Freescale Semiconductor, Austin TX

We derive an HCI degradation model where bond breaking occurs via multiple local excitations as opposed to a classical carrier injection or single-impact excitation assumption. The model predicts a strong Id/W power-law dependence of HCI in addition to typical 1/Vdd dependence and is used to study the impact of conventional and non-conventional scaling on MOSFET HCI degradation versus the main scaling knobs: A) Channel Length Scaling B) Channel Compressive/Tensile Stress, and C) Top and Side Surface Orientation.

TR09 PHONON-ENERGY-COUPLING ENHANCEMENT: DRAMATIC IMPROVEMENT OF THE RELIABILITY OF SILICON MOS TRANSISTORS—Z. Chen and J. Guo, Univ. of Kentucky, Lexington, KY

We report a new effect for the SiO₂/Si system, phonon-energy coupling enhancement, i.e. the energy coupling of vibrational modes of the Si-D bonds to Si-Si and Si-O bonds is enhanced dramatically when rapid thermal process (RTP) is directly applied to the SiO₂/Si system. When applying this effect to MOSFETs, we observed dramatic reliability improvement of MOS devices. The breakdown voltage of the gate oxide of the transistors has been improved by 40%. The hot-electron related lifetime of MOS transistors has been improved by 100 times over the deuterium annealed transistors.

TR10 A NEW NBTI LIFETIME MODEL (Ig-MODEL) AND AN INVESTIGATION ON OXIDE THICKNESS EFFECT ON NBTI DEGRADATION AND RECOVERY—C.L. Chen, M.J.Chen, C.J.Wang, and K. Wu, TSMC, Hsinchu, Taiwan

A new Ig-model is proposed to quickly predict NBTI lifetime for ultra thin oxide (<=3.0nm). The oxide thickness effect on NBTI degradation, recovery and lifetime prediction model are systematically investigated. The mechanism of the NBTI degradation and recovery dependence on oxide thickness is explained as the two-side hydrogen reaction-diffusion mechanism.

Thursday, March 30, 8:00 a.m., Room A, Parallel Session

5A TRANSISTORS

Co-Chairs: Giuseppe La Rosa, IBM and
Anand Krishnan, Texas Instruments

5A.1 NBTI: AN ATOMIC-SCALE DEFECT PERSPECTIVE—J.P. Campbell, P.M. Lenahan, Penn State Univ., University Park, PA, A.T. Krishnan, and S. Krishnan, Texas Instruments, Dallas, TX

We utilize a combination of gated-diode DC-IV, spin-dependent recombination magnetic resonance, and Arrhenius measurements to investigate the atomic-scale defects involved in NBTI in modern SiO₂ and plasma-nitrided SiO₂ based pMOSFETs. Our observations indicate that the D_it generation process in thin plasma-nitrided SiO₂ devices is fundamentally different from thicker SiO₂ devices.

5A.2 ANALYSIS OF NBTI DEGRADATION- AND RECOVERY-BEHAVIOR BASED ON ULTRA FAST V_T -MEASUREMENTS—H. Reisinger, O. Blank, W. Heinrigs, A. Muhlhoff, W. Gustin, and C. Schlunder, Infineon Technologies, München, Germany

Using a new ultra fast direct V_T measurement technique an analysis of short- as well as long term behaviour and recovery of pMOSFETs after NBTI stress has been done. Experimental data over an 11 decades time span were compared to theory for the first time. A fast precursor due to trapping was detected. Considering this precursor experimental degradation curves can be well fitted based on a physical model rather than on just straight line fits.

5A.3 INVESTIGATION OF NITROGEN-ORIGINATED NBTI MECHANISM IN SiON WITH HIGH-NITROGEN CONCENTRATION—K. Sakuma, D. Matsushita, K. Muraoka, and Y. Mitani, Toshiba, Yokohama, Japan

In this paper, we investigate the nitrogen originated NBT degradation mechanism of SiON films by using SiON with high nitrogen concentration. As a result, we interpret that there is a new NBT degradation mechanism with small NBTI exponents originated by nitrogen incorpolation.

5A.4 EFFECTS OF HOT CARRIER STRESS ON RELIABILITY OF STRAINED-Si MOSFETs—S. Dey, Univ. of Texas at Austin, Austin, TX, M. Agostinelli, C. Prasad, X. Wang, and L. Shifren, Intel, Hillsboro, OR,

It is demonstrated for the first time that the impact ionization rate (IIR) in tensile strained-Si NMOS, unlike compressively strained-Si PMOS, shows a peak at a particular strain in the channel and reduces at further higher strain. This peak-IIR strain is found to be strongly dependent on the electrical stress bias.

5A.5 ANALOG DEVICE AND CIRCUIT PERFORMANCE DEGRADATION UNDER SUBSTRATE BIAS ENHANCED HOT CARRIER STRESS—K. Narasimhulu and V. R. Rao, Indian Institute of Technology, Mumbai, India

In this paper, we investigate the influence of body bias stress on the hot carrier induced degradation of MOS analog performance parameters. The underlying physical mechanisms are identified with the help of experimental results, TCAD and Monte-Carlo simulations. Degradation in various analog circuits' performance is quantified by considering the individual transistors under different stress conditions.

5A.6 NEW INSIGHTS INTO RECOVERY CHARACTERISTICS POST NBTI STRESS—C.R. Parthasarathy^(1,3), M. Denais⁽¹⁾, V. Huard⁽²⁾, G. Ribes⁽¹⁾, E. Vincent⁽¹⁾, and A. Bravaix^{(3)          (1)}STMicroelectronics, Crolles, France;          ⁽²⁾Philips, Crolles, France;          ⁽³⁾L2MP-ISEN, Toulon, France

In this work, we investigate recovery characteristics post NBT stress when the recovery bias remains negative but lower in magnitude than the stress bias, consolidating the viewpoint involving role of hole trapping during NBTI degradation. We show that successive negative recovery biases can be applied to view trapping behavior explicitly.

Thursday, March 30, 8:00 a.m., Room B, Parallel Session

5B BEOL

Co-Chairs: Baozhen Li, IBM and
Gaddi Haase, Texas Instruments

5B.1 A STATISTICAL EVALUATION OF THE FIELD ACCELERATION PARAMETER OBSERVED DURING TIME-DEPENDENT DIELECTRIC BREAKDOWN TESTING OF SILICA-BASED LOW-k INTERCONNECT DIELECTRICS—J. Kim, E.T. Ogawa, and J.W. McPherson, Texas Instruments, Dallas, TX

Extensive time-dependent dielectric breakdown (TDDB) data were taken for several silica-based low-k interconnect dielectrics so that the full statistical-distribution for the field acceleration parameter (g) could be determined. The low-k materials tested during this study included: SiOF (k=3.6), OSG1 (k=2.9), OSG2 (k=2.6) and MSQ (k=2.3). While a strong material-dependence was found for the breakdown strength and time-to-failure, all of these silica-based materials tested at 105°C were observed to have a similar field acceleration parameter of (g)=4.13+/-0.85 cm/MV.

5B.2 A NEW TDDB DEGRADATION MODEL BASED ON Cu ION DRIFT IN Cu INTERCONNECT DIELECTRICS—N. Suzumura⁽¹⁾, S. Yamamoto⁽¹⁾, D. Kodama⁽¹⁾, K. Makabe⁽²⁾, J. Komori⁽¹⁾, E. Murakami⁽²⁾, S. Maegawa⁽¹⁾, and K. Kubota⁽³⁾, Renesas Technology Corp.          ⁽¹⁾Itami, Japan;          ⁽²⁾Hitachinaka, Japan;          ⁽³⁾Kodaira, Japan

A new physical model of Time-Dependent Dielectric Breakdown (TDDB) in Cu interconnect dielectrics is proposed. TDDB occurs due to the drift of Cu ions under an electric field E. An activation energy analysis of the leakage current demonstrates that these injected Cu ions affect the mechanism of leakage current. The dominant mechanism of the leakage current changes from Poole-Frenkel (PF) electron current through the Cubarrier dielectrics to Fowler-Nordheim (FN) current due to the Cu pile-up at the cathode end. We assume the influence of one of two types of Cu ion drift mechanism, Schottky type or Poole-Frenkel type. The field acceleration model (ÖE model) of the PF type fits the electric field dependence of TDDB lifetime and activation energy very well. The TDDB lifetime is proportional to the exponential of the square root of the electric field ÖE.

5B.3 RELIABILITY CHARACTERIZATION OF BEOL VERTICAL NATURAL CAPACITOR USING COPPER AND LOW-k SiCOH DIELECTRIC FOR 65nm RF AND MIXED-SIGNAL APPLICATIONS—F. Chen⁽¹⁾, F. Ungar⁽³⁾, A. Fischer⁽³⁾, A. Chinthakindi⁽²⁾, J. Gill⁽¹⁾, T. Goebel⁽³⁾, M. Shinosky⁽¹⁾, D. Coolbaugh⁽²⁾, V. Ramachandran⁽²⁾, Y.K. Siew⁽⁴⁾, E. Kaltalioglu⁽³⁾, S.O. Kim⁽³⁾, and K.-C. Park^{(5)          (1)}IBM Microelectronics, Essex Jct., VT;          ⁽²⁾IBM Microelectronics, Hopewell Junction, NY;          ⁽³⁾Infineon Technologies AG, Munich, Germany;          ⁽⁴⁾Chartered Semiconductor Mfg., Singapore,          ⁽⁵⁾Samsung Electronics Co., Kyunggi-Do, Korea

The TDDB degradation and capacitance stability of BEOL Vertical Natural Capacitor (VNCAP) using CVD low-k (SiCOH) dielectric and copper at 65nm node technology were critically studied. The impact of trapped moisture at SiCOH interface on device TDDB kinetics and capacitance stability was identified. With the optimal device design and process, SiCOH VNCAP was found to exhibit robust TDDB performance, as well as absence of capacitance instability during bias-temperature stress.

5B.4 RELIABILITY CHARACTERIZATION OF DIFFERENT PORE SEALING TECHNIQUES ON POROUS SiLK* DIELECTRIC FILMS—J. Michelon⁽¹⁾, J. Waeterloos⁽²⁾, P.H.L. Bancken⁽¹⁾, V.H. Nguyen⁽¹⁾, R. Caluwaerts⁽³⁾, S. Rozeveld⁽²⁾, E. Beach⁽²⁾, and R.J.O.M. Hoofman^{(1)          (1)}Philips, Leuven, Belgium;          ⁽²⁾Dow Chemical Co., Midland, MI;          ⁽³⁾IMEC, Leuven, Belgium

Reliability of porous SiLK processed with two different pore sealing techniques has been investigated. It has been shown that the post-CMP-burn-out (PCBO) pore sealing process outperforms the post-etch-burn-out (PEBO) process in term of dielectric reliability as well as in term of electromigration.

5B.5 DIELECTRIC CONDUCTION MECHANISMS OF ADVANCED INTERCONNECTS: EVIDENCE FOR THERMALLY- INDUCED 3D /2D TRANSITION—C. Guedj⁽¹⁾, V. Arnal⁽²⁾, M. Aimadeddine⁽²⁾, J.P. Barnes⁽¹⁾, J.C. Barbe⁽¹⁾, L. Arnaud⁽¹⁾, G. Reimbold⁽¹⁾, J.Torres⁽²⁾, G. Passemard⁽²⁾, and F. Boulanger^{(1)          (1)}CEA-Leti, Grenoble, France;          ⁽²⁾STMicroelectronics, Crolles, France

Electrical, electro-optical, mechanical and microstructural characterizations explain why the leakage currents in advanced Cu/ultra-low K interconnects can change from bulk (3D) to mostly interfacial (2D), above 150ºC. A physical model consistent with all these results is proposed for the first time.

Thursday, March 30, 10:30 a.m., Room B, Parallel Session

5C COMPOUND DEVICES 2

Co-Chairs: Robert S. Okojie, NASA-Glenn Research Center and
Brian J. Skromme, Arizona State University

5C.1 BV_CER INCREASED OPERATING VOLTAGE FOR SiGe HBTs—J. Kraft, B. Loffler, N. Ribic, and E. Wachmann, austriamicrosystems AG, Unterpremstatten, Austria

SiGe-heterojunction bipolar transistors operation is limited by BV_CEO. We show that BV_CER, the avalanche breakdown with a resistor RB connected to the base, can be easily calculated and used to define reliable operating conditions exceeding BV_CEO. The functionality of this concept is verified by investigating a power amplifier circuit.

5C.2 Time-to-fail extraction model for the Mixed-Mode reliability of high performance SiGe bipolar transistors—D. Panko, T. Vanhoucke*, R. Campos and G.A.M. Hurkx*, Philips Semiconductors, Hopewell Junction, NY *Philips Research Leuven, Leuven, Belgium

We present a mixed-mode reliability time-to-fail model for high-performance SiGe HBTs. We systematically extract model parameters for 10% current-gain (hFE) degradation as function of stress parameters VCB and IE over multiple orders of empirical drift data. The model also includes VBE readout and geometry scalings.

Thursday, March 30, 8:00 a.m., Room C, Parallel Session

5D MEMORY 2

Co-Chairs: Alessandro Spinelli, Politecnico di Milano and
Hanmant Belgal, Intel

5D.1 CHARACTERIZATION OF CHARGE TRAPS IN METAL-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR (MONOS) STRUCTURES FOR EMBEDDED FLASH MEMORIES—T. Ishida, Y. Okuyama, and R. Yamada, Hitachi, Ltd., Tokyo, Japan

A characterization of electron and hole traps in MONOS structures is studied. We clarify that the electron traps mainly locate at both top and bottom oxide/nitride interfaces, whereas hole traps locate at the same interfaces as well as in the nitride bulk. We also find that the mechanism of electron emission from the traps is thermal assisted tunneling.

5D.2 STUDY OF CHARGE LOSS MECHANISM OF SONOS-TYPE DEVICES USING HOT-HOLE ERASE AND METHODS TO IMPROVE THE CHARGE RETENTION—H.-T. Lue, Y.-H. Hsiao, Y.-H. Shih, E.-K. Lai, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, , Macronix Int'l Co. Ltd., Hsinchu, Taiwan

The retention degradation mechanism of NBit/NROM is examined extensively. The in-situ 150°C electrical testing is used to examine the electron/hole stability, where we find no discernable electron/hole lateral migration in the nitride. Next, we apply the refill and soft erase methods with various electrical conditions to study the charge loss mechanism. The experimental results show that the vertical charge loss measured by Vg-accelerated retention test at 25°C is highly correlated to the charge loss measured at 150°C baking. Our results strongly support the vertical charge loss model.

5D.3 RETENTION RELIABILITY OF FINFET SONOS DEVICE—J.J. Lee, S.H. Lee, H. Chae, B.Y. Choi, S.-K. Sung, S.P. Kim, E.S. Cho, C.H. Lee, and D. Park, Samsung Electronics Co., Ltd., Korea

This paper presents the retention reliability of the FinFET SONOS Flash memory. By understanding the charge loss mechanisms of the SONOS structure, a new approach for the prediction of long term retention lifetime have been proposed. The comparison between the thermal-accelerated and field-accelerated lifetime has been demonstrated.

5D.4 TEMPERATURE MONITOR: A NEW TOOL TO PROFILE CHARGE DISTRIBUTION IN NROM MEMORY DEVICES—L. Avital⁽¹⁾, A. Padovani⁽²⁾, L. Larcher⁽²⁾, I. Bloom⁽¹⁾, R. Arie⁽³⁾, P. Pavan⁽²⁾, B. Eitan^{(1)          (1)}Saifun Semiconductors, Netanya, Israel;          ⁽²⁾Università di Modena e Reggio Emilia, Reggio Emilia, Italy;          ⁽³⁾Tel Aviv Univ., Ramat Aviv, Israel

NROM memory cells are proposed as one of the most promising non-volatile memories. Issues on scaling and endurance have risen due to the presence of both electrons and holes, for the control of their relative position and spread in the charge trapping material. In this paper we present a new characterization tool able to sense the relative position of these two charge distributions that can be efficiently used for program/erase bias optimization and reliability predictions. This new tool exploits temperature effects on I_D-V_GS current measurements.

Thursday, March 30, 10:05 a.m., Room C, Parallel Session

5E PRODUCT & CIRCUITS 3

Co-Chairs: Fred Kuper, Philips Semiconductors and
Andreas Preussger, Infineon Technologies

5E.1 REALISTIC PROJECTIONS OF PRODUCT FAILS FROM NBTI AND TDDB—A. Haggag, M. Moosa, N. Liu, D. Burnett, G. Abeln, M. Kuffler, K. Forbes, P. Schani, M. Shroff, M. Hall, C. Paquette, G. Anderson, D. Pan, K. Cox, J. Higman, M. Mendicino, and S. Venkatesan, Freescale, Austin, TX

Statistical models for deconvolving the effects of competing mechanisms on product failures are presented. Realistic projections of product fails are demonstrated on high performance microprocessors by quantifying the contributions of NBTI, TDDB and extrinsic fail mechanisms. In particular, it is shown that transistor shifts due to NBTI manifest as population tails in the products minimum operating voltage (Vmin) distribution, while TDDB manifests as single-bit or logic failures that constitute a separate

5E.2 EARLY TECHNOLOGY PRODUCT DEFECT ISSUES—T.J. Anderson and J.M. Carulli, Jr., Texas Instruments, Dallas, TX

Many challenges must be met in order to bring a new product and technology to production. Among those are identifying ways to reduce latent defects during testing. By understanding the pareto of root cause failure modes gathered during burn-in studies, changes in process, test, or design may be employed to optimize product outgoing defect levels. These changes will be based on the defect acceleration kinetic, rather than just the reliability fail-fraction. Product use condition impact can now be quantified in terms of the reliability response of extrinsic defects. Measuring the level of control of low part-per-million defects is also critical in maintaining overall quality and a new method is discussed.

5E.3 SUCCESSFUL DEVELOPMENT AND IMPLEMENTATION OF STATISTICAL OUTLIER TECHNIQUES ON A 65 nm PROCESS DRIVER DEVICE—A. Nahar, S. Subramaniam, J.M. Carulli Jr., T.J. Anderson, and K.M. Butler, Texas Instruments, Dallas, TX

Burn-in and the concomitant post-burn-in retest are a significant cost adder to the overall. IC manufacturing and test process. Methods to reduce burn-in capacity are continually sought. Traditional outlier screens such as fixed-limit sigma or Tukey analyses applied to the newest technologies result in excessive Type I or II errors which cannot be tolerated. In this paper, we describe the results from developing and applying somewhat more sophisticated statistical burn-in avoidance techniques to a driver design fabricated in a 65nm low leakage technology and library.

Thursday, March 30, 2:00 p.m., Room A, Plenary Session

6A FAILURE ANALYSIS

Co-Chairs: Mike Bruce, AMD and Steven Kasapi, Credence

6A.0 (ESREF-Best invited) DOPANT IMAGING AND PROFILING OF WIDE-BAND-GAP DEVICES BY SECONDARY ELECTRON POTENTIAL CONTRAST—M. Buzzo^(a,b), M. Ciappa^(b), M. Stangoni^(b), and W. Fichtner^{(b) (a)}Infineon Technologies, Villach, Austria; ^(b) Swiss Federal Institute of Technology (ETH), Zurich, Switzerland

Secondary Electron Potential Contrast in Scanning Electron Microscopy is proposed as the method of choice for two-dimensional dopant imaging and profiling of wide-band-gap semiconductor devices, including SiC MOSFETs, SiC JFETs, quantum wells, and VCSEL lasers. After a review of the physical principles governing the signal generation, the quantitative capabilities of this technique are assessed with applications to test structures and real devices.

6A.1 SWITCHING TIME EXTRACTION OF CMOS GATES USING TIME-RESOLVED EMISSION (TRE)—F. Stellari, A. Tosi*, and P. Song, IBM T.J. Watson Research Center, Yorktown Heights, NY         *Politecnico di Milano, Milan, Italy

We present an innovative methodology, with experimental confirmation, for extracting the switching time of a gate by means of time-resolved optical measurements (using PICA) and optical simulations based on a luminescence model in a SPICE simulator. The method represents a valuable extension of the set of PICA measurements for improving hardware-model correlation and process yield.

6A.2 DYNAMIC THERMAL LASER STIMULATION: THEORY AND APPLICATIONS—K. Sanchez, R. Desplats, F. Beaudoin, P. Perdu, CNES, Toulouse, France, S. Dudit, and M. Vallet, STMicroelectronics, Crolles, France, D. Lewis, IXL, Talence, France

Challenges to IC analysis have forced the development of new techniques. Thermal Laser Stimulation (TLS) is now applicable to dynamically activated devices (test pattern). Localization of defects is performed using with opposite time constraints: slow thermal inertia and fast IC commutation. An understanding of physical interactions is imperative for pushing TLS even further.

6A.3 A NEW INSIGHT INTO THE BREAKDOWN MECHANISM IN ULTRATHIN GATE OXIDES BY CONDUCTIVE ATOMIC FORCE MICROSCOPY—L. Zhang and Y. Mitani, Toshiba, Kawasaki, Japan

BD evolution mechanism in ultrathin SiO₂ films is investigated by CAFM. The structural deformation at pre-BD stage and trap effect are found to be less pronounced with decreasing thickness and voltage. It is found that the pre-BD Si deformation is induced by the joule heating during inelastic tunneling of energetic carriers.

6A.4 FAILURE DEFECTS OBSERVED IN POST-BREAKDOWN HIGH-k/METAL GATE STACK MOSFET—R Ranjan⁽¹⁾, K.L. Pey⁽¹⁾, C.H. Tung⁽²⁾, D.S. Ang⁽¹⁾, L.J. Tang⁽²⁾, T. Kauerauf⁽³⁾, R. Degraeve⁽³⁾, G. Groeseneken⁽³⁾, S. De Gendt⁽³⁾, and L.K. Bera          ⁽¹⁾Nanyang Technological Univ., Singapore;          ⁽²⁾Institute of Microelectronics, Singapore;          ⁽³⁾IMEC, Leuven, Belgium

Failure defects associated with breakdown of metal/HfO₂ gate stack MOSFETs are studied. Very fast degradation rate in leakage current is attributed to possibly gate material filamentation of breakdown path. The consequence of the filamentation leads to various degrees of severities in microstructral damages in metal gate, different from poly-Si MOSFETs.

6A.5 HOT-CARRIER PHOTOEMISSION IN SCALED CMOS TECHNOLOGIES: A CHALLENGE FOR EMISSION BASED TESTING AND DIAGNOSTIC—A. Tosi, F. Stellari*, A. Pigozzi, G. Marchesi and F. Zappa, Politecnico di Milano, Milano, Italy          *IBM T.J. Watson Research Center, Yorktown Hgts., NY

We present the experimental characterization of hot-carrier luminescence emitted by transistors in four CMOS technologies. Aim of the research is to gain a better perspective on emission trends and dependences on technological parameters, identifying luminescence changes due to Short-Channel Effects and comparing p-FETs and n-FETs. The results extend the applicability of optical testing techniques also to future low-voltage chips.

6A.6 TIME-RESOLVED AND STROBOSCOPIC EBIC ANALYSES STUDIES OF A PHOTODIODE AND HIGH POWER DIODES —T. Geinzer, A. Pugatschow, R. Heiderhoff, F.-J. Niedernostheide*, L.J. Balk, Bergische Univ. Wuppertal, Wuppertal, Germany        *Infineon Technologies, München, Germany

Time-resolved and stroboscopic EBIC micro-analyses are powerful techniques to perform comprehensive studies on the dynamic behaviour of opto-electronic devices. The inhomogeneity of diffusion and drift processes of a dynamically operated photodiode is detected by an experimental set-up, which allows a distance up to 160 dB between operational and induced current. It is for the first time possible to generate EBIC maps of a dynamically biased diode using a new setup. This technique allows investigations of E-field distributions and their variations inside a power device.

6A.7 OXIDE PARTICLE INDUCED LEAKAGE IN FLASH MEMORY ENDURANCE RELIABILITY—W. Zhang and S.H. Tan, Systems on Silicon Mfg. Co., Singapore

Direct observation of SiO_x particle causing current leakage resulting in flash endurance failure was reported. The oxide particle differentiates from surrounding oxide in charge-attaining property and chemical components. The charges driven by thermal heating and electrical cycling finally form leakage path. Si-rich particle makes it an easier way for charges transportation.