Process-Induced Damage - A History, and Prognosis

The past 20 years has seen the growing pains in which new energetic processes have been introduced into the conventional semiconductor fabrication process repetoire. Salient among these are various depositions and etches assisted by a plasma. It developed that accompanying these processes were unanticipated electrical influences, causing damage to the devices being fabricated. An active sub-industry rapidly developed to understand these influences, and limit their impact to an acceptable level through design rules, tooling improvements, and new processes. In this tutorial we will review some of the more important discoveries of this effort, and how the application of these concepts can inform the development of future technologies.

Terence B. Hook

Terence B. Hook received the Sc. B degree in Electrical Engineering from Brown University in 1980, following which he earned the Ph.D. at Yale University under the auspices of the IBM Resident Study program, studying under Prof. T-P. Ma. He has worked in the IBM Microelectronics Division in the area of device design and technology integration on CMOS and bipolar technologies for 25 years. He is currently concentrating on 90 and 65, and 45nm bulk technologies, most directly on low-power transistors. He also continues to pursue his interest in plasma-induced damage, in both bulk and SOI technologies. He is based in Essex Junction, VT, but spends considerable time in East Fishkill, NY. He holds numerous patents and has authored many papers over the past 20 years.