Advanced Interconnect Processes for the 45 nm Node and Beyond



	Advanced Interconnect Processes for the 45 nm Node and Beyond

	Jeff Gambino IBM Systems and Technology Group Essex Junction, VT 05452

	Interconnect process using copper wiring and low-k dielectrics are reviewed for the 45 nm technology node and beyond. First, the structure and properties of low-k materials and barrier layers are described. Porous dielectrics are generally required to achieve k < 2.5, but these materials are mechanically weak and chemically reactive, making integration very challenging. Next, integration issues are described including patterning, cleans, metallization, chemical mechanical polishing (CMP), and packaging. The patterning process is becoming increasingly difficult because of the smaller dimensions, the need for reduced linewidth variation, and the use of dielectrics that contain carbon. Hardmasks are increasingly being used to solve problems such as resist erosion and resist strip damage of the low-k material. Metallization is more difficult because the liner and Cu seed thicknesses must be drastically reduced, to avoid increasing the line resistance and allow void free Cu plating to occur. The physical vapor deposition (PVD) techniques that have been used in previous technology generations are preferred for process simplicity. However, other deposition methods, such as atomic layer deposition (ALD) for the liner and direct plating to replace the seed layer, may be required beyond the 45 nm node. CMP is increasingly challenging because of the low mechanical strength of the low-k dielectrics and the need for reduced dishing and dielectric erosion. New planarization methods such as electro-chemical mechanical polishing (eCMP) are being used to address these problems. Packaging is increasingly difficult because of the low mechanical strength of the dielectrics. Dicing, wirebonding, molding, and underfill processes must be optimized when packaging chips that have low-k dielectrics in the stack. When using low-k materials, there is usually a trade-off between reliability and performance; to achieve high reliability, relatively thick barriers and liners are required, which results in higher line-to-line capacitance and higher wire resistance. The major challenge is how to achieve a significant improvement in effective dielectric constant when using porous low-k materials.



Jeff Gambino Jeff Gambino received the B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and the Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices . In 1992, he joined the DRAM development alliance at IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM's manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents .