Mixed Signal Circuit Reliability



	Mixed Signal Circuit Reliability Chain of cause and effect of IC-failures

	Christian Schluender Infineon Technologies, Inc.

	Modern state of the art CMOS technologies show inevitable parameter degradation of their devices during use. To ensure reliability of microelectronic products is a collective challenge for technology experts and circuit designers. A close collaboration early in development of new technologies and circuit design in terms of reliability is needed. There is an increasing demand for "Reliability by Design". For this task a deep understanding of the reliability risks of modern integrated circuits is necessary. This talk will discuss the chain of causation leading to a possible IC failure due to device degradation. Starting with device stress conditions based on circuit operation, up to the emerging damage mechanisms within MOSFETs, the electrical parameter shift will be explained, which finally causes the consequences for the circuit function. The problems will be illustrated with various circuit examples for digital-, analog- and RF-applications. Furthermore the influence of modern smart energy saving options like Power-Down-Modes, voltage scaling, clock gating or sleep transistor techniques will be taken into account. Simple guidelines for 'Design for Reliability' will complete the discussion.



Christian Schlünder Christian Schlünder has received his Dipl.-Ing. (1999) in electrical engineering from the University of Dortmund, Germany. From 1998-1999 he worked in a cooperative program between Siemens Corporate Research Labs in Munich and the University of Dortmund in the field of characterization, modelling and reliability of analog CMOS circuits. After founding of Infineon Technologies AG, he worked for a short time as a technical consultant for Infineon, until he joined Infineon as a member of the Corporate Research Department, where he has been active in research on bias temperature stress. Currently he is doing research work in the area of NBTI towards his Dr.-Ing.. Currently he is a Staff Engineer at the Infineon Central Reliability Methodology Group. He manages reliability qualification projects for various state-of-the-art CMOS-Technologies and working on the reliability of forefront technologies like SOI, MultiGate-FETs etc. He has published in several conference proceedings and microelectronic journals. He is frequently a member of the Technical Program Committee of the IEEE-conferences "IRPS", "IRW" and referee of several IEEE journals.