ESD & latchup

In this tutorial, the physics of CMOS components under high current conditions to derive ESD protection design for sub-100 technologies will be discussed. Special emphasis will be devoted to the process aspects in an effort to confidently predict high current behavior and scaling properties. This is useful for understanding protection device behavior and for optimizing protection circuit networks.

Gianluca Boselli

Gianluca Boselli completed his master's studies in electrical engineering at the University of Parma, Italy, in 1996. In 2001 he completed his doctoral studies at the University of Twente, The Netherlands, where he worked on high current phenomena of CMOS components.

He joined the Silicon Technology Development group of Texas Instruments, Dallas, Texas, USA, in February 2001. He authored and co-authored several papers in the area of ESD and Latch-up. He presented his work at major conferences, including IEDM, IRPS and EOS/ESD Symposium. His current work focuses on ESD and Latch-up development for advanced CMOS technologies with special emphasis on process and modeling aspects.

Dr. Boselli has been the recipient of the "Best Paper Award" on behalf of Microelectronics Reliability Journal in 2000. He also received "The Best Paper Award" and the "The Best Presentation Award" at the EOS/ESD Symposium in 2002. Dr. Boselli is a member of IEEE and of ESD Association. Dr. Boselli serves on the Technical Program Committee of the EOS/ESD Symposium, IRPS and ESREF.