Reliability Challenges
for
Ultra-thin Oxide

As the gate oxide thickness is scaled below 2 nm, meeting the product reliability specifications is becoming challenging. The reduction in reliability margins has lead to an increased research effort and deeper understanding of the mechanisms that govern degradation and eventually limit the reliability of ultra-thin oxides. In this tutorial, an overview of the main physical mechanisms that govern Time Dependent Dielectric Breakdown (TDDB) will be discussed. Based on these mechanisms, the different voltage and temperature acceleration models proposed in literature will be reviewed. For these ultra-thin gate oxides, the definition of breakdown is a function of the application for which the transistor is being optimized. An overview of the different stages of breakdown and their impact on the product lifetime will be presented. This understanding allows gate oxide failure to be defined accurately for a particular application.

Tanya Nigam

Tanya Nigam was born in Kanpur, India. She received her Bachelor's degree in Physics (Hons.) from St. Stephens College, Delhi University. She obtained a M.Sc in Physics from IIT Kanpur and a M.Sc in Electrical Engineering from the Katholieke Universiteit Leuven in 1995. Between 1995 and 1999, she worked towards a Ph.D in the area of ultra-thin gate oxides at IMEC, Belgium. From 1999 until 2001, Tanya was a Member of Technical Staff at Bell Labs. During this period she worked on novel device geometries to overcome sub-50nm device challenges. From 2001 until 2005, she was with Agere Systems, formerly the Microelectronics Division of Lucent Technology. At Agere, she worked on reliability issues for power LDMOS devices, and HCI/NBTI reliability concerns for CMOS. Since October 2005 Tanya is Senior Staff at Cypress Semiconductor involved in the optimization of 65nm CMOS. She has co-authored 25 papers in Journals and Conferences.