Gate oxide breakdown in FET devices and circuits

With the ongoing downscaling of CMOS devices, the probability of soft gate oxide breakdowns occurring during the useful product lifetime is steadily increasing. Conversely, such events do not anymore spell the immediate failure of the entire application. This tutorial attempts to build a fundamental physical understanding of the post-breakdown FET behavior. The impact of gate oxide breakdown on several types of devices and digital circuits is then discussed.

Ben Kaczer

Ben Kaczer received the M. S. degree in Physical Electronics from Charles University, Prague, Czech Republic, in 1992 and the M. S. and Ph. D. degrees in Physics from The Ohio State University in 1996 and 1998, respectively. For his Ph. D. research on the ballistic-electron emission microscopy of SiO₂ and SiC films he received an OSU Presidential Fellowship. In 1998 he joined the Reliability, Electrical Characterization and Modeling group of IMEC, where his activities include the research of degradation phenomena and reliability prediction of SiO₂ and high-k films.