Electrical Characterization of High-k Gate Dielectrics

Introduction of high-k gate dielectrics, which can enable several orders of magnitude lower gate current compared to SiO₂, is demanded especially for gate dielectrics of CMOSFETs of Low Standby Power and Low Operating Power applications. Extensive studies on the properties of high-k/Si system have been carried out in the past 5-6 years, however, the control of the electrical properties of high-k CMOSFETs is insufficient somewhat like that of Si-MOS in the 60's, and still not commercialized at this point. In this tutorial, I would like to summarize the measurement methodologies and corresponding observed electrical properties of high-k/Si system. Reliability issues will also be covered. New electrical measurement techniques which can decompose intrinsic and extrinsic properties of high-k gate dielectrics will be introduced and it will be pointed out that pre-existing traps play an important role in determining electrical properties and reliability.

Mariko Takayanagi

Mariko Takayanagi is currently a senior specialist in SoC Research and Development Center, Toshiba Corpration Semiconductor Company. She joined the Toshiba Research and Development Center, Kawasaki, Japan, in 1987, where she was engaged in the research on the characterization of the process and the electrical properties in Si MOS devices. In 1991, she moved to ULSI Device Engineering Laboratory, Toshiba (now named as SoC Research and Development Center, Toshiba Corp. Semiconductor Company), where she has been engaged in the research and the development of Field Programmable Gate Array, the analysis of hot carrier degradation in Si MOSFETs, and oxynitride gate dielectrics and oxide reliability physics. She is currently a team leader of device design/process integration team of CMOSFET with high-k gate materials. She is a committee of high-k committee for IRPS2006. She has authored and co-authored more than 60 technical and conference papers. She gave a tutorial talk in ICMTS (International Conference on Microelectronic Test Structures) in 2004, and was the invited speaker of IEDM 2005. She was awarded SSDM (International Conference on Solid State Devices and Materials) Paper Award in 2002 and STS Award from SEMI in 2005. Her main interest is the device physics of MOS system including reliability phenomena.