The role of Reliability Mechanisms in the architecture and design of embedded RAMs

VLSI technology scaling over time has uncovered new and complex issues for circuit designers to overcome. In order to provide high quality designs that meet market demands for performance, manufacturability and reliability, designers work closely with test and reliability colleagues at each new technology node. This helps designers to anticipate the advent of new or changing reliability issues which may drive design decisions. This tutorial will discuss how the synergism of reliability mechanisms coupled with process scaling effects can drive changes in RAM circuit design techniques and RAM product operating modes.

Wayne F. Ellis

Wayne F. Ellis is a Senior Scientist at the IBM Micro-Electronics facility in Essex Junction, Vermont where he has worked since 1977. He received the BSEE from Union College, Schenectady, New York in 1985, MSEE from the University of Vermont in 1992 and the Ph.D. in Materials Science in 1993, also from the University of Vermont, where his doctoral research studied Hot Carrier trapping in FETs under A.C. Stress. He has worked in various leadership and management positions in the design and development of DRAM, eDRAM and eSRAM products from inception to production ramp. He holds over 40 Patents and has published over 35 papers. He has been a past Workshop Moderator at the 1997 IRPS, gave an invited paper on DRAM Design at the 1999 IRW and has given two previous tutorials at the IRPS. Dr. Ellis spent the fall semester 2002 at the University of Linkoping, Sweden as a Distinguished Visiting Professor in Information Technology, under the auspices of the Swedish and American Fulbright Associations. He is an Adjunct Professor at the University of Vermont where he teaches a graduate course which studies the impacts of process variations, defects and Reliability Mechanisms on VLSI circuit design. Dr. Ellis is currently working in 65 nm embedded SRAM technology and product development.