IC Testing for Reliability

This tutorial will be an overview of test methods and design for testability (DFT) for semiconductor devices. The focus will be on manufacturing testing and on digital or mostly digital products. Also, since structured (DFT-based) tests now dominate the industry, particular attention will be paid to covering those aspects for both logic and memory. Aspects of testing that are particularly pertinent to reliability engineers such as stress, data collection for outlier analyses, and burn-in will be emphasized throughout the tutorial. The goal of the presentation will be to familiarize the attendee with concepts and terminology, but not to recommend nor provide detailed user information onparticular EDA tools.

Kenneth M. Butler

Kenneth M. Butler is a TI Fellow in the Qualtiy and Reliability Engineering Department within the Silicon Technology Development Group of Texas Instruments in Dallas, Texas. He received his MS and PhD degrees in electrical engineering from the University of Texas in 1987 and 1990, respectively. In 1991, he rejoined Texas Instruments, first in the Design Automation Division and then in the ASIC Division. He spent more than 13 years working in the areas of design for testability, test methodology development and automated diagnosis before moving to SiTD to work on advanced test data analysis and statistical outlier identification techniques. Ken is a Senior Member of the IEEE and was the program chair of the 2005 IEEE International Test Conference. He was the co-recipient of the best paper award for the 1999 IEEE VLSI Test Symposium, and was twice selected as the best speaker at the TI Symposium on Test. His research interests include automatic test pattern generation and advanced applications for scan design and other structured design and test techniques.