Technical Program (with abstracts)

• Keynote address: "Basic Research for the Air Force of the 21st Century," Dr. Tom Hussey, Chief Scientist for the Air Force Office of Scientific Research (AFOSR)

The Air Force Office of Scientific Research (AFOSR), located in Arlington, Virginia, is a directorate of the Air Force Research Laboratory. AFOSR manages the fundamental research activities (6.1) for the United States Air Force, and is charged with seeking out revolutionary technology advances and for assuring that the U. S. Air Force is prepared to embrace these advances. We accomplish this by identifying and funding many of the brightest and most innovative minds worldwide in areas that may profoundly impact the Air Force of the future. In this talk we describe the purpose and structure of AFOSR and give an overview of some of the revolutionary technology advances that it has supported in the past as well as some ongoing research that we believe will play a significant role in shaping the future Air Force.

• 2006 IRPS Best/Outstanding Paper and Best Poster Awards— John Suehle, 2006 IRPS Technical Program Chair

• Technical Program Introduction—Ronald Lacoe, Technical Program Chair

Tuesday, April 17, 9:40 a.m., Room A

SESSION 1. TRANSISTORS & MEMORY

Co-Chairs: Anand Krishnan, Texas Instruments, Walter Riordan, Intel,
Elyse Rosenbaum, University of Illinois, and Chandra Mouli, Micron

1.1 ON THE PHYSICAL MECHANISM OF NBTI IN SILICON OXYNITRIDE P-MOSFETS: CAN DIFFERENCES IN INSULATOR PROCESSING CONDITIONS RESOLVE THE INTERFACE TRAP GENERATION VERSUS HOLE TRAPPING CONTROVERSY?—S. Mahapatra, IIT Bombay, Mumbai, India, K. Ahmed, Applied Materials, Santa Clara, CA, D. Varghese, IIT Bombay, A.E. Islam, Purdue Univ., W. Lafayette, IN, G. Gupta, L. Madhav, D. Saha, IIT Bombay, Mumbai, India, and M.A. Alam, Purdue Univ., W. Lafayette, IN

Negative Bias Temperature Instability (NBTI) is studied in plasma (PNO) and thermal (TNO) Si-oxynitride devices having varying EOT. Threshold voltage shift and its field, temperature and time dependence obtained from no-delay on-the-fly I_DLIN measurements are carefully compared to that obtained from Charge Pumping. It is shown that thin and thick PNO and thin TNO devices show very similar NBTI behavior, which can primarily be attributed to generation of interface traps. Thicker TNO devices show different NBTI behavior, and can be attributed to additional contribution from hole trapping in pre-existing bulk traps. A physics based model is developed to analyze and explain the experimental results.

1.2 ESTIMATION OF NBTI DEGRADATION USING ON-CHIP IDDQ MEASUREMENT—K. Kang, M.A. Alam, and K. Roy, Purdue Univ., West Lafayette, IN

Temporal NBTI degradation can severely affect the lifetime functionality of CMOS digital circuits. An efficient NBTI characterization method using on-chip IDDQ measurement is proposed. It is shown that temporal degradation of fMAX and IDDQ is highly correlated. This relationship can be used to predict circuit lifetime reliability.

1.3 ON THE INTERACTION OF ESD, NBTI AND HCI IN 65 nm TECHNOLOGY—R. Mishra, George Mason Univ., Fairfax, VA, S. Mitra, R. Gauthier, IBM, Essex Junction, VT, D.E. Ioannou, George Mason Univ., Fairfax, VA, D. Kontos, K. Chatty, C. Seguin, R. Halbach, IBM, Essex Junction, VT

This paper presents the results of a study on the interaction between ESD, NBTI and HCI in silicide-blocked PMOSFETs fabricated in 65 nm technology. ESD pre-stressing enhances NBTI-induced device degradation. At elevated temperatures, pure NBTI dominates in longer channel devices, whereas HC-NBTI dominates in minimum channel length devices.

1.4 (invited) SRAM VARIABILITY AND SUPPLY VOLTAGE SCALING CHALLENGES—R. Kapre, Cypress Semiconductor

We will present an overview of the challenges experienced during development of a state-of-the-art 65 nm SRAM technology featuring a 0.48 µm² SRAM cell. Transistor and layout variability are put into perspective to random dopant fluctuations and cell stability. We will present a novel concept of operational margin to ensure yield over design, process variability and transistor reliability.

1.5 QUANTITATIVE ANALYSIS OF RANDOM TELEGRAPH SIGNALS AS FLUCTUATIONS OF THRESHOLD VOLTAGES IN SCALED FLASH MEMORY CELLS—H. Miki, T. Osabe, N. Tega, A. Kotabe, H. Kurata, Hitachi, Ltd., Tokyo, Japan, K. Tokami, Y. Ikeda, S. Kamohara, Renesas Technology, Tokyo, Japan, and R. Yamada, Hitachi, Ltd., Tokyo, Japan

Random telegraph signals (RTS) in fluctuations of threshold voltage are analyzed using massive readout data in scaled flash memories. All of the parameters were found to follow log-normal distribution, and to show weak mutual dependence. Possible origins of the distributions are also discussed.

Tuesday, April 17, 2:00 p.m., Room A

SESSION 2A HIGH-K

Co-Chairs: Michel Houssa, IMEC and Eduard Cartier, IBM

2A.1 (invited) DIELECTRIC BREAKDOWN IN HIGH-k GATE DIELECTRICS: MECHANISM AND LIFETIME ASSESSMENT—K. Okada, H. Ota, MIRAI-ASRC-AIST, Tsukuba, Japan, T. Nabatame, and A. Toriumi, MIRAI-ASRC-AIST & Univ. of Tokyo, Toyko, Japan

Establishing accurate reliability models for high-k gate dielectrics is crucial for their introduction in device production. In this paper, it is shown that the breakdown mechanism of high-k gate dielectrics can be quantitatively understood by the generated subordinate carrier injection (GSCI) model, allowing accurate lifetime predictions at operating condition.

2A.2 (withdrawn)

2A.3 NEW UNDERSTANDING ON THE BREAKDOWN OF HIGH k DIELECTRICS USING MULTI-VIBRATIONAL HYDROGREN RELEASE MODEL—M. Rafik, STM & IMEP, G.Ribes, STM, Crolles, France, D. Roy, and G. Ghibaudo, IMEP Grenoble, France

It is demonstrated that the Multi-Vibrational Hydrogen Release (MVHR) model can not be applied to dielectric breakdown in HfO₂ dielectric stacks in substrate injection mode because no Si-H bonds are present in HfO₂. However, for HfSiON gate stacks it is found that the MVHR can be used because of the presence of Si-H bonds.

2A.4 PROGRESSIVE BREAKDOWN CHARACTERISTICS OF HIGH-k/METAL GATE STACKS—G. Bersuker, N. Chowdhury, C. Young, D. Heh, and R. Choi, Sematech, Austin, TX

Breakdown characteristics of HfO₂ gate stacks under inversion stress was investigated in a wide thickness range. A strong correlation between SILC and interface traps suggests that breakdown is triggered by trap generation in the interfacial SiO₂ layer. Using differential resistance, breakdown is identified as being progressive.

2A.5 DEFECTS GENERATION IN SiO₂/HfO₂ STUDIED WITH VARIABLE T_charge-T_discharge CHARGE PUMPING (VT²CP)—M.B. Zahid, Liverpool John Moores Univ., UK, R. Degraeve, L. Pantisano, IMEC, Leuven, Belgium, J.F. Zhang, Liverpool John Moores Univ., UK, G. Groeseneken, IMEC, Leuven, Belgium & Catholic Univ. Leuven, Belgium

A variant of the Charge Pumping (CP) method with variable T_charge- and T_discharge times (VT²CP) is used to separate trap creation in the SiO₂ interlayer and in the HfO₂ dielectric. The creation of HfO₂ traps is shown to correlate with the voltage acceleration for TDDB, suggesting that breakdown occurs at a critical HfO₂ trap density.

2A.6 IN DEPTH ANALYSIS OF Vt INSTABILITIES IN HfO₂ TECHNOLOGIES BY CHARGE PUMPING MEASUREMENTS AND ELECTRICAL MODELING—X. Garros, CEA-Leti, Grenoble, France, J. Mitard, STM, Crolles, France, C. Leroux, G. Reimbold, and F. Boulanger, CEA-Leti, Grenoble, France

The Vt instability in HfO₂ gate stacks is measured by two methods: Charge Pumping (CP) and pulsed IdVg measurements. The results from both methods are shown to agree well. Results for both methods are modeled in terms of the spatial location and the energy distribution of the HfO₂ traps, revealing a strong defect band 0.9eV below the HfO₂ conduction band edge.

2A.7 COMPARISON OF PLASMA-INDUCED DAMAGE IN SiO₂/TiN AND HfO₂/TiN GATE STACKS—C.D. Young, G. Bersuker, Sematech, F. Zhu, Univ. of Texas, Austin, TX, K. Matthews, ATDF, Austin, TX, R. Choi, S.C. Song, H.K. Park, GIST, Korea, J.C. Lee, Univ. of Texas, Austin, TX, and B.H. Lee, IBM assignee to Sematech, Austin, TX

SiO₂ and HfO₂ gate dielectrics with TiN electrodes were subjected to an aggressive post-fabrication plasma exposure. The plate antennae structures demonstrate evidence of plasma-induced damage. While, the physical origin of PD in SiO₂ devices was found to be the amphoteric interface states, the primary effect in HfO₂ devices was charges trapped in the bulk of the high-k film.

Tuesday, April 17, 2:00 p.m., Room B

SESSION 2B PRODUCT & CIRCUIT RELIABILITY I

Co-Chairs: Walter Riordan, Intel and Tom Anderson, Texas Instruments

2B.1 KINETIC ANALYSIS OF X-RAY IRRADIATION INDUCED STATIC REFRESH FAILURE MECHANISM IN DRAM—A. Ditali, M. Ma, B. Black, Micron Technology, Boise, ID, S.-J. Wen, S. Chung, Cisco System, San Jose, CA

The vulnerability of DRAM to low dose x-ray irradiation levels typical in inspection systems are presented for several DRAM vendors. Fail rates are PPM level. Damage is manifested as increase in junction leakage of storage node cell. The GIDL component of the memory cell appeared to be insensitive to X-Rays. Thermal annealing did lead to recovery in Ij, however, a complete recovery was not observed even at high temperatures.

2B.2 MACRO-MODEL FOR POST-BREAKDOWN 90 nm AND 130 nm TRANSISTORS AND ITS APPLICATIONS IN PREDICTING CHIP-LEVEL FUNCTION FAILURE AFTER ESD-CDM EVENTS—T.W. Chen, Stanford Univ., Stanford, CA, C. Ito, W. Loh, LSI Logic, Milpitas, CA, W. Wang, and R.W. Dutton, Stanford Univ., Stanford, CA

A post-breakdown transistor macro-model for 90 nm and 130 nm technologies is presented and experimentally verified. Oxide breakdown does not necessarily imply function failure, which is dependent on the location of the breakdown on a circuit level. A simulation methodology implementing this macro-model is presented. This tool can be used to predict function failure of three different System-on-Chip (SoC) designs. Simulations agree well with Failure Analysis (FA) observations, verifying the validity of the macro-model.

2B.3 DEGRADATION MECHANISMS IN CMOS POWER AMPLIFIERS SUBJECT TO RADIO-FREQUENCY STRESS AND COMPARISON TO THE DC CASE—C.D. Presti, F. Carrara, Università degli Studi di Catania, Catania, Italy, A. Scuderi, STM, Catania, Italy, S. Lombardo, IMM, Catania, Italy, and G. Palmisano, Università degli Studi di Catania, Catania, Italy

Degradation dynamics in CMOS power amplifiers was studied. The transistor was operated at 1.9 GHz under real-world conditions. Experiments demonstrated that damage severity strongly depends on drain waveforms, rather than on dissipated power. Large discrepancies are found between RF stress measurement results and quasi-static models derived from F-N and hot carrier tests.

2B.4 (late) REALISTIC PROJECTIONS OF PRODUCT Fmax SHIFT AND STATISTICS DUE TO HCI AND NBTI—A. Haggag, M. Lemanski, G. Anderson, P. Abramowitz, and M. Moosa, Freescale, Austin, TX

Product Fmax shift is shown to be mainly due to HCI and NBTI. This is because the likelihood of a TDDB event in the product speed path is negligible. An exponential drain current and voltage dependence of HCI and a power-law gate voltage dependence of NBTI are shown to fit the Fmax shift quite well for realistic guardbands.

Tuesday, April 17, 4:05 p.m., Room B

SESSION 2C ASSEMBLY & PACKAGING

Co-Chairs: Sidharth, AMD and Rajen Dias, Intel

2C.1 THE IMPACT OF BALL-BONDING (BB) INDUCED VOLTAGE TRANSIENT ON SUB-90 nm CMOS TECHNOLOGY—J.-H. Lee, J.R. Shih, B.L. Lin, P.-K. Niu, J. Wang, C.-H. Tang, A.S. Oates, and K. Wu, TSMC, Hsin-Chu, Taiwan

Impact of Ball Bond induced voltage transient on reliability including EM, TDDB, NBTI, and ESD are investigated. During the ball bonding process, a spark discharge current applies a high electric field and also charges up the potential of the wire. BB-induced voltage transient can be treated as a low current and low voltage stress event and may impact device lifetime if without protection circuitry.

2C.2 ON THE PHYSICS OF FAILURE IN THE CASE OF MOISTURE INDUCED DELAMINATION IN PLASTIC ENCAPSULATED MICROELECTRONIC DEVICES—K.C. Lee, Infineon Technologies Asia Pacific Pte Ltd, Singapore and P. Alpern, Infineon Technologies AG, Neubiberg, Germany

By using the moisture concentration at the weakest material interface as the critical parameter for the defect onset, the quantitative prediction of moisture induced delamination between molding compound and die surface in plastic packages is realized. A generalized case of delamination onset during multiple soaks and reflow process, as prescribed by the EIAJ ED-4701/300 standard, was predicted and validated from the IPC/JEDEC J-STD-020C moisture sensitivity level.

2C.3 IDENTIFICATION OF BRITTLE SOLDER JOINTS USING HIGH STRAIN RATE TESTING OF BGA SOLDER JOINTS—R. Pandher and M. Boureghda, Cookson Electronics, Jersey City, NJ

A solder joint failing due to mechanical shock is a critical issue for portable electronics. This paper deals with a high-speed ball pull test to differentiate the brittle nature of solder joints from ductile. Data will be presented on lead-free solder (Sn-Ag-Cu alloys SAC 105 and 305) under different reflow profiles and after aging.

2C.4 A STUDY ON WIRE BALL/PAD OPEN FAILURE MECHANISM OF A MULTI-STACK PACKAGE (MSP) UNDER HIGH TEMPERATURE STORAGE (HTS) CONDITION—S.Y. Yang, H.-J. Byun, S.-W. Park, and W.-J. Lee, Samsung Electronics Co., Hwasung-City, Korea

The failure mechanism of wire ball/pad open failure that occurs at gold wire and bonding pad interface of a multi-stack package (MSP) under high temperature storage (HTS) condition, 150°C, is verified to be tensile (pull-off) stress imposed on gold wires and bond weakening process due to metallic diffusion and corrosion. Engineering works conducted to verify such factors are included.

Tuesday, April 17, 2:00 p.m., Room C

SESSION 2D INTERCONNECTS I

Co-Chairs: Baozhen Li, IBM and Amit Marathe, AMD

2D.1 ANALYTICAL STUDY OF IMPURITY DOPING EFFECTS ON ELECTROMIGRATION OF Cu INTERCONNECTS BY EMPLOYING COMPREHENSIVE SCATTERING MODEL—S. Yokogawa, Y. Kakuhara, H. Tsuchiya, and K. Kikuta, NEC Electronics, Kanagawa, Japan

We investigated the impurity doping effect on resistivity with decomposition into surface, grain boundary, and impurity scattering factors by employing comprehensive scattering model. The surface scattering is dominant for resistivity increasing, while EM-induced Cu drift is suppressed as Al concentration increasing. EM lifetime is improved by suppression of the Cu diffusion due to piled-up Al at the top surface of Cu interconnects.

2D.2 PLASTICITY-AMPLIFIED DIFFUSIVITY: DISLOCATION CORES AS FAST DIFFUSION PATHS IN Cu INTERCONNECTS—A.S. Budiman, Stanford Univ., Stanford, CA, C.S. Hau-Riege, P.R. Besser, A. Marathe, AMD, Sunnydale, CA, Y.-C. Joo, Seoul National Univ., Seoul, Korea, N. Tamura, J.R. Patel, LBNL, Berkeley, CA, and W.D. Nix, Stanford Univ., Stanford, CA

The diffusivity (D) of Cu during EM testing is typically dominated by interface diffusion. If a mechanism other than interface diffusion begins to affect the overall diffusion process, effectively D of the EM process would deviate from that of interface diffusion only. We have preliminary evidence that it could be the case, and report its implications for EM lifetime assessment.

2D.3 Cu INTERCONNECT WIDTH EFFECT, MECHANISM AND RESOLUTION ON DOWN-STREAM STRESS ELECTROMIGRATION—Y.L.Cheng, B.L. Lin, S.Y. Lee, C.C. Chiu, and K. Wu, TSMC, Hsinchu, Taiwan

Experiments were performed to study the effect of line width and stress current direction on electromigration. For down-stream stress, two distinct failure modes, via bottom and metal line depletion, were found. The difference between the failure times of each failure mode becomes larger as metal width increases. We propose enlarging via size and enhancing Cu/cap interface to improve the EM distribution.

2D.4 DESIGN FOR MANUFACTURABILITY AND ITS ROLE IN ENHANCING STRESS MIGRATION RELIABILITY OF POROUS ULTRA LOW-k COPPER INTERCONNECTS—Y.K. Lim, Chartered Semiconductor Mfg. Ltd., & Nanyang Tech. Univ., Singapore, K.L. Pey, P.S. Lee,Y.H. Lee, Nanyang Tech. Univ., Singapore, N.R. Kamat, J.B. Tan, T. Fu, and L.C. Hsia, Chartered Semiconductor Mfg. Ltd., Singapore

Process and structural improvements are important in coping with increasing SM reliability challenges. Early implementation of simulation model for reliability physics study and the subsequent DFM are important considerations for device reliability community to study sub-45 nm CMOS devices as significant cost in performing SM related failure study will be reduced.

Tuesday, April 17, 4:05 p.m., Room C

SESSION 2E MICROELECTRONICS IN EXTREME ENVIRONMENTS

Chair: Donald C. Mayer, The Aerospace Corp.

2E.1 (invited) SiGe BiCMOS TECHNOLOGY: AN IC DESIGN PLATFORM FOR EXTREME ENVIRONMENT ELECTRONICS APPLICATIONS—J.D. Cressler, Georgia Tech, Atlanta, GA

Commercially-available silicon-germanium (SiGe) BiCMOS IC technology offers inherent total dose radiation tolerance, wide temperature range operational capability, and optimal monolithic mixed-signal circuit design flexibility using power efficient, high-speed SiGe HBTs on the same silicon wafer with CMOS and a suite of passive components. An IC design platform to support the development of lunar electronics components designed to operate under extreme environmental conditions will be discussed.

2E.2 (invited) UNDERSTANDING TiN PLASMAS: A NEW APPROACH TO TiN WHISKER RISK ASSESSMENT—M. Mason and G. Eng, The Aerospace Corporation, Los Angeles, CA

We discuss the mechanisms governing sustained plasma formation from tin whiskers in vacuum and at atmospheric pressure. We qualitatively model plasma voltage and current signatures and derive engineering estimates for tin plasma risk as a function of voltage. The tin plasma risk at one atmosphere may be comparable to, or worse than, the known high risk in vacuum.

2E.3 CRYOGENIC RELIABILITY IMPACT ON ANALOG CIRCUITS AT EXTREME LOW TEMPERATURES—Y. Chen, JPL, Pasadena, CA, L. Westergard, C. Billman, AMIS, Pocatello, ID, R. Leon, T. Vo, and M. White, JPL, Pasadena, CA

Hot carrier lifetime at low temperatures depends on bias conditions within the circuit. The combination of low temperature and low bias during characterization of a commercial 0.35 µm CMOS technology can yield large parametric degradation, which can reduce NMOS hot carrier lifetime by a factor of 70 from 300K to 20K. Analog gain tolerance and offset voltage may also have more bias dependence at low temperatures.

Wednesday, April 18, 8:00 a.m., Room A

SESSION 3A MEMORY I

Co-Chairs: Chandra Mouli, Micron and Renichi Yamada, Hitachi

3A.1 STATISTICAL INVESTIGATION OF RANDOM TELEGRAPH NOISE Id INSTABILITIES IN FLASH CELLS AT DIFFERENT INITIAL TRAP-FILLING CONDITIONS—C.M. Compagnoni, R. Gusmeroli, A.S. Spinelli, A.L. Lacaita, M. Bonanomi, and A. Visconti, DEI-Politecnico di Milano, Milano, Italy

We investigate the impact of a pre-read gate bias on the cell drain current (Id) fluctuations due to random telegraph noise in Flash memories. We show that RTN Id instabilities depend on the applied gate bias as a result of different initial trap filling conditions. A statistical model is presented to identify the traps involved in the RTN process.

3A.2 EFFECTS OF LATERAL CHARGE SPREADING ON THE RELIABILITY OF TANOS-NAND FLASH MEMORY—C. Kang, J. Choi, J. Sim, J. Park, Y. Shin, C. Lee, J. Sel, Y. Park, and K. Kim, Samsung Electronics Co., Yongin-City, Korea

The charge loss behavior of TANOS (TaN-Al₂O₃-Nitride-Oxide-Silicon) cells for NAND Flash memory application is studied. Lateral charge spreading via trap layers from programmed cells to adjacent erased cells is shown to be an important factor for data retention in TANOS cells.

3A.3 RELIABILITY AND PROCESSING EFFECTS OF BANDGAP ENGINEERED SONOS (BESONOS) FLASH MEMORY—S.-Y. Wang, H.-T. Lue, E.-K. Lai, L.-W. Yang, T. Yang, K.-C. Chen, J. Gong, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, Macronix Int'l, Hsinchu, Taiwan

Reliability characteristics of BE-SONOS Flash device, is studied in this paper. By employing a multi-layer bandgap-engineered tunneling barrier, efficient hole tunneling erase with low direct tunneling leakage is achieved, overcoming fundamental limitations in conventional SONOS for fast erase and good data retention.

3A.4 A NOVEL GATE-SENSING AND CHANNEL-SENSING TRANSIENT ANALYSIS METHOD FOR REAL-TIME MONITORING OF CHARGE VERTICAL LOCATION IN SONOS-TYPE DEVICES AND ITS APPLICATIONS IN RELIABILITY STUDIES—H.-T. Lue, P.-Y. Du, S.-Y. Wang, E.-K. Lai, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, Macronix Int'l, Hsinchu, Taiwan

A novel transient analysis method is presented to monitor the location of trapped charge in SONOS-type devices. This new technique is applied to study charge-trapping efficiency, charge migration dynamics during program/erase cycling, data retention and reliability characteristics.

3A.5 DEVELOPMENT AND OPTIMIZATION OF RE-OXIDIZED TUNNEL OXIDE WITH NITROGEN INCORPORATION FOR THE FLASH MEMORY APPLICATION—J.-G. Jee, W.H. Kwon, W. Lee, J.-H. Park, H.-K. Kim, H.-M. Son, W.-J. Chang, J.-J. Han, Y.-W. Hyung, and H.-D. Lee, Samsung Electronics Co., Ltd, Yongin-City, Korea

The re-oxidized tunnel oxide was developed to improve flash device reliability. Post-cycling Vth shifts (Endurance) and post cycling bake was improved compared to conventional NO annealed oxide.

3A.6 INFLUENCE OF HYDROGEN PERMEABILITY OF LINER NITRIDE FILM ON PROGRAM/ERASE ENDURANCE OF SPLIT-GATE TYPE FLASH EEPROMS—Z. Liu, S. Fujieda, F. Hayashi, M. Shimizu, M. Nakata, H. Ishigaki, NEC Corp., Kanagawa, Japan, M. Wilde, and K. Fukutani, Univ. of Tokyo, Tokyo, Japan

H-diffusion into the tunnel oxide was proven to degrade the P/E endurance of split-gate type Flash memories through generation of interface traps and negative charges. Assessing the H-permeability of liner nitride films by nuclear reaction analysis, we study the influence of nitride film properties on P/E endurance.

Wednesday, April 18, 8:00 a.m., Room B

SESSION 3B DIELECTRICS

Co-Chairs: Ernest Wu, IBM and Frederic Monsieur, STM

3B.1 (invited) THE CURRENT UNDERSTANDING OF THE TRAP GENERATION MECHANISMS THAT LEAD TO THE POWER LAW MODEL FOR GATE DIELECTRIC BREAKDOWN—P. E. Nicollian, A. T. Krishnan, C.A. Chancellor, R.B. Khamankar, S. Chakravarthi, C. Bowen, and V.K. Reddy, Texas Instruments, Dallas, TX

This paper reviews recent experiments that have shown that the probable mechanism for trap generation and breakdown at low voltages in ultra thin dielectrics is anode hydrogen release. Vibrational excitation of silicon-hydrogen bonds is the process that provides the most plausible explanation for the existence of a power law model for TDDB.

3B.2 QUANTUM MECHANICAL TREATMENT OF Si-O BOND BREAKAGE IN SILICA UNDER TIME DEPENDENT DIELECTRIC BREAKDOWN TESTING—J.W. McPherson, Texas Instruments, Dallas, TX

A quantum mechanical treatment of Si-O bond breakage in silica is presented under the conditions of high electric field, hole injection, and hydrogen release. When the full spectrum of the bound-state energy eigenvalues for the Si-ion are considered, it is shown that, due to the width of the potential energy barrier separating the 4-fold and 3-fold coordinated bonded positions, the tunneling probability is relatively small and the transmission probability is described well by thermionic emission.

3B.3 LIFETIME PREDICTION FOR CMOS DEVICES WITH ULTRA THIN GATE OXIDES BASED ON PROGRESSIVE BREAKDOWN—A. Kerber, Qimonda AG, Munich, Germany, M. Röhner, T. Pompl, R. Duschl, and M. Kerber, Infineon Technologies AG, Munich, Germany

Progressive Breakdown observed in CMOS devices with ultra thin gate oxides can significantly increase the time dependent dielectric breakdown (TDDB) reliability margin of digital CMOS products. The voltage acceleration, the failure distribution of the progressive breakdown and the methodology for quantification of the progressive breakdown is discussed. Extensive experimental data are provided, enabling its implementation.

3B.4 SIGNIFICANCE OF BREAKDOWN LOCATION ON POST-BREAKDOWN TRANSIENT AND MOSFET DEGRADATION—K.L. Pey, T.A.L Selvarajoo, Nanyang Technological Univ., Singapore, C.H. Tung, Institute of Microelectronics, Singapore, D.S. Ang, and V.L. Lo, Nanyang Technological Univ., Singapore

Abstract: Progressive breakdown of ultra-thin gate dielectrics is found to be strongly dependent on breakdown location in channel of MOSFETs. Breakdown near center of channel have a dIG/dt of 1-2 orders of magnitude smaller than that near source/drain diffusion/breakdown location has a strong impact on gate oxide lifetime projection.

3B.5 RE-CONSIDERATION OF HYDROGEN-RELATED DEGRADATION MECHANISM IN GATE OXIDES—Y. Mitani, T. Yamaguchi, H. Satake, and A. Toriumi, Toshiba Corp., Isogo-ku, Japan

In this paper, correlation between released hydrogen from Si/SiO2 interface and SILC was investigated using thick (~6nm) gate oxides. As a result, SILC is clearly observed after low voltages NBT stress. In addition, the SILC is suppressed by decreasing released hydrogen using fluorine incorporation in both pMOSFETs and nMOSFETs. From these results, it can be concluded that hydrogen release might be common origin for both NBTI and SILC.

3B.6 (late) ANALYTIC EXTENSION OF THE CELL-BASED OXIDE BREAKDOWN MODEL TO FULL PERCOLATION AND ITS IMPLICATIONS—A.T. Krishnan and P.E. Nicollian, Texas Instruments , Dallas, TX

We extend the cell-based approach of Su�� to full percolation that is predictive down to 0.4nm. We resolve conflicting reports in the literature on the scaling behavior of the Weibull shape parameter with oxide thickness, and show that Weibull statistics can be violated if pre-existing traps are present.

Wednesday, April 18, 8:00 a.m., Room C

SESSION 3C ORGANICS

Co-Chairs: David Gundlach, NIST and Sue Carter, UC Santa Cruz

3C.1 (two slots) (invited) DEFECTS IN ORGANIC MOLECULAR CRYSTALS: SPECTROSCOPY AND EFFECTS ON ELECTRONIC AND OPTICAL PROPERTIES—O. Mitrofanov, Bell Laboratories, Alcatel-Lucent, Murray Hill, NJ

Transport and optical properties of organic molecular crystals depend on the presence and distribution of crystallographic defects. In this paper we overview the impact of defects on properties of single crystal rubrene, an organic material with the highest to date hole mobility. We show that the defects strongly affect the mobility and carrier concentration in rubrene.

3C.2 (two slots) (invited) BIAS STRESS EFFECTS IN ORGANIC FIELD-EFFECT TRANSISTORS—T.N. Ng, Palo Alto Research Center, Palo Alto, CA

Device instability and limited lifetime have been the hurdles to commercialization of organic electronics. Through electrical characterizations and microscopy techniques, much progress has been made in understanding gate bias stress that limits the stability of organic field-effect transistors. The kinetics and mechanisms of charge trapping in organic semiconductors are examined to explain the bias-stress behaviors. The external processing factors, such as dielectric treatments and environmental conditions that affect the severity of bias stress, are also investigated to enable controllable and reproducible device fabrication.

3C.3 (two slots) (invited) MECHANISMS OF OPERATION AND DEGRADATION IN SOLUTION-PROCESSABLE ORGANIC PHOTOVOLTAICS—S. Shaheen, National Renewable Energy Laboratory, Golden, CO

Efficiencies of organic photovoltaic (OPV) devices are approaching values than can be considered for initial commercial application. A large concern is the device lifetime, which is a poorly understood but critical aspect in the pathway to commercialization. This paper will introduce the basic working mechanisms of OPV devices and outline issues in degradation such as interface degradation, morphology changes, and oxidation.

3C.4 (two slots) (invited) OLED DEVICE OPERATIONAL LIFETIME: INSIGHTS AND CHALLENGES—S. Xia, Universal Display Corporation, Ewing, NJ

This paper discusses some of the most important intrinsic and extrinsic factors that affect the organic light-emitting devices (OLEDs) stability. OLEDs lifetime can be greatly improved through materials design by improving the redox properties, thermal properties, and charge transporting properties. Extrinsic factors, such as materials purity, are also discussed.

Wednesday, April 18, 1:35 p.m., Room A

SESSION 4A TRANSISTORS

Co-Chairs: Anand Krishnan, Texas Instruments and Souvik Mahapatra, IIT Mumbai

4A.1 BALLISTIC PHONON ENHANCED NBTI—Y. Wang, K.P. Cheung, Rutgers Univ., Piscataway, NJ, A.S. Oates, TSMC, Hsinchu, Taiwan, and P. Mason, Agere Systems, Allentown, PA

In sub-100 nm cmos technology where the transistor channel lengths are smaller than the phonon scattering mean-free-path, a new kind of drain junction heating problem arises due to ballistic phonon effect. The impact of this new heating phenomenon on long term reliability of transistor is examined for the first time here. We show that nbti in pmos is severely worsened.

4A.2 MECHANISM AND MODELING OF PMOS NBTI DEGRADATION WITH DRAIN BIAS—Y. Luo, J. Orona, D. Nayak, and D. Gitlin, Xilinx Inc., San Jose, CA

A new mechanism is presented for PMOS NBTI with drain bias to explain the turn-around behavior of device degradation. While drain bias reduces gate oxide voltage and causes less NBTI, the enhancement from channel-hot-hole causes more device degradation. For the first time, a semi-empirical model is proposed that fits well with the experimental data, including different effects.

4A.3 THE UNIVERSALITY OF NBTI RELAXATION AND ITS IMPLICATIONS FOR MODELING AND CHARACTERIZATION—T. Grasser, W. Gos, V. Sverdlov, TU Wien, Wien, Austria, and B. Kaczer, IMEC, Leuven, Belgium

We show that NBTI relaxation follows a universality that is much more general than previously anticipated. It is shown that this universal relaxation applies to both on-the-fly and standard measurements and forms a link between various delay times. We then use this universality to benchmark existing NBTI models. Our results indicate that the relaxation behavior is still not fully understood.

4A.4 CORRECTION OF SELF-HEATING FOR HCI LIFETIME PREDICTION—J.M. Roux, STM, Crolles, France, X. Federspiel, NXP, Crolles, France, D. Roy, STM, Crolles, France, P. Abramowitz, Freescale Semiconductor

The integration of buried oxide in SOI technology enhances self-heating in MOS transistor devices. Here, we have characterized self-heating in transistors with various gate widths, using gate resistance methodology. The resulting self-heating model was used to build HCI extrapolation model taking into account VD and width effect on channel temperature.

4A.5 CONSIDERATION OF RECOVERY EFFECTS DURING NBTI MEASUREMENTS FOR ACCURATE LIFETIME PREDICTIONS OF STATE-OF-THE-ART PMOSFETs—C. Schlünder, W. Heinrigs, W. Gustin, and H. Reisinger, Infineon Technologies AG, Munich, Germany

We investigate the impact of delay times from 1 µs up to 60s and stress times from 100 ms up to 250000s on lifetime estimates. A correlation between stress time, delay time induced recovery and error in predicted lifetime is elaborated for the first time. Furthermore we give simple guidelines for measurement requirements and essential stress times for accurate lifetime evaluations.

Wednesday, April 18, 4:05 p.m., Room A

SESSION 4B SER

Chair: Ken Rodbell, IBM

4B.1 (two slots) (invited) SEU AND SET MODELING AND MITIGATION IN DEEP SUBMICRON TECHNOLOGIES—D.G. Mavis, Micro-RDC, Albuquerque, NM

As technology feature sizes decrease, single event upset, single event transient, and multiple bit upset effects dominate the radiation response of microcircuits. New modeling approaches are presented which, for the first time, account for experimentally observed heavy-ion induced transient widths. Novel hardening and mitigation approaches are proposed based on our new understanding of the circuit response mechanisms.

4B.2 SINGLE EVENT UPSETS IN A 130 nm HARDENED LATCH DESIGN DUE TO CHARGE SHARING—O.A. Amusan, A.L. Sternberg, A.F. Witulski, B.L. Bhuva, J.D. Black, Vanderbilt Univ., Nashville, TN, M.P. Baze, Boeing Co., Seattle, WA, and L.W. Massengill, Vanderbilt Univ., Nashville, TN

Circuit and 3D TCAD mixed-mode simulations show that the SEU vulnerability of a 130 nm hardened latch to low LET particles is due to charge sharing between multiple nodes as a result of a single ion strike. The low LET vulnerability of the hardened latch is verified experimentally.

4B.3 EXPERIMENTAL CHARACTERIZATION AND APPLICATION OF CIRCUIT ARCHITECTURE LEVEL SINGLE EVENT TRANSIENT MITIGATION—K.C. Mohr and L.T. Clark, Arizona State Univ., Tempe, AZ

Experimental characterization of single event transient performance as a function of node capacitance and drive strength for a 130 nm process is presented. Use of this data to improve soft error performance without increasing design size and the effect on integrated circuit active power is described.

4B.4 RANDOM DOPANT EFFECT ON Vt VARIATIONS AFFECTING THE SOFT-ERROR RATES OF NANOSCALE CMOS MEMORY CELLS—A. Balasubramanian, A.L. Sternberg, B.L. Bhuva, S. Kalemeris, and L.W. Massengill, Vanderbilt Univ., Nashville, TN

As technologies scale, random dopant fluctuations (RDF) cause increasingly significant threshold voltage (Vt) variations. This invalidates the assumption of a single value for the critical charge (Qcrit) in SRAM cells and results in another layer of statistical spread in Qcrit.

Wednesday, April 18, 1:35 p.m., Room B

SESSION 4C ESD & LATCHUP

Co-Chairs: Elyse Rosenbaum, Univ. of Illinois and Gianluca Boselli, Texas Instruments

4C.1 (invited) SURVEY ON VERY FAST TLP AND ULTRA FAST REPETITIVE PULSING FOR CHARACTERIZATION IN THE CDM-DOMAIN—H.A. Gieser and H. Wolf, Fraunhofer Institute for Reliability and Microintegration IZM, Munich, Germany

Charged Device Model pulses may be less than 1 ns wide with peak currents exceeding 10 A. They are a true challenge for the ESD protection of advanced technologies with shrinking safety margins. This paper surveys the characterization with very fast rising single shot TLP pulses and repetitive medium voltage techniques with ps-risetimes necessary to meet the CDM-goals.

4C.2 EFFECTS OF BACKGROUND DOPING CONCENTRATION ON ESD PROTECTION PROPERTIES OF HIGH VOLTAGE OPERATION EXTENDED DRAIN N-TYPE MOSFET DEVICE.—K.-H. Kim, Leadis Technology, Kyungki-do, S. Korea, Y.-J. Seo, Daebul Univ., Chonanm-do, S. Korea, and W.-J. Choi, Leadis Technology, Kyungki-do, S. Korea

The effects of background doping concentration (BDC) on the ESD performance of a high voltage operating, extended drain N-type MOSFET (EDNMOS) device were investigated. Devices with low BDC undergo a second snapback, upon which current localization and thermal failure occur. EDNMOS with high BDC avoid second snapback and provide good ESD protection.

4C.3 DRAIN EXTENDED NMOS HIGH CURRENT BEHAVIOR AND ESD PROTECTION STRATEGY FOR HV APPLICATIONS IN SUB-100 nm CMOS TECHNOLOGIES—G. Boselli, V. Vassilev, and C. Duvvury, Texas Instruments, Dallas, TX

The high current behavior of drain extended NMOS (DeNMOS) transistors in 65 nm technology is investigated. A sufficient level of ESD protection, approximately 2 mA/mm, can be achieved through substrate biasing. This concept is exploited to build robust ESD protection.

4C.4 EVALUATION OF SCR-BASED ESD PROTECTION DEVICES IN 90 nm AND 65 nm CMOS TECHNOLOGIES—J. Di Sarro, Univ. of Illinois, Urbana, IL, K. Chatty, R. Gauthier, IBM, Essex Jct., VT, and E. Rosenbaum, Univ. of Illinois, Urbana, IL

Using a consistent layout style, promising SCR designs for low voltage technologies are compared in 90 and 65 nm bulk CMOS technologies. The metrics used are trigger voltage, trigger current, on-resistance, turn-on time, and dc leakage current. It is reported that SCR turn-on time depends on the amplitude of the applied pulse.

4C.5 EXTERNAL LATCHUP CHARACTERISTICS UNDER STATIC AND TRANSIENT CONDITIONS IN ADVANCED BULK CMOS TECHNOLOGIES—D. Kontos, R. Gauthier, K. Chatty, IBM, Essex Junction, VT, K. Domanski, Infineon Technologies, Munich, Germany, M. Muhammad, C. Seguin, and R. Halbach, IBM, Essex Junction, VT

Transient current and voltage characteristics are presented for external latchup test structures that are triggered by 100 ns TLP. Test structures with a variety of different design and process configurations are fabricated in 65 nm technology. Detector topology, injector to detector spacing, second guard-ring protection scheme, and the effects of substrate resistivity are investigated.

Wednesday, April 18, 4:05 p.m., Room B

SESSION 4D PROCESS INTEGRATION RELIABILITY

Co-Chairs: Sanjay Rangan, Intel and Vijay Reddy, Texas Instruments

4D.1 PLASMA DAMAGE ENHANCED TRANSISTOR RELIABILITY DEGRADATION—W.T. Weng, J.C. Lin, and A.S. Oates, TSMC, Hsinchu, Taiwan

This paper demonstrates the impact of antenna ratio, transistor active area and gate oxide thickness on hot carrier reliability and NBTI. A model to explain the observed experimental dependences to accurately simulate complete failure distributions in the presence of plasma damage is also discussed.

4D.2 STUDY OF PLASMA DAMAGE AT RECESS-CHANNEL GATE (RG) STRUCTURE DURING PLASMA NITRIDATION—H.-J. Cho, T.-Y. Kim, S.-A. Jang, H. Ahn, Y.S. Kim, K.-Y. Lim, M.G. Sung, H.-S. Yang, S.-H. Phy, and J.W. Kim, Hynix Semiconductor, Ichon-si, Korea

The plasma damage of gate oxide was investigated at the recess-channel gate(RG) cell structure during plasma nitridation. The degradation behavior of 3D RG cell structure was different from that of 2D planar structure. The model of electron shading can explain the 3D structure dependence of the plasma damage.

4D.3 IMPACT OF THE BOTTOM INTERFACIAL LAYER ON THE THRESHOLD VOLTAGE AND DEVICE RELIABILITY OF FLUORINE INCORPORATED PMOSFETs WITH HIGH-k/METAL ELECTRODE—K. Choi, Sematech, Austin, TX, T. Lee, S. Kweon, Univ. of Texas, Austin, TX, C.D. Young, H. Harris, R. Choi, S.C. Song, Sematech, Austin, TX, B.H. Lee, and R. Jammy, IBM assignee Sematech, Austin, TX

A combination of F implantation and a high quality bottom interfacial layer is applied in an attempt to improve device characteristics of metal/AlN/high-k gate stacks for PFET devices. Results show that F combined with a thermally grown bottom interface significantly reduces threshold voltage (Vth) and improves reliability.

4D.4 RELIABILITIES INVESTIGATIONS FOR BULK-FinFETs IMPLEMENTING PARTIALLY-INSULATING LAYER—J. Park, J.-M. Park, S.-O. Sohn, J.- B. Lee, C.-H. Jeon, S.Y. Han, S. Yamada, W. Yang, Y. Roh, and D. Park, Samsung Electronics, Yoingin-Si, Korea

This paper presents a detailed analysis of the reliability characteristics of Partially-Insulated FinFETs(PI-FinFETs) where a new source/drain structure was adapted using a pad-Polysilicon Side Contact (PSC). The new PSC structure shows excellent improvement of device performance and reliability characteristics due to an advantageous location of impact ionization.

Wednesday, April 18, 1:35 p.m., Room C

SESSION 4E INTERCONNECTS II

Co-Chairs: Baozhen Li, IBM and Amit Marathe, AMD

4E.1 TDDB CHARACTERISTICS OF AREA DEPENDENCE AND LINE SPACING SCALING FOR 45 nm LOW-k SiCOH DIELECTRICS—F. Chen, IBM, Essex Jct, VT, P. McLaughlin, IBM, Hopewell Jct, NY, J. Gambino, E. Wu, D. Meatyard, and M. Shinosky, IBM, Essex Jct, VT

There has been very little reported on the area dependence and line spacing scaling of low-k TDDB. A thorough investigation into the 45 nm low-k SiCOH TDDB area dependence and line spacing scaling using multiple temperatures and electric fields was conducted to understand the breakdown failure statistics, model the area dependence, and explore the spacing scaling for technology design.

4E.2 MODELING OF INTERCONNECT DIELECTRIC LIFETIME UNDER STRESS CONDITIONS AND NEW EXTRAPOLATION METHODOLOGIES FOR TIME-DEPENDENT DIELECTRIC BREAKDOWN—G.S. Haase and J.W. McPherson, Texas Instruments, Dallas, TX

Simulation of accelerated time-dependent dielectric breakdown and ramp-to breakdown tests with actual line spacing distributions can explain why these tests often predict too low product lifetime. It is shown that even if one adheres to the conservative E-model, one can still pass stringent reliability requirements if the statistical analysis is done correctly.

4E.3 TIME DEPENDENT DIELECTRIC BREAKDOWN CHARACTERISTICS OF LOW-k DIELECTRIC (SiOC) OVER A WIDE RANGE OF TEST AREAS AND ELECTRIC FIELD—J. Kim, E.T. Ogawa, and J.W. McPherson, Texas Instruments, Dallas, TX

TDDB is reported on integrated SiOC over a wide range of area and electric-field conditions. Package level data was taken at 105°C for over 2 years. The field acceleration (4.5+/0.5 cm/MV) was found approximately independent of area (over 4 decades) and fields (1.5 - 6.0 MV/cm). While the time-to-failure is a strong function of area and field, physics does not vary greatly.

4E.4 MOISTURE RELATED LOW-k DIELECTRIC RELIABILITY BEFORE AND AFTER THERMAL ANNEALING—Y. Li, I. Ciofi, L. Carbonell, G. Groeseneken, K. Maex, and Z. Tokei, IMEC, Leuven, Belgium

A systematic investigation of moisture related SiOC:H low-k dielectric reliability before and after thermal annealing was conducted. The data are correlated with TDS measurements and analyzed in terms of possible OH bonds. The moisture related failure mechanism is not solely determined by physisorbed moisture but by other more tightly bound OH-groups as well.

4E.5 ROLE OF Cu IN TDDB OF LOW-k DIELECTRICS—J.R. Lloyd, S. Ponoth, E. Liniger, and S. Cohen, IBM, Yorktown Heights, NY

Interdigitated comb capacitors with and without Cu present were TDDB tested. Cu containing samples failed in a fraction of the time of those without Cu. To elucidate the role of Cu, samples were annealed at stressing temperature without bias with no effect on the time to failure, indicating that neutral Cu does not play a role. The results are explained through the `Impact Damage' model.

Wednesday, April 18, 4:05 p.m., Room C

SESSION 4F MEMS

Co-Chairs: Danelle Tanner, Sandia National Labs and Jeremy Walraven, Sandia National Labs

4F.1 EFFECT OF SCRATCH STRESS ON THE SURFACE HARDNESS AND INNER STRUCTURES OF A CAPACITIVE FINGERPRINT SENSOR LSI—N. Shimoyama, S. Shigematsu, H. Morimura, T. Shimamura, T. Kumazaki, NTT Electronics Corp., Tokyo, Japan, M. Nakanishi, H. Ishii, and K. Machida, NTT Advanced Technology, Kanagawa, Japan

A scratch test performed on a capacitive fingerprint sensor LDI using a weighted needle revealed that the scratch stress degrades not only the sensor's surface, also the metal interlayer. Increasing the thickness of the surface passivation film and the interlayer are effective ways to prevent scratch stress.

4F.2 TIME AND VOLTAGE DEPENDENCE OF DIELECTRIC CHARGING IN RF MEMS CAPACITIVE SWITCHES—R.W. Herfst, P.G. Steeneken, NXP Semiconductors, Eindhoven, Netherlands, and J. Schmitz, Univ. of Twente, Enschede, Netherlands

A major reliability issue of RF MEMS capacitive switches is charge injection into the dielectric. We experimentally determined that the voltage shift of the CV-curve due to injected charge shows a vt dependence over a large time range and increases exponentially with the applied stress voltage.

4F.3 A CRITICAL ENHANCEMENT IN THE YIELD ANALYSIS OF MICROSYSTEMS—P. Vudathu, U. Gurajada, and R. Laur, Univ. of Bremen, Bremen, Germany

We present a critical enhancement to the yield analysis of microsystems using worst-case methods. The enhancement has been achieved in terms of accuracy of the yield calculation process. A function suite has been developed to implement the enhanced worst-case analysis and compare the results of the pre and post enhancements.

4F.4 FAILURE MECHANISMS IN MEMS BASED SILICON CARBIDE HIGH TEMPERATURE PRESSURE SENSORS—R.S. Okojie, NASA Glenn, Cleveland, OH, P. Nguyen, V. Nguyen, E. Savrun, Sienna Technologies, Woodingville, WA, D. Lukco, J. Buehler, and T. McCue, QSS Group, Inc., Cleveland, OH

Newly discovered failure mechanisms of premature oxidation of the metal/SiC interface during packaging hampered the long-term operation of silicon carbide pressure sensors. We used Auger Electron Spectroscopy, Scanning Electron Microscopy, and Energy Dispersive X-ray to understand these new mechanisms, and developed solution strategies to resolve the failures.

Thursday, April 19, 8:00 a.m., Room A

SESSION 5A PRODUCT & CIRCUIT RELIABILITY II

Co-Chairs: Walter Riordan, Intel and Tom Anderson, Texas Instruments

5A.1 EXTENDED RELIABILITY STUDY OF HIGH DENSITY PZT CAPACITORS: INTRINSIC LIFETIME DETERMINATION AND WAFER LEVEL SCREENING STRATEGY—E. Bouyssou, G. Guégan, S. Bruyère, R. Pezzani, L. Berneux, L. Dantas de Morais, J.-P. Rebrassé, C. Anceau, and C. Nopper, STM, Tours, France

A complete reliability study of integrated PZT capacitors is presented, including both intrinsic and extrinsic purposes. The intrinsic lifetime limits are first assessed from an extended accelerated tests campaign, resulting in a predictive reliability model. A successful in-line screening methodology is then proposed to get rid of extrinsic devices.

5A.2 IMPACT OF NBTI AND PBTI IMPACT ON SRAM V_ccmin DRIFT FABRICATED WITH HIGH-k GATE DIELECTRICS—J.C. Lin, A.S. Oates, and C.H. Yu, TSMC, Hsinchu, Taiwan

SPICE simulations are used to investigate V_ccmin drift in SRAMs fabricated with high-k gate dielectrics. NBTI and PBTI lead to an additive degradation in the bit - cell read voltage. The drift is enhanced at much earlier times compared to SiO₂ gate devices. Results indicate maintaining V_ccmin stability presents a significantly greater challenge for high-k gate dielectrics versus SiO₂, and presents a potentially fundamental limitation for high-k gate dielectrics.

5A.3 ERRATIC BIT ERRORS IN LATCHES—P. Relangi and S. Mitra, Stanford University, Stanford, CA

The effects of erratic bit errors in latches are studied using SPICE simulation. A latch structure using a C-element was found to correct most erratic bit errors. This structure also enables chip-level power reduction by enabling chip operation at low voltage through correction of latch bit errors. The structure can also correct radiation induced soft errors.

5A.4 UNDERSTANDING SRAM HIGH-TEMPERATURE-OPERATING-LIFE NBTI: STATISTICS AND PERMANENT vs RECOVERABLE DAMAGE—A. Haggag, G. Anderson, S. Parihar, D. Burnett, G. Abeln, J. Higman, and M. Moosa, Freescale, Austin, TX

We show, using deconvolution, SRAM V_min shift statistics yield a spread that follows Poisson area scaling and a time- and voltage- dependence of t^1/6 and V³, respectively. This is demonstrated to be consistent with permanent NBTI shift (Si-H bond breaking) relevant for end-of-life extrapolation. In contrast recoverable NBTI shift (hole trapping/detrapping) is shown to be only a function of stress duty and can be very small for realistic product duties.

Thursday, April 19, 8:00 a.m., Room A

SESSION 5B COMPOUND SEMICONDUCTORS

Co-Chairs: Brian J. Skromme, Arizona State University and Gaudenzio Meneghesso, Univ. of Padova

5B.1 REVERSIBLE DEGRADATION OF GaN LEDS RELATED TO PASSIVATION—M. Meneghini, L. Trevisanello, R. Penzo, M. Benedetti, Univ. of Padova, Padova, Italy, U. Zehnder, U. Strauss, OSRAM OptoSemiconductors, Regensburg, Germany, G. Meneghesso, and E. Zanoni, Univ. of Padova, Padova, Italy

This paper analyzes the thermal degradation of GaN LEDs. The optical output degradation is attributed to the interaction between H from the PECVD SiN passivation layer and the LED surfaces. This degradation is found to be reversible after passivation removal and subsequent annealing. Use of sputtered SiN in place of PECVD SiN is shown to eliminate these high temperature instabilities.

5B.2 ULTRA-FAST CHARACTERIZATION OF TRANSIENT GATE OXIDE TRAPPING IN SiC MOSFETS—M. Gurfinkel, Univ. of Maryland, College Park, MD, J.S. Suehle, NIST, Gaithersburg, MD, J.B. Bernstein, Univ. of Maryland, College Park, MD, Y. Shapira, Tel Aviv Univ., Tel Aviv, Israel, A.J. Lelis, D. Habersat, Army Research Labs, Adelphi, MD, and N. Goldsman, Univ. of Maryland, College Park, MD

V_TH instability under normal operation conditions limits the introduction of SiC MOSFETs in commercial power devices. Fast I-V measurements reveal the full extent of the V_TH instability, significantly underestimated by dc measurements. A physical model involving fast transient charge trapping and de-trapping at and near the SiC/SiO₂ interface is proposed.

5B.3 INVESTIGATING THE STABILITY OF THIN FILM TRANSISTORS WITH ZINC OXIDE AS THE CHANNEL LAYER—R.B.M. Cross and M.M. De Souza, De Montfort University, Leicester, UK

This paper describes the effect of bias stress and elevated temperature measurement on the stability of zinc oxide thin film transistors. High and low bias stress cause reversible shifts in the transfer characteristics and other device performance parameters. These shifts are thought to involve a combination of charge trapping and defect creation at or near the interfacial region.

5B.4 ACCELERATED RF LIFE TESTING OF GaN HFETs—A.M. Conway, M. Chen, P. Hashimoto, P.J. Willadsen, and M. Micovic, HRL Labs, LLC, Malibu, CA

This paper reports the results of a comprehensive three temperature accelerated RF life test on GaN HFETs at 10 GHz. Transistors were stressed at 2 dB gain compression with a bias of Ids=100 mA/mm and Vds=25 V at 285, 315, and 345°C. An activation energy of 1.8 eV was extracted, giving a MTTF of 3.5x10⁹ hrs at Tch=125°C.

5B.5 RELIABILITY ASSESSMENT OF 1.55-µm VERTICAL CAVITY SURFACE EMITTING LASERS FOR OPTICAL COMMUNICATION SYSTEMS—K.H. Rhew, S.C. Jeon, Yonsei Univ., Seoul, Korea, O-K. Kwon, ETRI, Daejeon, Korea, D.H. Lee, B.S. Yoo, Raycan Co., Daejeon, Korea, and I. Yun, Yonsei, Univ., Seoul, Korea

In this paper, the long-term reliability of all monolithic 1.55 µm vertical cavity surface-emitting lasers (VCSELs) was investigated. The median VCSEL lifetime as a function of temperature was extrapolated and the activation energy of the device degradation mechanism was calculated. Based on the results, the long-term reliability of these VCSELs for high-speed optical communication applications is projected.

Thursday, April 19, 8:00 a.m., Room B

SESSION 5C HIGH VOLTAGE DEVICES

Co-Chairs: Peter Moens, AMIS and Sameer Pendharkar, Texas Instruments

5C.1 (invited) RELIABILITY OF HIGH POWER MODULES FOR TRACTION APPLICATIONS—M. Ciappa, ETH Zurich, Zurich, Switzerland

The enhancement of the system efficiency in conjunction with a reduction of weight and volume in railway and automotive applications requires high temperature power devices with reduced losses and with an optimized thermal management. This paper addresses the main technology issues to be faced in order to reach the necessary reliability level.

5C.2 (ESREF best paper invited) EFFECT OF A BUFFER LAYER IN THE EPI-SUBSTRATE REGION TO BOOST THE AVALANCHE CAPABILITY OF A 100V SCHOTTKY DIODE—A. Irace, G. Breglio and P. Spirito, University of Naples, A. Bricconi, D. Raffo and L. Merlin, International Rectifier Corporation Italiana, MICROELECTRONICS RELIABILITY 46 (2006) 1784-1789

The aim of this paper is to give an insight and a possible explanation of the limitations in the Reverse Bias Safe Operating Area of 100V Si Power Schottky Diodes. Starting from experiments and going through device simulations and theory a physical explanation of device failure both in short (i.e. isothermal) and long pulse are explained. With the help of the theoretical analysis an improvement of the design is proposed to increase avalanche capability of these devices and preliminary experimental data are reporting a very promising increase of both the maximum sustainable current in avalanche condition and the maximum sustainable avalanche energy in UIS conditions.

5C.3 INVESTIGATION AND IMPROVEMENT OF FAST TEMPERATURE-CYCLE RELIABILITY FOR DMOS-RELATED CONDUCTOR PATH DESIGN—T. Smorodin, Infineon Technologies, Munchen, Germany, J. Wilde, Univ. of Freiburg, Freiburg, Germany, P. Alpern, and M. Stecher, Infineon Technologies, Munchen, Germany

During operation DMOS transistors are objected to severe temperature pulses, which cause a thermo-mechanical stress and ILD cracking. Due to its relevance for the DMOS design, the influence of the conductor line width is studied. From the observed failure evolution an effective method to improve high-cycle reliability is derived.

5C.4 A COMPREHENSIVE MODEL FOR HOT CARRIER DEGRADATION IN LDMOS TRANSISTORS—P. Moens, AMIS, Oudenaarde, Belgium, J. Mertens, IMEC, Diepenbeek, Belgium, F. Bauwens, P. Joris, AMIS, Oudenaarde, Belgium, W. De Ceuninck, IMEC, Diepenbeek, Belgium, and M. Tack, AMIS, Oudenaarde, Belgium

This paper presents a comprehensive yet physical model for hot carrier degradation in LDMOS transistors. The model allows to calculate AC degradation performance out of the DC hot carrier data. A physical explanation of the observed effects is provided, and important differences between LDMOS and standard CMOS are highlighted.

5C.5 PHOTO MISALIGNMENT IMPACT ON THE HOT CARRIER DEVICE RELIABILITY OF LATERAL DMOS DEVICES—D. Brisbin, P. Lindorfer, and P. Chaparala, NSC, Santa Clara CA

Power management devices often require operation in the 20 V to 30 V range. Because of the high voltages applied to the NLDMOS device hot carrier (HC) degradation is a real reliability concern. This paper focuses on understanding unusual N-LDMOS HC performance in which devices implemented as single gate devices had significantly better HC performance than dual gate devices.

5C.6 (withdrawn)

Thursday, April 19, 10:30 a.m., Room A

SESSION 5D LATE PAPERS

Co-Chairs: Anand Krishnan, Texas Instruments and Baozhen Li, IBM

5D.1 DENSITY OF STATES AND STRUCTURE OF NBTI-INDUCED DEFECTS IN PLASMA-NITRIDED pMOSFETs—J.P. Campbell, P.M. Lenahan, Penn State Univ., University Park, PA, A.T. Krishnan, and S. Krishnan, Texas Instruments, Dallas, TX

We utilize DC-IV and magnetic resonance measurements to investigate NBTI-induced defects in SiO₂ and plasma nitrided pMOSFETs. Our observations indicate that the defects in plasma nitrided devices are located in the near-interface dielectric region and exhibit a far narrower density of states than the interface defects observed in SiO2 devices.

5D.2 RELIABILITY CHALLENGES IN COPPER METALLIZATIONS ARISING WITH THE PVD RESPUTTER LINER ENGINEERING FOR 65nm AND BEYOND—A.H. Fischer, Infineon, Munich, Germany, O. Aubel, AMD, Dresden, Germany, J. Gill, T.C. Lee, B. Li, C. Christiansen, F. Chen, IBM Microelectronics, Essex Jct., VT, M. Angya, IBM Microelectronics, East Fishkill, NY, T. Bolom, AMD, East Fishkill, NY, E. Kaltalioglu, Infineon, East Fishkill, NY

In this paper the influence of liner deposition parameters on the reliability of 65nm copper metallizations have been investigated for two different deposition sequences. The use of resputter liners in the 65nm generation turned out to change the via-voiding failure mode qualitatively from voiding at the very via-bottom to void nucleation at mid-half of the via. In addition, the resputter intensity and liner thickness have a quantitative impact on the electromigration (EM) failure times and stressmigration (SM) failure rates. For a given liner thickness an increasing resputter intensity turned out to improve the overall reliability as a result of a more pronounced anchoring of the via within the metal line underneath. In terms of the liner thickness, thinner barriers yield in general reduced failure times. However, this loss can be compensated at least partially by adjusting the resputter intensity with repsect to the specific liner

Thursday, April 19, 2:00 p.m., Room A

SESSION 6A FAILURE ANALYSIS

Co-Chairs: Steven Kasapi, Credence and John West, Texas Instruments

6A.1 HIGH-RESOLUTION CHARACTERIZATION OF ULTRA-SHALLOW JUNCTIONS BY SCANNING SPREADING RESISTANCE MICROSCOPY—L. Zhang, K. Adachi, H. Tanimoto, and A. Nishiyama, Toshiba Corp., Kawasaki, Japan

This paper investigates two-dimensional characterization of ultra-shallow junction CMOSFETs using high-resolution SSRM in vacuum. The effective probe radius of the SSRM is confirmed to be 0.5 nm by comparing with device simulations. The difference in halo impurity distributions was directly observed to be in agreement with the difference in roll-off characteristics.

6A.2 PICOSECOND TIMING ANALYSIS IN INTEGRATED CIRCUITS WITH PULSED LASER STIMULATION—A. Douin, V. Pouget, D. Lewis, P. Fouillat, and P. Perdu, IXL, Univ. Bordeaux, Talence, France

This paper presents a new approach for timing analysis of high-speed integrated circuits using picosecond pulsed laser stimulation. The authors present case studies on digital test structures showing very good temporal resolution. This technique should find general applications in finding timing-related faults.

6A.3 INVESTIGATION OF LASER VOLTAGE PROBING SIGNALS IN CMOS TRANSISTORS—U. Kindereit, Berlin Univ. of Technology, Berlin, Germany, G. Woods, Sooner Silicon Consulting, Sunnyvale, CA, J. Tian, Credence Systems Corp., Sunnyvale, CA, U. Kerst, and C. Boit, Berlin Univ. of Technology, Berlin, Germany

This paper presents a study of the physics of Laser Voltage Probing (LVP) of large FETs. Quantitative measurements were performed using a CW laser at 1.3 µm with frequency-domain signal extraction. The inherent low noise allows two-dimensional mapping of modulation depth. A qualitative model is also presented which agrees with the measurements.

6A.4 (late) PHASE VARIATION MAPPING, A DYNAMIC LASER STIMULATION TECHNIQUE WITH PICOSECOND TIMING RESOLUTION—K. Sanchez, CNES, Toulouse, France, P. Perdu, and F. Beaudoin, Credence, Sunnyvale, CA

The proposed methodology extends the application of existing Dynamic Laser Stimulation techniques to the study and characterization on the impact of design/process issues on the overall dynamic performance of state of the art ICs. Phase Variation Mapping is also directly applicable to non latched and asynchronous devices for the localization of defects such as soft defects or physical anomalies and to all alternative and periodic signals coming from a device, like the current or the case of analog devices.

Thursday, April 19, 2:00 p.m., Room B

SESSION 6B MEMORY II

Co-Chairs: Chandra Mouli, Micron and Renichi Yamada, Hitachi

6B.1 (invited) DATA RETENTION CHARACTERIZATION OF PHASE CHANGE MEMORY ARRAYS—R. Gleixner, Intel and A. Pirovano, STM

To support reliable large array products, Phase-Change Memory (PCM) technologies must support bit level failure rates of less than 1 in 10⁶ cells. This requires the identification and suppression of defect tail mechanisms that only become apparent once device testing is performed at the multi-megabit level. In this paper, we characterize the data retention characteristics of cells that fail earlier than the intrinsic distribution. We then address means of reducing the number of such cells to acceptable levels.

6B.2 A PHYSICS-BASED CRYSTALLIZATION MODEL FOR RETENTION IN PHASE-CHANGE MEMORIES—U. Russo, D. Ielmini, and A.L. Lacaita, DEI - Politecnico di Milano, Milano, Italy

This work presents a new crystallization model for phase-change memory (PCM) devices, enabling prediction of PCM retention time from accelerated high-temperature data. Data retention capability between different chalcogenide materials is compared.

6B.3 A HIGHLY RELIABLE FRAM (FERROELECTRIC RANDOM ACCESS MEMORY)—J.-H. Kim, D.J. Jung, Y.M. Kang, H.H. Kim, W.W. Jung, J.Y. Kang, E.S. Lee, H. Kim, J.Y. Jung, S.K. Kang, Y.K. Hong, S.Y. Kim, H.K. Koh, D.Y. Choi, J.H. Park, S.Y. Lee, H.S. Jeong, and K. Kim, Samsung Electronics, Yongin-City, S. Korea

Random-single-bits in 64 Mb FRAM during package-level tests were studied and linked to oxygen-vacancies and imperfections in the contact to cell capacitor. Reliability of FRAM cells was improved by removing these defects.

6B.4 CYCLING-INDUCED PROGRAM DISTURB OF SPLIT GATE FLASH MEMORY—Y.-H. Wang, Y.-S. Tsair, A.-C. Kang, W.-T. Chu, E. Chen, J.R. Shih, H.W. Chin, and K. Wu, TSMC, Hsin-Chu, Taiwan

Analytical program disturb modeling is presented and used to estimate post-cycling time to disturb by formulating punchthrough (PT) current evolution with cycling. The optimized erase voltage is chosen to achieve maximum endurance based on tradeoff of erase time pushout (ETP) and post-cycling program disturb. Early PT failure mechanism of array cycling was studied and eliminated through optimizations to STI corners.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION AP ASSEMBLY & PACKAGING

Co-Chairs: Sidharth, AMD and Rajen Dias, Intel

AP01 AN EFFICIENT CERTIFICATION APPROACH FOR NEW Sn-Ag-Cu SOLDER ALLOY—J. Masicat, Intel Technology Philippines Inc., Cavite, Philippines, C. Kumar, Intel, Chandler, AZ, and M. Nuda, Intel Technology Philippines Inc., Cavite, Philippines

This poster will outline efficient qualification strategies employed on cellular handheld products in qualifying the newer Sn-Ag-Cu solder alloy, SAC105 (98.5% tin, 1.0% silver and 0.5% copper). Various component level and board level evaluations, including shock, were conducted.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION CD COMPOUND SEMICONDUCTORS

Co-Chairs: Brian J. Skromme, Arizona State University and Gaudenzio Meneghesso, Univ. of Padova

CD01 THE MIXED-MODE DAMAGE SPECTRUM OF SiGe HBTS—P. Cheng, C. Zhu, J.D. Cressler, Georgia Tech, Alanta, GA, and A. Joseph, IBM, Essex Junction, VT

We present a technique for assessing the complete mixed-mode damage spectrum of SiGe HBTs, and apply it to three SiGe technology generations. We distinguish four distinct regions of cross-generational SiGe HBT stress response, identify a new low-current damage mechanism in third generation devices, and observe a novel stress-induced annealing phenomenon.

CD02 TEMPERATURE AND VOLTAGE DEPENDENT RF DEGRADATION STUDY IN AlGaN/GaN HEMTs—R. Coffie, Y. Chen, I. Smorchkova, B. Heying, V. Gambin, W. Sutton, Y.-C. Chou, W.-B. Luo, M. Wojtowicz, and A. Oki, Northrop Grumman Corp., Redondo Beach, CA

In this work, the reaction-diffusion limited trap generation model typically used to explain MOSFET degradation is applied to GaN HEMT degradation. An analytical expression to describe the time dependence of RF output power is derived based on this model. In addition, the voltage and temperature dependences of the fitting parameters are determined.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION DI DIELECTRICS

Co-Chairs: Ernest Wu, IBM and Frederic Monsieur, STM

DI01 CORRELATING WAFER-LEVEL TDDB LIFETIME PROJECTIONS TO HTOL GATE OXIDE FAILURES—A. Ditali, H.A. Le, D.L. Butler, M. Ingram, and M. Ma, Micron Technology, Boise, ID

The power-law model provides a relatively good correlation between WL TDDB (highly accelerated test) conducted on test structures and HTOL (moderately accelerated test) conducted on product. This is true when WL stress is configured identically to HTOL stress, and the difference in oxide area between the two devices under stress is taken into account for lifetime projections.

DI02 THE ROLE OF POWER DISSIPATION ON THE PROGRESSIVE BREAKDOWN DYNAMICS OF ULTRA-THIN GATE OXIDES—E. Miranda, Univ. Autonoma de Barcelona, Bellaterra, Spain

The connection between the leakage current increase in ultra-thin gate oxides associated with progressive breakdown and the power dissipation dynamics at the breakdown spot is investigated. Using a simple equivalent circuit model and the transmission properties of mesoscopic conducting systems, it is shown that the current stabilization during a constant voltage stress is linked to the gradual transfer of dissipated power from the constriction's bottleneck to the semiconductor electrodes.

DI03 A NEW `MULTI-STEP' POWER-LAW TDDB LIFETIME MODEL AND BORON PENETRATION EFFECT ON TDDB OF ULTRA THIN OXIDE—P.J. Liao, C.L. Chen, C.J.Wang, and K. Wu, TSMC, Hsinchu, Taiwan

A new "multi-step" power-law TDDB lifetime model is characterized and proposed for ultra thin gate oxide. The effect of leakage current and that of boron penetration on TDDB lifetime are systematically investigated. The mechanism of the voltage acceleration factor degradation in p-FETs is well understood as boron penetration enhances the electron and holes tunneling currents.

DI04 A CRITICAL GATE VOLTAGE TRIGGERING IRREVERSIBLE GATE DIELECTRIC DEGRADATION—V.L. Lo, K.L. Pey, Nanyang Technological Univ., Singapore, C.H. Tung, Institute of Microelectronics, Singapore, and D.S. Ang, Nanyang Technological Univ., Singapore

A critical gate voltage (Vcrit), which prevents the post-breakdown gate leakage current from evolving into a stable, irreversible state, is discovered. Our study reveals that Vcrit decreases with decreasing oxide thickness, and thus, its impact on the reliability assessment of sub-65-nm devices cannot be ignored.

DI05 NEW INSIGHTS ON PERCOLATION THEORY AND THE ORIGIN OF OXIDE BREAKDOWN THICKNESS AND PROCESS DEPOSITION DEPENDENCE—G. Ribes, STM, Crolles, France, M.Rafik, STM & IMEP/ENSERG, Crolles, France, D. Barge, NXP, Crolles, France, S. Kalpat, Freescale, Crolles, France, M. Denais, STM, Crolles, France, V. Huard, NXP, Crolles, France, and D. Roy, STM, Crolles, France

We proposed in previous paper a quantitative oxide breakdown model called Multi-Vibrational Hydrogen Release applicable to advanced gate dielectrics. In this paper we are using this model in order to better understand the percolation theory and the impact of gate oxide process deposition.

DI06 METHODOLOGY FOR WORD LINE-CONTACT DIELECTRIC CHARACTERIZATION IN FLASH NOR MEMORIES—G. Ghidini, R. Bottini, M. Brambilla, D. Brazzelli, N. Galbiati, A. Ghetti, A. Mauri, and C. Scozzari, STM, Agrate, Italy

Aim of this work is to study the reliability of the dielectric between cell control gate and drain contact. Conduction characteristics and reliability under high field stress are investigated. The large spread in this dielectric thickness because of mask misalignment makes the usual reliability procedures very difficult to be applied. Results relative to fast and long reliability measurements are discussed, proposing a method for the evaluation of the spread between control gate and drain contact. Moreover, this methodology allows a screening of the structures with a too critical mask misalignment, or with a poor dielectric quality which could cause memory failures during cycling.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION EE MICROELECTRONICS IN EXTREME ENVIRONMENTS

Chairs: Donald C. Mayer, The Aerospace Corp.

EE01 REVERSE-BODY BIASING FOR RADIATION-HARD BY DESIGN LOGIC GATES—L.T. Clark, K.C. Mohr, and K.E. Holbert, Arizona State Univ. Tempe, AZ

Transistors hardened by reverse-body bias (RBB) are compared with annular NMOS transistors and unhardened transistors with respect to CMOS gate area, gate delay, active and standby power, and total-dose hardness. Experimental data for a 130 nm bulk CMOS process shows that RBB permits smaller devices and reduced chip-level leakage at 1 Mrad(Si) than a design hardened using annular gates.

EE02 POWER PERFORMANCE CHARACTERISTICS OF SiGe POWER HBTs AT EXTREME TEMPERATURES—G. Qin, G. Wang, and Z. Ma, Univ. of Wisconsin-Madison, Madison, WI

The performance characteristics of SiGe power heterojunction bipolar transistors (HBTs) at cryogenic temperature (77K) and at high temperature (160°C) are presented. SiGe HBTs exhibited excellent large-signal characteristics and reliability at 77K. In addition, large-area SiGe HBTs also exhibit excellent large-signal power performance characteristics under high-temperature operation. High-temperature simulations suggest that the increase of base and emitter resistance accounts for the degradation of power performance of these devices.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION EL ESD & LATCHUP

Co-Chairs: Elyse Rosenbaum, Univ. of Illinois and Gianluca Boselli, Texas Instruments

EL01 ESD TESTING OF COPPER AND ALUMINUM VERTICAL PARALLEL PLATE (VPP) CAPACITOR STRUCTURE FOR RF APPLICATIONS—S.H. Voldman, E.G. Gebreselasie, and Z.-X. He, IBM, Essex Junction, VT

Vertical Parallel Plates (VPP) ESD robustness is evaluated for the first time. HBM experimental results demonstrate that Cu-based VPP structures are superior to Al-based VPP structures. ESD testing of independent and combined structures will be shown. Additionally, ESD results show that Cu-based VPP can achieve over 500 V ESD HBM levels without RF ESD protection networks.

EL02 A SIMPLE AND USEFUL LAYOUT SCHEME TO ACHIEVE THE COMPLETELY UNIFORM CURRENT DISTRIBUTION FOR MULTI-FINGERS SILICIDED GROUNDED-GATE NMOS—J.-H. Lee, Y.-H. Wu, C.-H. Tang, S.-H. Chen, and A.S. Oates, TSMC, Hsinchu, Taiwan

Using long contact to contact space can build a ballast resistor for silicided GGNMOS and had been proven that can improve IO device ESD performance (IT2, HBM AND MM), especially MM, and eliminate the short channel induced the core device ESD performance degradation effect.

EL03 BOARD LEVEL ESD OF DRIVER ICs ON LCD PANELS—C.T. Hsu, J.C. Tseng, Y.L. Chen, F.Y. Tsai, S.H. Yu, P.A. Chen, Winbond Electronics, Hsinchu, Taiwan , and M.D. Ker, National Chiao-Tung University, Hsinchu, Taiwan

A method utilizing CDM discharging to emulate real-world CBM discharging was proposed. This is the first time to disclose the investigation of board-level ESD about TCP/COF packaged driver ICs. Besides, this paper addresses the guidelines about chip-level ESD cell design and layout optimization against CBM ESD damage.

EL04 LEAKAGE SUPPRESSION OF LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR—S.-H. Dai, National Tsing-Hua Univ., Hsin-Chu, Taiwan, H.-N. Wang*, M.-T. Chiang, Vishay General Semiconductor Taiwan Ltd., Hsin-Chu, Taiwan, C.-J. Lin, and Y.-C. King, National Tsing-Hua Univ., Hsin-Chu, Taiwan

Diode-based transient voltage suppressors are widely used in protection from electrical surge. Low voltage TVS devices encounter a problem of large leakage under normal bias condition. In this work, the locos diode is proposed. These devices effectively reduce the edge effect on the highly doped diode by some simple modifications on the process.

EL05 DESIGN OF HIGH-VOLTAGE-TOLERANT POWER-RAIL ESD CLAMP CIRCUIT IN LOW-VOLTAGE CMOS PROCESSES—M.-D. Ker, C.-T. Wang, T.-H. Tang, and K.-C. Su, National Chiao-Tung Univ., Hsinchu, Taiwan

new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1×VDD devices for 3×VDD-tolerant mixed-voltage I/O interfaces is proposed in this work. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-um CMOS process with only 1.2-V devices.

EL06 NOVEL ROBUST HIGH VOLTAGE ESD CLAMPS FOR LDMOS PROTECTION—A.J. Walker, S.T. Ward, and H. Puchner, Cypress Semiconductor, San Jose, CA

We present a series of novel high voltage ESD clamps to protect LDMOS FETs from ESD damage. The clamps have been implemented on smart power products and tested employing a TLP test system. The clamps have been investigated for HBM and CDM robustness. Multiple zaps as well as walkout phenomena have been analyzed.

EL07 FAILURE OF ON-CHIP POWER-RAIL ESD CLAMP CIRCUITS DURING SYSTEM-LEVEL ESD TEST—C.-C. Yen and M.-D. Ker, National Chiao-Tung Univ., Hsinchu, Taiwan

Four different on-chip power-rail electrostatic discharge (ESD) protection circuits, (1) with typical RC-triggered; (2) with NMOS and PMOS feedback; (3) with PMOS feedback; and (4) with cascaded PMOS feedback, have been designed and fabricated in a 0.18-µm CMOS technology to investigate their susceptibility to system-level ESD test. The main purpose for adopting the feedback loop into the power-rail ESD clamp circuits is to avoid the false triggering during a fast power-up operation. However, during the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuit provides the lock function to keep the main ESD device in a latch-on state. The latch-on ESD device, which is often designed with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. From the experimental results, two kinds of on-chip power-rail ESD clamp circuits with feedback structures have lower system-level ESD immunity than others. The failure location after system-level ESD test has been inspected, which is located on the VDD power line even drawn with a metal width of 30 µm.

EL08 AN INVESTIGATION OF EXTERNAL LATCHUP—F. Farbiz and E. Rosenbaum, Univ. of Illinois, Urbana, IL

External latchup susceptibility of CMOS technology is experimentally investigated by focusing on the N-well minority carrier collection. An ESD diode is a substrate current injector and a nearby N-well is the minority carrier collector. Latchup susceptibility is a function of injector to detector spacing, detector orientation, and temperature. Physical explanations are provided for the experimental results and a modeling framework suggested.

EL09 MIXED DEVICE-CIRCUIT SOLUTION FOR ESD PROTECTION OF HIGH-VOLTAGE FAST PINS—V.A. Vashchenko, NSC, Santa Clara, CA, N. Olson, Univ. of Illinois, Urbana, IL, D. Farrenkopf, V. Kuznetsov, P. Hopper, NSC, Santa Clara, CA, and E. Rosenbaum, Univ. of Illinois, Urbana, IL.

This study presents a new, mixed device-circuit solution for ESD protection of high-voltage, high-speed pins in power analog circuits, specifically in switching voltage regulators. Experimental validation of the new approach is provided; the demonstration vehicle is a LDMOS-SCR ESD device whose triggering characteristics are controlled by an active circuit.

EL10 25V ESD NPN TRANSISTOR OPTIMIZED BY DISTRIBUTED EMITTER BALLASTING USING EMITTER CONTACT AREA SEGMENTATION—M. Denison, S. Murtaza, R. Steinhoff, S. Merchant, S. Pendharkar, TI, Dallas, TX, and S. Bychikhin, D. Pogany, Vienna Univ. of Technology, Vienna, Austria

A 25V ESD NPN transistor is made high current capable by means of distributed emitter ballasting. The proposed segmentation of the emitter contact area along the width offers an efficient way to extend the homogeneous current regime without causing any significant increase of the holding voltage. At high current, a second snap-back is observed in the TLP current-voltage characteristics. Transient interferometric mapping analyses show that this voltage drop is due to current filamentation arising at a time decreasing with increasing current amplitude.

EL11 A NOVEL METHOD FOR GUARD RING EFFICIENCY ASSESSMENT AND ITS APPLICATIONS FOR ESD PROTECTION DESIGN AND OPTIMIZATION—D. Trémouilles, IMEC, Leuven, Belgium, M.I. Natarajan, Silterra Malaysia, Kulim, Malaysia, M. Scholz, IMEC, Leuven, Belgium, N. Azilah, Silterra Malaysia, Kulim, Malaysia, M. Bafleur, LAAS-CNRS, Toulouse, France, M. Sawada, T. Hasebe, Hanwa Electronics, and G. Groeseneken, IMEC, Leuven, Belgium & Katholieke Univ., Leuven, Belgium

A novel characterization methodology to quantify the parasitic interaction between the ESD protection devices and the associated latch-up guard rings is presented for the first time. With these results, optimal sizing of the ESD device guard rings as a function of the ESD power clamp can be achieved.

EL12 AN INSIGHT INTO THE HIGH CURRENT ESD BEHAVIOR OF DRAIN EXTENDED NMOS (DENMOS) DEVICES IN NANOMETER SCALE CMOS TECHNOLOGIES—A. Chatterjee, UC Santa Barbara, Santa Barbara, CA, S. Pendharkar, Y.-Y. Lin, C. Duvvury, TI, Dallas, TX, and K. Banerjee, UC Santa Barbara, Santa Barbara, CA

In this work we model high current behavior for a 90nm DENMOS transistor that is applicable for 1.8V/3.3V/5V designs. This work presents an insight into physical understanding and hence turn-on behavior of a parasitic BJT in the DENMOS and its impact on the irreversible snapback behavior.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION FA FAILURE ANALYSIS

Co-Chairs: Steven Kasapi, Credence and John West, Texas Instruments

FA01 LIMITATION OF WSix/WN DIFFUSION BARRIER FOR TUNGSTEN DUAL POLYMETAL GATE MEMORY DEVICES—K.-Y. Lim, M.G. Sung, Y.S. Kim, H.-J. Cho, S.-R. Lee, S.-A. Jang, S.-G. Choi, Y.-J. Lee, T.-K. Oh, Y.-S. Chun, Y.-H. Kim, K.-S. Choi, K.O. Kim, Y.-K. Jung, S.-Y. Koo, W.-K. Ma, J.-H. Han, G.-H. Kim, S.-J. Kim, S.-R. Won, S.-A. Shin, J.-K. Lee, T.-O. Youn, W. Kim, Y.-T. Hwang, H.-S. Yang, S.-H. Pyi, and J.-W. Kim, Hynix Semiconductor, Ichon-si, Korea

This paper compares WSix/WN and Ti/WN diffusion barriers for tungsten dual polymetal gate application. The WSix/WN barrier shows not only degradation of p+poly-Si PMOS gate oxide but also slow device performance, which is attributed to B-N formation due to reaction of boron and W-Si-N barrier.

FA02 FAILURE ANALYSIS OF AN ANOMALOUS SUBTHRETHOLD CURRENT IN NANO-SCALE NAND FLASH MEMORY—D.-H. Lee, S.-W. Shin, C.-K. Ryu, J.-H. Choi, C.-M. Lim, N.-Y. Kwak, H.-S. Shon, J. Koo, K. Hong, B.-S. Lee, S.-K. Park, and S.-W. Park, Hynix Semiconductor, Icheon-si, S. Korea

This paper presents an application of scanning capacitance microscopy (SCM) to failure analysis of nano-scale NAND flash memory devices. The SCM results are compared with chemical staining data. In order to suppress anomalous hump characteristics typical of dual-threshold effects, a numerical simulation study of trench sidewall implantation processes is also presented.

FA03 A NEW METHOD FOR FAILURE ANALYSIS WITH PROBING SYSTEM BASED ON AN SCANNING ELECTRON MICROSCOPE—T. Nokuo, Y. Eto, JEOL Ltd., Tokyo, Japan, and Z. Marek, JEOL USA, Peabody, MA

Failure analysis of semiconductor devices requires accurate fault site localization. However, the shrinking of circuit elements and the structure of multi-layer devices make it more difficult. This paper describes a new scanning-electron microscope (SEM) technique which addresses this growing challenge.

FA04 FAILURE ANALYSIS AND OPTIMIZATION OF METAL FUSES FOR POST PACKAGE TRIMMING—Y.-H. Cheng and C.E. Kendrick, ON Semiconductor, East Greenwich, RI

Post package trimming is important for achieving precise control of circuit parameters that may shift due to package stresses. However, the size of on-chip driver circuitry must be minimized while still maintaining reliably trimmed fuses. This case study presents a statistical analysis and physical characterization of trimmed fuses to optimize fuse geometry and trimming conditions.

FA05 (withdrawn)

FA06 MAXIMUM PERMISSIBLE EB ACCELERATION VOLTAGE FOR SEM-BASED INSPECTION BEFORE ELECTRICAL CHARACTERIZATION OF ADVANCED MOS—T. Mizuno, M. Takahashi, Y. Azuma, H. Yanagita, K. Asayama, and K. Nakamae, Renesas Technology, Tokyo, Japan

This paper studies the effect electron beam acceleration voltages of SEM on electrical circuit behaviour. Quantitative evaluation is performed using the Nano-Prober to measure the same generation devices with tuned ILD thicknesses, and the result is compared with Monte Carlo Simulations.

FA07 DETERMINATION OF INTRINSIC SPECTRA FROM FRONTSIDE & BACKSIDE PHOTON EMISSION MICROSCOPY OF SILICON MOSFETs AT NEAR-IR WAVELENGTHS.—S.L. Tan, D.S.H. Chan, and J.C.H. Phang, National Univ. of Singapore, Singapore

For accurate photon emission spectroscopy, the optical effects of dielectrics and silicon layers on the intrinsic emission spectra must be taken into consideration. A model to derive the intrinsic spectra from both frontside and backside measured spectra is developed. The model is applied to derive the intrinsic spectra of a saturated nMOSFET and oxide leakage emission.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION HK HIGH-K

Co-Chairs: Michel Houssa, IMEC and Eduard Cartier, IBM

HK01 INVESTIGATION OF HOT CARRIER EFFECTS IN n-MOSFETs THICK OXIDE WITH HfSiON AND SiON GATE DIELECTRIC—K.J. Nam, S.H. Lee, D.C. Kim, S.J. Hyun, J.H. Kim, I.S. Jeon, S.B. Kang, S.Y. Choi, and U.I. Chung, Samsung Electronics, Yongin-City. Korea

This paper reports the hot carrier reliability characteristics of poly gated n-MOSFETs with HfSiON and SiON gate dielectrics in both thin and thick oxide of dual gate oxide scheme. It is found that HC immunity at Isub,max stress should be checked in thick oxide transistor below 50 nm design rule era.

HK02 BTI AND ELECTRON TRAPPING IN Hf-BASED DIELECTRICS WITH DUAL METAL GATES—Y.T. Hou, J.C. Liao, P.F. Hsu, C.L. Hung, K.C. Lin, K.T. Huang, T.L. Lee, Y.K. Fang, and M.S. Liang, TSMC, Hsinchu, Taiwan

In metal/high-k stacks, nitridation and channel strain are found to degrade NBTI. A new pulse technique with minimized de-trapping is proposed to simultaneously characterize fast and slow trapping. Solid evidence is given to the tunneling mechanism of fast trapping and it is also revealed that de-trapping during stress plays important role in slow trap generation.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION HV HIGH VOLTAGE DEVICES

Co-Chairs: Peter Moens, AMIS and Sameer Pendharkar, Texas Instruments

HV01 HOT CARRIER DEGRADATION OF p-LDMOS TRANSISTORS FOR RF APPLICATIONS—J. Kraft, B. Loffler, M. Knaipp, and E. Wachmann, austriamicrosystems AG, Unterpremstaetten, Austria

A p-LDMOS transistor is developed focusing on RF applications with operating voltages of 12V. It is implemented in a 0.35 um SiGe BiCMOS technology by only one additional implant mask. Three different degradation root causes were identified by long term hot carrier stress measurement and correlated with TCAD simulation results.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION IT INTERCONNECTS

Co-Chairs: Baozhen Li, IBM and Amit Marathe, AMD

IT01 LEAKAGE CURRENT CHARACTERISTIC OF PRE-DAMAGED INTERLAYER DIELECTRIC DURING VOLTAGE RAMP METHOD—S.-S. Hwang, S.-Y. Jung, and Y.-C. Joo, Seoul National Univ., Seoul, Korea

The degradation of dielectric under constant electric field with time was studied by various VRDB tests on predamaged samples in both intrinsic and extrinsic system. Poole-Frenkel conduction mechanism which appears after pre-damage reveals that Cu ion plays a role of Poole-Frenkel trap site.

IT02 NEW UNDERSTANDING OF METAL-INSULATOR-METAL (MIM) CAPACITOR DEGRADATION BEHAVIOR—C.-C. Hung, A.S. Oates, H.C. Lin, P. Chang, J.L. Wang, C.C. Huang, and Y.W. Yau, TSMC, Hsinchu, Taiwan

This work provides a new understanding of MIM capacitor degradation behavior under a wide range of constant current stress conditions. It was found that capacitance degrades with stress, but the behavior of the degradation strongly depends on the stress current density. A metal-insulator interlayer growth is observed using crosssectional transmission electron microscopy (TEM) micrographs to explain the observed

phenomenon.

IT03 TEST STRUCTURE DESIGN FOR PRECISE UNDERSTANDING OF Cu/LOW-k DIELECTRIC RELIABILITY—T.L. Tan, C.L. Gan, Nanyang Technological Univ., Singapore, A. Du, C.K. Cheng, Institute of Microelectronics, Singapore, C.M. Ng, and L. Chan, Chartered Semiconductor Mfg. Ltd, Singapore

Single line test structures are suggested for the failure analysis and reliability improvement development due to challenges in controlling the damage after electrical tests and pin-pointing sub-surface failures with present techniques. Three failure modes are presented, which demonstrate the importance of including different geometrical layouts for backend reliability

IT04 THEORETICAL ANALYSIS OF VACANCY TRANSPORTATION COMBINED WITH ELECTROMIGRATION AND STRESS INDUCED VOIDING—T. Nemoto, A.T. Yokobori Jr., and T. Murakawa, Tohoku Univ., Sendai, Japan

The effect of residual stress on vacancy transportation due to EM and SIV was investigated. A modified Huntington's equation was proposed to include the residual stress. Computer aided simulation can be applied to demonstrates void formation and failure in various combination of current density and residual stress

IT05 CHARACTERIZATION OF ELECTROMIGRATION PARAMETERS ON SINGLE DEVICE—L. Doyen, X. Federspiel, NXP, Crolles, France, D. Ney, STM, Crolles, France, E. Petitprez, Freescale, Crolles, France, V. Girault, STM, Crolles, France, L. Arnaud, CEA Grenoble-LETI, Crolles, France, and Y. Wouters, LTPCM, Saint-Martin-d'Hères, France

Careful analysis of resistance evolution with time during electromigration tests provides valuable information about damascene architecture and intrinsic electromigration behavior. We applied stress patterns consisting of temperature and/or current variations, and analyzed the resistance change events, to determine electromigration parameters (Ea and n) on single devices.

IT06 NEW DEGRADATION PHENOMENA OF STRESS-INDUCED VOIDING INSIDE VIA IN COPPER INTERCONNECTS—H. Matsuyama, M. Shiozu, T. Kouno, T. Suzuki, H. Ehara, S. Otsuka, T. Hosoda, T. Nakamura, Y. Mizushima, M. Miyajima, and K. Shono, Fujitsu, Tokyo, Japan

Stress Induced Voiding inside VIA has investigated in detail using three different kinds of test patterns. Resistance increase has been seen larger in "Extrusion Pattern" than in "Wide Pattern". It caused by voiding inside VIA. Resistance shift increase depends upon length of the narrow pattern of "Extrusion Pattern". Our new finding is that resistance shift through 10K hour is dominated by the "Body Metal area". These phenomena can be explained with the effect of vacancy diffusion through the path of the copper and barrier metal side interface

IT07 CHARACTERIZATION OF DEGRADATION OF 65 nm NODE VIA CHAINS AND SINGLE VIAS—X.Federspiel, S.Courtas, NXP, Crolles, France, and M. Gregoire, STM, Crolles, France

Using single via devices, we found that the evolution of resistance in time follows a parabolic regime up to 325°C, with activation energy of 1.0 eV. The good correlation with a simple Arrhenius relation also shows that there is no effect of thermoelastic stress on degradation.

IT08 ON THE INTERACTION BETWEEN INTER-METAL DIELECTRIC RELIABILITY AND ELECTROMIGRATION STRESS—Y. Li*, C. Bruynseraede, G. Groeseneken*, K. Maex*, and Z. Tokei, IMEC, Leuven, Belgium. *also K.U. Leuven, Belgium

In this study, the effect of copper electromigration stress on the reliability of a CVD SiOC:H inter-metal low k dielectric (k=3, porosity=7%, average pore size=1.8 nm) is investigated. The main finding is that the electromigration stress can degrade the TDDB lifetime of the SiOC:H lowk dielectric.

IT09 SIMULATIONS OF Cu GRAIN STRUCTURE EVOLUTION IN 3D-IC VIAS DUE TO THERMO-MECHANICAL STRESSES—M.O. Bloomfield, D.N. Bentz, and T.S. Cale, Rensselaer Polytechnic Institute, Troy, NY

We discuss stress-induced grain structure evolution in polycrystalline Cu, using 3D `grain-continuum' models; i.e., grain boundaries are represented and tracked, in an effort to establish design windows for inter-wafer Cu vias in 3D-ICs. Strain energies, generated by temperature changes, are computed and used to drive grain boundary motion.

IT10 INFLUENCE OF SURFACE CLEANING ON STRESSVOIDING AND ELECTROMIGRATION OF Cu DAMASCENE INTERCONNECTION—J.-P. Wang, Y.-K. Su, and J.F. Chen, National Cheng Kung Univ., Tainan, Taiwan

This paper is to study the effects of Cu surface clean process on stress voiding and electromigration of Cu dual damascene metallization. A superior Cu pre-cleaning process condition is developed to improve Cu stress- induced voiding (SIV) and electromigration (EM). Higher pre-clean bias-power and shorter pre-clean time demonstrate remarkable low via resistance and excellent Cu reliability performance.

IT11 INVESTIGATION OF VIA BOTTOM BARRIER INTEGRITY IMPACT ON ELECTROMIGRATION—O. Aubel, S. Thierbach, F. Koschinsky, F. Feustel, AMD Saxony LLC, Dresden, Germany, C.S. Hau-Riege, AMD, Sunnyvale, CA, and C. Zistl, AMD Saxony LLC, Dresden, Germany

We present results indicating a dramatic change of electromigration failure behavior. Due to a specially designed test structure the failure type (long runner) can be detected in regular electromigration testing by differences in the resistance behavior compared to standard failure. By extensive study we find a clear correlation between via-bottom-barrier integrity and the change in failure location.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION MY MEMORY

Co-Chairs: Chandra Mouli, Micron and Renichi Yamada, Hitachi

MY01 EFFECT OF INTERFACE BUFFER LAYER ON THE RELIABILITY OF ULTRA-THIN MgO TUNNEL JUNCTIONS FOR SPIN TRANSFER SWITCHING MRAM—K. Hosotani, Y. Asao, M. Nagamine, T. Ueda, H. Aikawa, N. Shimomura, S. Ikegawa, T. Kajiyama, S. Takahashi, A. Nitayama, and H. Yoda, Toshiba, Isogo-ku, Japan

Study of the reliability of ultra-thin MgO tunneling barriers for spin transfer switching magnetoresistive random access memory (MRAM) revealed MgO is an excellent film of little resistance drift. Precise control of CoFeB/MgO/CoFeB interface was found to be important to make highly reliable tunneling barriers.

MY02 IMPROVING THE ENDURANCE CHARACTERISTICS THROUGH BORON IMPLANT AT ACTIVE EDGE IN 1 G NAND FLASH—D. Kang, H. Shin, B.-G. Park, J.D. Lee, I.H. Park, S. Jang, Y. Song, H. Yoon, E. Lee, S. Seo, D. Chang, and W. Lee, Seoul National Univ., Seoul, Korea

The impact of Fowler-Nordheim current stressing on oxide and interface trap generation rate is studied for scaled, STI-isolated NAND cells. Improvement in endurance and bake retention with adjustments to boron doping in the edge of the active area is studied.

MY03 HOLE DISTRIBUTIONS IN NROM DEVICES: PROFILING TECHNIQUE AND CORRELATION TO MEMORY RETENTION—A. Padovani, Università di Ferrara, Ferrara, Italy, L. Larcher, and P. Pavan, Università di Modena, Reggio Emilia, Italy

This paper presents a combined simulation-experimental technique for profiling hole distribution in NROM devices. It also presents charge evolution through the same technique. Correlation between lateral field in nitride and degradation in post-cycling data retention time is discussed.

MY04 MEASUREMENT TECHNIQUE OF CARRIER MOBILITY IN SILICON NITRIDE AND ITS APPLICATION TO DATA RETENTION IN MONOS MEMORIES—K. Katayama, Renesas Technology Corp., Itami, Japan

A novel method to measure carrier mobilities in insulators such as silicon nitride was developed. The electric field dependence of the mobility in Si₃N₄ shows the trap barrier lowering proportional to the electric field in contrast with the Pool-Frenkel emission Theory.

MY05 ROLE OF OXIDE/NITRIDE INTERFACE TRAPS ON THE NANOCRYSTAL MEMORY CHARACTERISTICS—A. Gasperin, A. Cester, N. Wrachien, A. Paccagnella, Università di Padova, Padova, Italy, C. Gerardi, and V. Ancarani, STM, Catania, Italy

Threshold voltage evolution of nanocrystal memories under constant gate bias and different temperature was studied. The programmed cell shows an increase of the threshold voltage due to the motion of charge trapped at oxide/nitride interfaces. Electrical stress enhances this effect.

MY06 RELIABILITY STUDIES ON NON PLANAR DRAM CELL TRANSISTOR—M.J. Lee, S. Jin, C.-K. Baek, S.-Y. Park, H.-H. Park, Seoul National Univ., Seoul, Korea, S.-D. Lee, S.-W. Chung, J.-G. Jeong, S.-J. Hong, S.-W. Park, Hynix Semiconductor, Ichon-si Korea, I.-Y. Chung, Gyeongsang National Univ., Kyungnam, Korea, Y.J. Park, and H.S. Min, Seoul National Univ., Seoul, Korea

Leakage mechanism and device degradation due to Fowler-Nordheim and hot-carrier stress in recessed channel and other non-planar DRAM cell transistors are studied in this paper.

MY07 RELIABILITY OF A 90 nm EMBEDDED MULTI-TIME PROGRAMMABLE LOGIC NVM USING WORK-FUNCTION ENGINEERED TUNNELING DEVICE—B. Wang, Y. Ma, A. Horch, and R. Paulsen, Impinj, Seattle, WA

An embedded multi-time programmable (MTP) floating gate non-volatile memory (NVM) has been developed in a standard 90nm logic process. Using a work function engineered tunneling device and 70� tunneling oxide, excellent endurance (> 500 K cycles) was achieved. Reliability of the NVM is evaluated against the traditional tunneling device and a model is proposed to explain the observed reliability differences.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION PC PRODUCT & CIRCUIT RELIABILITY

Co-Chairs: Walter Riordan, Intel and Tom Anderson, Texas Instruments

PC01 IMPACT OF GATE TUNNELING LEAKAGE ON PERFORMANCES OF PHASE LOCKED LOOP CIRCUIT IN NANOSCALE CMOS TECHNOLOGY—J.-S. Chen and M.-D. Ker, National Chiao-Tung Univ., Hsinchu, Taiwan

The influence of gate tunneling leakage on the circuit performances of second-order phase locked loop (PLL) was analyzed and investigated for 90-nm CMOS process. MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. Locked time, static phase error, and jitter of second-order PLL are degraded by gate tunneling leakage of MOS capacitor in loop filter.

PC02 IMPACT OF NBTI ON SRAM ARRAY PERFORMANCE DUE TO PRODUCT BURN-IN STRESS—L. Wang, Q. Ye, R. Wong, and M. Liehr, IBM, East Fishkill, NY

Product Burn-in stresses are carried out on a 36M SRAM array processed with 65nm SOI technology. The shift of SRAM array Iddq and Vcsmin are analyzed with device reliability models and circuit simulation. The impacts from PFET NBTI and NFET Hot carrier effect on SRAM array degradation are discussed.

PC03 ON THE 6T-SRAM CELLS DEGRADATION CHARACTERIZATION IN ULTRA-SCALED CMOS TECHNOLOGIES—E. Nowak, M. Denais, STM, Crolles, France, and N. Gierczynski, NXP, Crolles, France

The 6T SRAM cell degradation characterization during writing, retention, and reading modes is investigated experimentally. Individual transistor degradation characteristics are measured and are related to NBTI and HCI degradation. The pass gate nmos hci degradation and pull-up pmos nbti degradation was measured using n-curve technique. The nbti recovery is observed when the bit stored in the cell is switched.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION PI PROCESS INTEGRATION RELIABILITY

Co-Chairs: Sanjay Rangan, Intel and Vijay Reddy, Texas Instruments

PI01 IMPROVED HOT CARRIER RELIABILITY IN STRAINED-CHANNEL NMOSFETs WITH TEOS BUFFER LAYER—C.-S. Lu, H.-C. Lin, National Chiao Tung Univ., Hsinchu, Taiwan, Y.-J. Lee, National Nano Device Labs, Hsinchu, Taiwan, and T.-Y. Huang, National Chiao Tung Univ., Hsinchu, Taiwan

Improvement in hot-carrier resistance for NMOS has been demonstrated using a modified SiN CESL scheme, through a thin buffer layer. The improvement is ascribed to the suppression of hydrogen diffusion from the SiN capping layer during deposition by the incorporation of the buffer layer.

PI02 EFFECT OF IN SITU PLASMA TREATMENT ON HIGH-k FILMS AFTER HIGH-k REMOVAL WITH PLASMA ETCHING FROM THE S/D REGION—B.S. Ju, S.C. Song, Sematech, Austin, TX, T.H. Lee, Univ. of Texas at Austin, Austin, TX, B. Sassman, C.Y. Kang, Sematech, Austin, TX, B.H. Lee, and R. Jammy, IBM assignee

This paper demonstrates a plasma etch technique for removing high-k dielectric from the source and drain (s/d) areas after metal/high-k gate stack patterning, along with potential anneal solutions to the plasma damage during the etch. With this etch process and O₂ treatment, excellent structural and electrical performance has been achieved.

PI03 HIGH PRESSURE DEUTERIUM ANNEALING EFFECT ON NANO-SCALE STRAINED CMOS DEVICES—S.-M. Cho, J.-H. Lee, Kyungpook National Univ., Daegu, Korea, M. Chang, M.-S. Jo, H.-S. Hwang, Gwangju Inst. of Sci. & Tech., J.-K. Lee, S.-B. Hwang, MagnaChip Semiconductor, Cheongju, Korea, and J.-H. Lee, Kyungpook National Univ., Daegu, Korea

High pressure deuterium annealing was applied to nano-scale strained CMOS device, its effect was characterized in terms of charge pumping, hot carrier, NBTI stress, and 1/f noise for the first time. Characteristics of tensile stressed NMOS were improved by the annealing. But compressive stressed PMOS devices showed degraded characteristics.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION SE SER

Chair: Ken Rodbell, IBM

SE01 QUANTIFYING THE EFFECTIVENESS OF GUARD BANDS IN REDUCING THE COLLECTED CHARGE LEADING TO SOFT ERRORS—B. Narasimham, Vanderbilt Univ. , Nashville, TN, R.L. Shuler, NASA Johnson Space Center, Houston, TX, J.D. Black, B.L. Bhuva, R.D. Schrimpf, A.F. Witulski, W.T. Holman, and L.W. Massengill, Vanderbilt Univ., Nashville, TN

An autonomous SET pulse-width measurement technique is used to quantify the effects of guard bands on the collected charge. Experimental results on a 0.35-um technology indicate guard bands reduce SET width by more than 30%. This corresponds to over 55% improvement in the SER of advanced technology combinational logic circuits.

SE02 A QUANTITATIVE ANALYSIS OF NEUTRON-INDUCED MULTI-CELL UPSET IN DEEP SUBMICRON SRAMs AND OF THE IMPACT DUE TO ANOMALOUS NOISE—H. Kameyama, Y. Yahagi, and E. Ibe, Renesas Technology, Tokyo, Japan

In recent years, "multi-cell upsets" (MCU's) have been a concern attracting much interest in the semiconductor reliability community. This poster describes the energy dependence of MBU's, the probability of MBU occurrences and the relationship between MBU's, real time SER events and neutron acceleration testing.

Wednesday, April 18, 7:00 p.m., Arcade

SECTION TR TRANSISTORS

Co-Chairs: Anand Krishnan, Texas Instruments and Souvik Mahapatra, IIT Mumbai

TR01 THE INFLUENCE OF GATE POLY-SILICON OXIDATION ON NEGATIVE BIAS TEMPERATURE INSTABILITY IN 3D FinFET—H. Lee, KAIST, Daejeon, Korea, C.-H. Lee, D. Park, Samsung Electronics, Yongin-City, Korea, and Y.-K. Choi, KAIST, Daejeon, Korea

This paper presents the effects of gate poly-silicon oxidation (GPOX) on negative bias temperature instability (NBTI) in buried channel bodytied and SOI FinFETs for the first time using a measurement technique without a recovery during a NBT-stress test. Gate length dependency of the NBTI on FinFETs with GPOX is analyzed with various gate oxide thicknesses, stress biases, substrate biases, and device structures. In addition, the proposed revamped geometry-aware reaction-diffusion model explains the GPOX effects on 3D FinFET with gate length dependency.

TR02 DEGRADATION DEPENDENT ON CHANNEL WIDTH IN SEQUENTIAL LATERAL SOLIDIFIED POLY-Si THIN FILM TRANSISTORS—H.-Y. Liang, S.-I. Hsieh, National Tsing Hua Univ. Hsin-chu, Taiwan, H.-T. Chen, ITRI, Hsin-chu, Taiwan, C.-J. Lin, and Y.-C. King, National Tsing Hua Univ., Hsin-chu, Taiwan

We investigated the impurity doping effect on resistivity with decomposition into surface, grain boundary, and impurity scattering by employing scattering model. Surface scattering is dominant for resistivity increase, while EM-induced Cu drift is suppressed as Al concentration increase. EM lifetime is improved by suppression of the Cu diffusion with piled-up Al at the top surface of Cu interconnects.

TR03 HOT CARRIER RELIABILITY OF STRAINED N-MOSFET WITH LATTICE MISMATCHED SOURCE/DRAIN STRESSORS—K.-W. Ang, National Univ. of Singapore & Institute of Microelectronics, Singapore, C. Wan, K.-J. Chui, National Univ. of Singapore, Singapore, C.-H. Tung, N. Balasubramanian, Institute of Microelectronics, Singapore, M.-F. Li, G. Samudra, and Y.-C. Yeo, National Univ. of Singapore, Singapore

The hot carrier reliability of a novel uniaxial tensile strained n-channel transistor with silicon-carbon (Si_1-yC_y) source and drain (S/D) regions is investigated for the first time. Strained n-FETs show reduced hot carrier lifetime than the control n-FETs when stressed at comparable I_sub/I_d ratio. Worst case hot carrier stressing is observed to occur at maximum substrate current I_sub condition which leads to a higher drive current I_Dsat degradation as compared to the V_GS =V_DS stress. At nominal operating voltages, strained n-FET is projected to have a hot carrier lifetime well exceeding the 10-years requirement, showing no severe reliability issues.

TR04 IDENTIFICATION OF A NEW POSITIVE BIAS AGING FAILURE MODE IN N-CHANNEL MOSFETs WITH PLASMA-NITRIDED SiO₂ OXIDE—V. Huard, NXP, Crolles, France, C. Guerin, C. Parthasarthy, STM, Crolles, France, K. Romanjek, and S. Vanbergue, NXP, Crolles, France

A new positive bias aging failure mode of N-CHANNEL MOSFETs with plasma-nitrided SiO₂ oxides is reported for the first time. Interface traps creation is main contributor of electrical paramrter shifts, since no transient effects are reported. Process impact and voltage/temperature extrapolation laws are studied.

TR05 THE IMPACT OF NITROGEN ON THE FREQUENCY DEPENDENCE OF NEGATIVE-BIAS TEMPERATURE INSTABILITY—S. Wang, D.S. Ang, and G.A. Du, Nanyang Technological Univ., Singapore

Negative-bias temperature instability (NBTI) of the ultra-thin oxynitride gate p-MOSFET is found to exhibit an inverse power-law dependence on the gate frequency. The frequency dependence is observed to become much weaker in more heavily nitrided gate devices. Results suggest that near-interface nitrogen-related deep-level hole traps, which can be generated rapidly but cannot be readily annealed upon removal of stress, play an important role on the frequency dependence of NBTI.

TR06 HISTORY DEPENDENT RECOVERY OF NBTI UNDER ALTERNATING DC AND AC STRESS—H. Kufluoglu, Purdue Univ., W. Lafayette, IN, C. Prasad, and M. Agostinelli, Intel, Hillsboro, OR

Fast NBTI recovery experiments performed for alternating DC and AC stress modes show that recovery behavior is strongly influenced by degradation history. Proper modeling of PMOS recovery in circuits as well as projections of product lifetime must comprehend the interaction of DC and AC usage states.

TR07 THE ENERGY-DRIVEN HOT CARRIER DEGRADATION MODES—C. Guerin, STM, Crolles, France, V. Huard, NXP, Crolles, France, and A. Bravaix, STM, Crolles, France,

In this work, we confirm that the energy is the driving force of hot carrier effects. When the energy is high, the LEM picture is still valid, but when energy is lowered, electron-electron scattering becomes dominant and for even lower energy multiple vibrational excitation mechanism takes the lead.

TR08 AN INVESTIGATION OF SELF-HEATING DEGRADATION OF METAL INDUCED LATERALLY CRYSTALLIZED n-TYPE POLYSILICON THIN FILM TRANSISTORS—H. Wang, M. Wang, Z. Yang, Soochow Univ., Suzhou, China, and M. Wong, Hong Kong Univ. of Sci. & Tech., Kowloon, Hong Kong

Self-heating degradation of n-type MILC polysilicon TFTs is systematically investigated under different stress powers. Two-stage degradation behaviors with turnaround effect at initial stage are characterized. An anomalous continuous field-effect mobility increase along with its Vg dependence shift is first observed. A consistent model is proposed to understand observed degradation characteristics.

TR09 UNIFIED PERSPECTIVE OF NBTI AND HOT-CARRIER DEGRADATION IN CMOS USING ON-THE-FLY BIAS PATTERNS—C.R. Parthasarathy, STM & L2MP-ISEN, Crolles, France, M. Denais, STM, Crolles, France, V. Huard, Philips, C. Guerin, G. Ribes, E. Vincent, STM, Crolles, France, and A.Bravaix, L2MP-ISEN, Crolles, France

We analyze NBTI and Channel Hot Carrier from a unified perspective using a novel technique of applying sequential stress biases and monitoring degradation on-the-fly. This way, we are able to segregate two distinct types of mechanisms during degradation. In particular, we gain vital insights into recovery phenomena using this methodology.