NBTI in p-MOSFETs: Characterization, Modeling, & Material Dependence

Negative Bias Temperature Instability (NBTI) is a serious reliability concern for Silicon Oxynitride (SiON) p-MOSFETs. This tutorial will focus on issues involving proper selection of stress condition and measurement technique as well as choice of extrapolation model and methodology to obtain accurate device lifetime. After a brief introduction to the problem, the impact of NBTI stress on p-MOSFET parameters will be discussed, along with a review of various techniques to directly characterize traps generated during stress. The very important problem of the impact of measurement delay on measured degradation (due to NBTI recovery) will be discussed, and several fast measurement schemes that avoid (or reduce) measurement delay will be reviewed. It will be shown that NBTI time dependence not only depends on measurement technique, but also on stress bias, and the unwanted impact of hot hole generation (due to improper choice of stress bias) on overall degradation will be discussed. NBTI data measured over a wide class of films (plasma & thermal nitridation, variation in N₂ dose, EOT) will be presented, and the time and temperature dependence of most of these films will be shown to be governed by interface trap generation and can be explained by the well-known Reaction Diffusion model. Cases (material and stress dependence) when additional hole trapping is seen will also be discussed. It will be shown that NBTI depends on oxide field (not stress voltage), and the bias dependence of NBTI will be discussed in the framework of inversion layer hole assisted breaking of interfacial Si-H bonds. Finally, NBTI recovery and frequency (in)dependence under AC stress will be discussed, and the relief in NBTI lifetime when qualified under AC stress will be shown

Souvik Mahapatra

Souvik Mahapatra received his PhD in Electrical Engineering from IIT Bombay, India in 1999. He worked at Bell Laboratories, Murray Hill, NJ during 2000-01 and since 2002 he is with the Department of Electrical Engineering, IIT Bombay, where he is presently an Associate Professor. His research interests are CMOS device and Flash memory reliability. He has published more than 60 papers in referred international journals and conferences, delivered invited talks at major international conferences including the IEDM, given tutorials at IRPS and served as a reviewer for several international journals and conferences. He is a member of the IEEE.