Soft Errors - History, Trends and Challenges

We present the basic definitions and sources of soft errors followed by the basic upset mechanisms for a commonly used 6T SRAM cell. SEL (single event latchup) is discussed afterwards in detail. We will present technology scaling trends and mitigation techniques based on process mitigation and design mitigation. Finally we present experimental data from 250nm to 65nm technology nodes including single bit and multi bit upset studies. Finally, a quick outlook for different memory/logic platforms.

Helmut Puchner

Helmut Puchner was born in Steyr, Austria. He received the 'Diplomingenieur' degree in electrical engineering and the PhD degree from the Vienna Technical University in 1992 and 1996, respectively. He joined LSI Logic Corp. in Santa Clara, CA as a device development engineer in 1997. In 2002 he joined Cypress Semiconductor, where he is responsible for transistor developement, TCAD, DFM, and device reliability. His research interests include the development of advanced CMOS structures and power transistors including their reliability aspects. He has published more than 60 conference/journal articles and holds 18 US patents.