Latch-up
Steven H. Voldman, IBM
Latch-up continues to be of interest today in advanced CMOS, mixed signal (MS) CMOS, RF CMOS, BiCMOS, and BiCMOS silicon germanium. The latch-up tutorial will provide a discussion on device-level latch-up physics, latch-up metrics and design criteria, latch-up test structures, test methods, latch-up measurement techniques, device-level CAD simulation, and new latch-up issues. Both internal and external latch-up phenomenon, as well as DC and transient latch-up, will be addressed. Latch-up structures, guard ring physics, and characterization will be discussed in depth. The tutorial will provide examples of discussion on latch-up device level simulation using latch-up scaling issues as examples. Semiconductor process sensitivities to shallow trench isolation (STI), silicides, retrograde n-wells, and p-wells in single-well and dual-well CMOS will be discussed. Latch-up process solutions, such as heavily doped buried layers (HDBL), deep trench (DT), trench isolation (TI) and triple wells will be shown. Latch-up testing, characterization methods, and latch-up test standards will also be discussed. The tutorial will end with a discussion on state-of-the-art latch-up issues and characterization techniques and tools.
Those attending this course will understand the fundamentals of CMOS latch-up. The course will focus on theory, test structures, application, experimental results, simulation and CAD design systems. Those attending will also understand the impact of design, semiconductor process and circuits on CMOS latch-up.
Steven H. Voldman
Steven H. Voldman is the first IEEE Fellow in ESD phenomenon field for "contributions to electrostatic discharge protection in CMOS, SOI and SiGe technologies" at the IRPS 2003 in Dallas, Texas.is an ESD/Latchup engineer/scientist in IBM's RF Silicon Germanium development team. He received his B.S. in Eng. Science from the Univ. of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from MIT; MS Eng. Physics (1986) and Ph.D EE (1991) from the Univ. of Vermont under IBM's Resident Study Fellow program. As a reliability/device engineer since 1982, his work involved bipolar and CMOS SRAM SER, MOSFET GIDL, hot electron, epitaxy/well design, CMOS latchup, and ESD. He has authored ESD and latchup publications in the area of MOSFET scaling, device simulation, Cu, low-k, MR heads, CMOS, SOI, SiGe and SiGeC technology and recently authored an article in the Oct. 2002 Scientific American. He was responsible for defining the IBM ESD/latchup strategy for CMOS, BiCMOS and RF CMOS from 1986 to 2004. Voldman served as SEMATECH ESD Chair (1996-2000), EOS/ESD TPC, Vice Chair, and General Chair (1999-2002), IRPS ESD/Latchup Chairman (2003, 2004), EOS/ESD 2003 Past General Chairman, ESD Assoc. Board of Directors, ESD TLP and VF-TLP Work Group Standards Chairman, ESD Education Committee, IPFA Tech. Program Steering Committee, ISQED Committee, Taiwan ESD Conference Technical Program Committee, International ESD Workshop (IEW) as well as providing ESD and latchup tutorials for the IRPS, IPFA and ESD Symposium. Voldman has served on the ESD Association Board of Directors from 2000 to 2007 and is founder and presently chairman of the "ESD on Campus" program that has brought ESD lectures across the US, Singapore, Malaysia, Thailand, Taiwan and China. Voldman is author of the first ESD book series, whose texts are ESD: Physics and Devices, ESD: Circuits and Devices, and ESD: RF Technology and Circuits. He is a recipient of the ESD Best Paper (1995), ESD Best Presentation (1997), the IBM 55th Plateau Invention Achievement Award, has 160 issued US patents and 70 US patents pending, over 150 publications, Additionally, he has been recently highlighted in EE Times Times People, Pour La Science and Intellectual Property Law and Business.