On-chip ESD Protection

A safe path for dissipation of static charge must be provided between any arbitrary pair of pins, otherwise yield may be compromised and/or ESD induced failures may be experienced by customers. This tutorial will provide an overview of the various devices available for ESD protection in deep sub-micron CMOS and BiCMOS technologies. This will be followed by an examination of full-chip ESD protection networks. The special challenges associated with RF I/Os will be described.

Elyse Rosenbaum

http://www.icims.csl.uiuc.edu/~elyse