CMOS Scaling & Gate Stack Technology Trends
Raj Jammy, SEMATECH/IBM
&
Prashant Majhi, SEMATECH/Intel
In this tutorial, efforts to extend the lifetime of CMOS technology will be reviewed along with impact on device performance and reliability. After 30 years of aggressive downsizing of transistors, geometrical scaling has clearly reached fundamental material limits, and is now in the era where further scaling can be realized mainly by new materials and/or device architecture. Traditional gate stacks based on SiO2 and poly-Si are now being replaced by high-k and metal gates. Strain engineering by means of SiGe in source-drain regions along with stress inducing layers are options being practiced since 90nm generation to boost mobility in the channels. New approaches to form low resistance ultra-shallow junctions with high active dopant concentrations are under investigation and likely to be employed in the next generation devices. Options to reduce barrier height of source-drain contacts are also under evaluation. All these options require integration of novel material systems on to a traditional Si platform, and are challenging from an implementation and reliability perspective. First part of this tutorial will summarize the technical requirements and challenges for future CMOS technologies.
The well tested and long used Si channel itself appears to be running out of steam in being able to provide for low-power, high-performance needs in highly scaled devices beyond the 22nm technology generation. Along these lines, several high-mobility materials are being investigated as potential channel materials for next-generation CMOS devices. There has been a surge in research activities on high mobility channel materials integrated on Si platform, primarily to investigate roadblocks (if any) based on intrinsic properties. Generally, the high-mobility channel materials (group IV and III-V) have a larger lattice constant, lower band-gap, lower thermal stability and lower dopant solubility limits; these characteristics directly challenge a) heterogeneous integration on Si platform, b) controlled short channel properties, c) formation of stable gate stacks, and d) low external resistance, respectively. This tutorial will summarize some of the key challenges, status and opportunities for addressing the aforementioned issues, discuss about the potential reliability challenges for the future generation MOSFET options.
Rajarao Jammy
Rajarao “Raj” Jammy joined Sematech for a three-year assignment from IBM. He served as a manager of Advanced CMOS Gate Stack and Surface Preparation Technologies at the T.J. Watson Research Center in Yorktown Heights, NY and previously managed the Thermal Processes and Surface Preparation Group in the DRAM development alliance between IBM and Infineon. He holds a doctorate in electrical engineering from Northwestern Univ. and a master’s from the Univ. of Rochester in Rochester, NY. He also earned a bachelor’s in electrical engineering from Bangalore Univ. in Bangalore, India. He holds 35 US patents and has co-authored nearly 50 invited/peer-reviewed papers in professional journals.
Prashant Majhi