Reliability Implication in CMOS & Gate Stack Scaling

The near term approach to extend CMOS lifetime is to import new gate stack materials such as high-k dielectrics and metal gate electrodes in to traditional CMOS device structures. Recent reports show that the major technical issues impeding the implementation of alternative gate stack materials have been solved. In this tutorial, major process and integration approaches and issues will be introduced and the reliability status of the-state-of-the-art devices from this approach will be summarized. This application of new materials brought unique electrical characterization challenges which require different test methodologies for correct assessment. The degradation mechanisms and models are also different from the conventional ones used for silicon based devices. By applying electrical characterization techniques with high time and spatial resolution (in particular, pulsed Id-Vg measurements in the nanoseconds range, variable frequency charge pumping, etc.) along with profiling of the stack composition using high resolution EELS, XPS, ESR, etc., coupled with ab initio modeling of the dielectric atomic structures, electrically active defects have been identified and physical models for device life-time evaluation were developed.

Rino Choi

Rino Choi received his B.S. (1992) and M.S. (1994) in the inorganic materials engineering of the Seoul National Univ.. He received the Ph.D. in materials science and engineering (2004) from the UT at Austin. He worked for Daewoo Motors Company from 1994 to 1999, where he worked as a development and test engineer. Since 1999, he studied various high-k dielectrics and published more than 50 journal and conference papers. After his graduation, he has been continuing the research on the electrical characterization and reliability of advanced gate stacks at Sematech.

Gennadi Bersuker

Gennadi Bersuker completed his M.S. and Ph.D. in physics at the Leningrad State Univ. and Kishinev State Univ., respectively. After graduation, he joined Moldavian Academy of Sciences, and then worked at Leiden Univ. (The Netherlands) and the UT at Austin. Since 1994, he has been working at Sematech on process induced charging damage, electrical characterization of Cu/low-k interconnect, high-k gate stacks and advanced CMOS process development.