Flash Process Technology Scaling Trends and their Impact to Reliability

The need to increase memory bit density two-fold every generation, which is 15 months or less in the case of NAND Flash memory, results in ever shrinking cell capacitance with fewer and fewer electrons stored (>100 electrons in the 3x nm node for NAND Flash) resulting in increased sensitivity to both intrinsic and extrinsic reliability phenomenon. In additional new and exotic materials, including nano-crystals and other trap materials which are being pursued as classical floating gate replacements and High K dielectrics both as tunneling and blocking dielectrics, will lead to potentially different and unique reliability mechanisms and distinctive interactions with process modules. In this talk I will review some of the key scaling challenges for non-volatile Flash memories and the foremost options being explored by the industry and their implications to reliability.

Kiran Pangal

Kiran Pangal is with Intel Corporation and currently he is the Technology manager in the Joint Development Program with Micron Technologies responsible for advanced NAND Flash process development. He received his Ph. D. in Electrical engineering from Princeton University in 1999 and his thesis topic being study of crystallization of a-Si films and applications in thin film transistors. He joined Intel Corporation, Santa Clara after his graduation and has worked as process integration engineer on the 130 nm NOR Flash technology development working on the front end process and tunnel oxide reliability improvements. In 2005, he won the Intel's Achievement Award for his work on tunnel oxide process improvements enabling Flash MLC scaling. Subsequently he was the process integration manager responsible for 90 nm NOR Flash technology development from early development through ramp and transfer to high volume manufacturing.