Gate Dielectrics YEAR-IN-REVIEW

The Gate Dielectrics Year-in-Review will cover an extensive summary of the most exciting studies on defect generation in silicon dioxide and high-K material that were published in year 2006 and 2007. With High-K being the choice for gate dielectrics for sub 45 nm technology, a number of reliability challenges need to be answered. The review will focus on issues like Vt instability and bulk defect generation that limits Time Dependent Dielectric Breakdown (TDDB) in High-K and ultra-thin SiO₂.

Tanya Nigam

Tanya Nigam was born in Kanpur, India. She received her Bachelor's degree in Physics (Hons.) from St. Stephens College, Delhi University. She obtained a M.Sc in Physics from IIT Kanpur and a M.Sc in Electrical Engineering from the Katholieke Universiteit Leuven in 1995. Between 1995 and 1999, she worked towards a Ph.D in the area of ultra-thin gate oxides at IMEC, Belgium. From 1999 until 2001, Tanya was a Member of Technical Staff at Bell Labs. During this period she worked on novel device geometries to overcome sub-50nm device challenges. From 2001 until 2005, she was with Agere Systems, formerly the Microelectronics Division of Lucent Technology. At Agere, she worked on reliability issues for power LDMOS devices, and HCI/NBTI reliability concerns for CMOS. Since October 2005 Tanya is Senior Staff at Cypress Semiconductor involved in the optimization of 65nm CMOS. She has co-authored 25 papers in Journals and Conferences.