SUNDAY

110 FRONT-END RELIABILITY SESSION

120: BACK-END RELIABILITY SESSION

130: PRODUCT RELIABILITY

140: FA AND PACKAGING SESSION

150: ESD AND LATCH-UP SESSION

MONDAY

210: CIRCUIT RELIABILITY SESSION

220: MEMORY SESSION

230: TECHNOLOGY, CIRCUIT AND CHIP RELIABILITY SESSION

240: PROCESS RELIABILITY SESSION

300:    Reliability-Year-In-Review

SUNDAY

110 FRONT-END RELIABILITY SESSION

111: Gate Dielectric Reliability: SiO₂ based dielectric

Ernest Y. Wu, IBM
and
Jordi Suñé, Universitat Autónoma de Barcelona, SPAIN

Dielectric reliability such as gate oxide reliability has entered a new era with ever high demands for increase applied voltage and high integration with one billion transistors or more on a single chip. Although oxide thickness has reached to its minimum thickness around 1.0 nm with only a few atoms due to the more consumption constraint, to maintain the same reliability specifications under these extraordinary conditions requires an excellent and fundamental understanding of gate oxide failure mechanisms and innovative evaluation- and projection- methodologies. In this tutorial, we will provide an overview for dielectric breakdown statistics and voltage acceleration models such as power-law voltage acceleration model. In particular, the experimental evidences and theoretical modeling will be presented in a combined fashion to facilitate the overall understanding. We will review a new but also promising physics-based percolation model, recently reported, which is capable of explaining both the first breakdown and post-breakdown statistical behaviors. To fully account for circuit reliability at product levels, new post breakdown mode such as progressive breakdown must be considered and carefully implemented in a comprehensive methodology and at the same time to provide additional reliability margin. We will also review the most recent advance in the understanding of statistical distribution and voltage acceleration of progressive breakdown mode. Some fallacy regarding the use of first breakdown and post breakdown statistics will be discussed so that a standard projection methodology can be established. While establishing a sound physical understanding of breakdown mechanisms and statistics is always important, this tutorial will also focus on many aspects of practical qualifications in daily work of reliability engineers. To this end, a few examples of first breakdown and progressive breakdown projection methodology will be provided at the end of this tutorial in attempt to eliminate some of the confusion regarding reliability projection.

Ernest Y. Wu

Jordi Suñé

112: Fast measurements techniques for determination of degradation due to NBTI

Hans Reisinger, Infineon

It is well known that the NBTI effect involves very short time constants in degradation as well as in recovery. A significant part of the degradation recovers as soon as the stress is released. This recovery is in a much shorter time than the typical measuring delay which can be achieved with commercial analyzers. This measuring delay has a considerable effect on drift curves and extrapolations. Thus alternative measuring techniques and instruments have been developed with the goal to obtain curves as close as possible to the "true", recovery-free drift curve. In the tutorial a comparison of all fast (OTF, fast VT, fast ramp, charge pumping) as well as conventional slow electrical measurement techniques will be given. A focus will be the treatment of systematic errors and statistical errors due to noise and the discussion of advantages and disadvantages of the different techniques. An estimation of the degree of achieving the "true" drift curve will be given. The tutorial will give details of specialized NBTI characterization setups and discuss their performance limits. Also covered will be the capabilities and limits of standard analyzers and new analyzers announnced by equipment manufacturers. Sample specific problems, e.g. noise as a function of MOSFET geometry and other problems of narrow devices will be briefly sketched.

Hans Reisinger

113: Negative Bias Temperature Instability: Modeling Challenges and Perspectives

Tibor Grasser, Institute for Microelectronics

Modeling efforts of negative bias temperature instability date back to the work of Jeppson and Svensson in 1977, who proposed the basic form of the popular reaction-diffusion model.  This model is still at the heart of many modeling attempts today.  However, recent research indicates that even refined variants of this model, while getting some features of NBTI right, cannot capture some crucial aspects of the phenomenon, most notably its ubiquitous logarithmically-decaying recovery phase. Consequently, alternative models have been developed.  Some of these models, like the extensions based on dispersive transport of the released hydrogen species, predict like the underlying reaction-diffusion model, that the overall degradation is controlled by (dispersive) diffusion of hydrogen.  Alternatively, some models assume that the actual depassivation reaction is the rate limiting step.  On top of the creation of interface states, some authors have argued that trapped holes form a considerable part of the overall degradation. Despite all the efforts, however, no universally accepted theory of NBTI is available today, with published models covering only some aspects of the phenomenon and giving contradictory predictions of other aspects.  This tutorial attempts to give a broad review of published modeling attempts, comparing their strengths and weaknesses, and eventually listing the requirements for a more complete model of NBTI.

Tibor Grasser

120: BACK-END RELIABILITY SESSION

121: Electromigration, the complete story.....maybe

Jim Lloyd, IBM

Electromigration remains one of the most important reliability issues in semiconductor technology. The change to Cu metallization has only delayed, not eliminated the threat. In addition, electromigration in solder interconnect has been shown to be significant, especially with the introduction of led-free solders. For the uninitiated, the subject appears to be complex and mysterious, however, with an understanding of the basic physics and materials science of electromigration, the mysteries begin to vanish enabling the enlightened engineer to make a have confidence in designing and interpreting tests that lead to reliability projections and design rule generations.

This tutorial will begin with the basic physics of electromigration leading to an understanding of the meaning and correct applications of Black's Law, the Blech Length effect, current crowding and other often more subtle effects. The latest developments in electromigration theory will then be presented in a manner that will generate confidence in the student.

Jim Lloyd

122: Stress migration in copper interconnects from basics to design

Martina Hommel, Infineon Technologies AG

Mechanical stress in copper interconnects cannot be avoided during processing. In a metallization stack of a microelectronic chip, many materials with different mechanical properties like the thermal coefficient of expansion are in close neighborhood. This leads to high mechanical stresses during the temperature steps of subsequent thermal cycles after deposition. This can already damage the connection between via and metal line. After storage of the metal stack at constant temperature, a time-dependent voiding mechanism by stress driven vacancy drift can occur. This can cause a final failure of the electrical connection. Hence there are some technological influences like the via size and the via aspect ratio which can have an influence on stress migration. These aspects will be discussed in this tutorial. On the other hand the design of the connected metal has a large influence on the stress migration reliability, because it determines the vacancy reservoir size and most likely also the intrinsic stress of the structure. Many correlations between design and stress migration behavior have been observed and will be reviewed in this tutorial.

Martina Hommel

123: Addressing Cu/Low-k Dielectric TDDB Reliability Challenges

Fen Chen, IBM

With the wide application of low-k and ultra-low-k dielectric materials at the 90nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification. Low-k time-dependent dielectric breakdown (TDDB) is usually considered as one of the most important reliability issues during Cu/low-k technology development because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO₂ dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In this tutorial, in the first part, a proposed qualification procedure for comprehensive evaluation of low-k dielectric integrity will be outlined. In the second part, some basic aspects of low-k TDDB characteristics such as t_BD statistical distribution, field acceleration model, thermal acceleration kinetics, area scaling law, and spacing scaling trend will be thoroughly reviewed. The mechanism responsible for the TDDB deterioration of low-k dielectric in fully integrated interconnects will be discussed. In part 3, as low-k TDDB has been found to be sensitive to all aspects of integration, the effects of process variations on low-k TDDB degradation will be covered. Some key aspects which need to be carefully addressed to control overall low-k TDDB performance from process and integration side will be proposed. Where possible, an introduction of emerging air gap TDDB reliability issue for upcoming technology nodes will also be done.

Fen Chen

Fen Chen received a M.S. degree in Physics in 1994, and a Ph.D. degree in Electrical Engineering from University of Delaware in 1998. From 1997 to 1998, he was with IBM System Group at Rochester, MN and Intel Component Research at Santa Clara, CA as a graduate intern working on system stress and IC interconnect reliability. He joined IBM microelectronics at Essex Junction, VT in 1998 as a technology reliability engineer and has worked on semiconductor technology reliability issues including both FEOL and BEOL wearout mechanisms since that time. During the past several years he has focused on low-k ILD TDDB issue for various IBM and IBM Alliance development programs at 90nm, 65nm, 45nm, and 32nm technology nodes.

124: Reliability at the heart of scaling: Challenges and emerging solutions for 32 and 22 nm technology

Roey Shaviv, Novellus Systems

Reliability is emerging as a key challenge to Moore's Law on several important fronts. The ITRS projects a non-linear increase in J_max, while theoretical studies predict a steep decrease in the same property. Therefore, electromigration becomes a major challenge for continuing the historical scaling trends. Solutions to the electromigration challenge, such as selective Co cap, cause degradation in dielectric reliability, and an increase in RC delay. This problem is further exacerbated by integration of ultra low-k dielectrics (k < 2.6) and/or air gaps to remedy the increase in RC delay as dimensions of interconnect shrink. Moreover, line edge roughness, associated with shrinking dimensions, create variations in the electric field between the metal lines of comb capacitors, with an additional detrimental effect on dielectric reliability. Hence, an integrated solution, addressing both electromigration and dielectric reliability, becomes the heart of technology scaling.

This tutorial will review the state of the art of emerging solutions to these key challenges. In particular, it will address integrated approaches that would enable sustaining Moore's law.

Roey Shaviv

Roey Shaviv received his Ph.D. in chemistry in 1988 from the University of Michigan, in Ann Arbor. He is a senior integration and applications technologist at Novellus Systems Inc. He joined Novellus in 2001 and is specializing in reliability and integration issues associated with copper / low k interconnects. Prior it this, he was the Etch Engineering Section Head, and earlier the Thin Films and CMP Engineering Section Head, at Tower Semiconductors. He was a Lecturer at the Chemistry Department of the University of Michigan and a Research Associate in the Chemistry Department of University of Illinois, Chicago.

130: PRODUCT RELIABILITY

131: Product qualification and reliability

Carole Graas, IBM

Product qualifications are an essential part of doing business in today’s semiconductor industry. Whether shipping packaged chips or untested wafers, a chip maker needs to know intimately what his fabricator is producing, and whether the products he ships meet his customer’s needs – at ‘time zero’ or after years of service. A properly planned and executed qualification allows to meet this goal.

This tutorial covers the many activities, experiments, considerations, and opportunities that represent a thoughtfully designed qualification. While the industry has developed standards aimed at guiding the implementation of numerous aspects of product qualifications, the field remains largely an art as much as a science. Prior experience, team synergies, anticipation, cross-functional expertise, and reaction to uncovered issues, all contribute to the success of a qualification.

A successful product qualification starts with in-depth understanding of customer objectives, product use conditions, any new technology features, and potential chip design sensitivities. In addition to product reliability stressing, it requires the timely closure of technology and package qualifications, the implementation of manufacturing line process controls, ESD and latchup characterization, and soft-error rate evaluations. Technology qualifications characterize wearout mechanisms and ensure that they are properly ‘designed-out’ of product chips. The product qualification can subsequently focus on the major two remaining classes of potential failure modes – systematic and defect related. Systematic failure modes generally involve a combination of circuit design features and process sensitivities, hence can be detected with relatively small product stress sample sizes (but they can usually not be detected by testsites). Defect failure modes are strictly the result of process limitations, and require carefully planned reliability stress experiments to be effectively accounted for. The types of defects uncovered by accelerated stressing have evolved over time. In today’s nano-process technologies, they often cause parametric drift, and can elude traditional as well as sophisticated imaging techniques.

The prediction of chip early and average failure rates (EFR and AFR respectively) in their intended use environment is enabled by reliability modeling. Voltage and temperature accelerated stressing is the toolset used by reliability engineers to produce models suitable for failure rate sizings. A number of considerations enter into the design and interpretation of stress results, including the proper formulation of assumptions. Product stresses designed to specifically produce a range of failures modes afford the greatest opportunity for predictive modeling as well as manufacturing line learning. They require, however, that sufficient acceleration be applied during stress, a condition that an increasing number of today’s chip designs cannot support, due to either power limitations, or lack of sufficient functionality margins. For this reason, alternative, low-acceleration product stress strategies are often used, an approach that lacks the predictive benefits often sought-after by customers.

Outcomes of today’s thorough product qualifications are far more complex than a mere seal of approval and publication of a report. Manufacturing line improvement actions rely on qualification findings. Design and technology development strategies can be profoundly influenced by such results. And finally, the judicious definition of reliability screens and test strategies is a critical enabler of manufacturing success. Voltage screens, thermal cycling, burn-in, and product guardbanding, while expensive, can all be effective tools in the quest for continuous improvement while meeting aggressive technology deployment objectives.

Ultimately, it is when field data confirm predictions drawn by qualification work and line monitoring programs, that reliability and qualifications engineers are able to integrate their learning into an experience base critical for the development of future generation qualification plans. While the contents of qualifications can be modulated according to use conditions and customers expectations, the engineering rigor necessary to properly close any uncovered issues must never vary.

With the continuing introduction of new materials, and the use ever more challenging technology groundrules, successful and timely product qualifications will continue to require combinations of expertise, insight, and experience. New defect and systematic failure modes can be expected, resulting in increasing customization of qualification plans. It is through careful balancing of schedule limitations, customer requirements, qualification scope, and technology innovations that successful manufacturers will continue to produce reliable products for tomorrow’s challenging microelectronics markets, and the qualifications engineer plays a central role in solving this equation.

Carole Graas

Dr. Carole Graas manages ASICs and Foundry Product Qualifications and Reliability in the Systems and Technology Group of IBM in Essex Junction, Vermont. She graduated from the University of Paris, the ESEM Engineering School, and the University of Orleans in France, prior to completing her Ph.D. in Materials Science in the US at the Colorado School of Mines. She started her microelectronics career in 1989 when she joined Texas Instruments in Dallas TX as a process development engineer. She held various engineering and management positions at TI, before returning to Europe in 1998 as a member of the International Technology Transfer Management group of Siemens Microelectronics. She was then appointed as the reliability functional manager for the joint IBM, Toshiba and Siemens/Infineon DRAM Development Alliance based in East Fishkill, NY. She joined IBM’s Site Assurance organization in 2003, where she has since focused her interests on product qualifications and reliability. She has published numerous technology reliability papers and holds several patents. She was the 2006 General Chair of the IEEE International Reliability Physics Symposium.

133: RF product reliability

William J. Roesch, TriQuint Semiconductor, Inc.

Introduction. The highest performing RF products are constructed using compound semiconductors. Although compound semiconductors have been around since the beginning of solid state technology, the commercialization and "catch up" phase started in earnest just about 20 years ago. Although it has a certain allure, new technology has unfortunately carried a suspicion of reliability risk. This tutorial will address the question: What has happened with RF Product Reliability over the past 20 years? After this brief review, we will turn to: What's left to be done in compound semiconductor reliability? The intent of this discussion is to provide information on: 1) Identification of the reliability issues, 2) Coming to grips with the issues, and 3) Offering a roadmap to address the issues.

RF Reliability Basics. The basics start off with defining the vocabulary on units of reliability, roles of reliability in product development, and goals of reliability in end applications. Next, the aspects of reliability, in terms of causes of unreliability will be discussed.

Understanding Mechanisms. The three keys to reliability prediction are: 1) knowledge of the root cause failure mechanisms, 2) measurement of degradation distributions, and 3) characterization of acceleration factors. Measurements in the key areas of Failure Mechanisms, Failure Distributions, and Acceleration Factors will be mentioned _ with emphasis on reliability methodology and results for at least one specific example. Product, technology, and package mechanisms will be described. The prevalence of accelerated test fallout mechanisms and customer fallout mechanisms will be compared.

Using the Right Acceleration. If we are to make predictions about reliability, we must be able to accelerate the failure mechanisms without generating new issues. Thermal acceleration is easy, but that doesn't make it the right thing to do. An understanding of mechanisms and degradation distributions can help us to look where acceleration might be less understood. To help, we need to talk more with our customers. Their use of the devices can give clues as to what types of acceleration are most applicable. For example, thermal excursions, voltage, current density, and humidity might be preferable to high temperature acceleration. With few exceptions, the reliability investigations on RF circuits over the past two decades have evolved to rely on thermally accelerated wearout failure mechanisms. Regardless of the measured lifetimes, there have been no wearout failures reported during use of the circuits. Instead, customers do report measurable defect rates and early life failures that often match-up with yield fallout failure mechanisms. This discussion will summarize various mechanisms, while focusing on yield and reliability relationships which are intertwined with early lifetimes of products.

Being Innovative. There are a few obvious improvement tactics available to compound semiconductor reliability engineers. Some tactics are similar to what are used by mainstream silicon folks, and some are unique to the special technologies. As the overall reliability improves, degradation becomes elusive. An alternate method of using yield correlations is an innovative example to predict failure rates. If yield fallout also disappears, we can use new tricks such as physical amplification of defects in order to extend our predictive capability. Recent compound semiconductor breakthroughs with innovative tests such as "bubble tests," power cycling, and "breakdown walkout," are the kind of tactics that can put compound semiconductors ahead of our silicon-based solid state relatives.

Strategy to Excel. We've touted the technology differences as defense for the RF Product niche; why not use the reliability differences as well? Because of the unique mechanisms and absence of the silicon problems, compound semiconductors have an opportunity to demonstrate exceptional reliability

Bill Roesch

Bill Roesch has a BSEE degree in Electrical and Computer Engineering from Oregon State University. He started his engineering career at Tektronix; scrutinizing component reliability for five years. In 1985, Bill joined TriQuint Semiconductor to explore aging, traumatizing, dissecting, and improving compound semiconductor devices so that they could be commercialized in GPS, fiber optic, cell phone, and wireless communication applications. For the past twelve years, Roesch guided the quality and reliability engineering group at TriQuint's Hillsboro, Oregon, factory. In 2007, Bill was designated a TriQuint Fellow in Reliability Science and Engineering. He has presented over 30 technical publications on GaAs reliability and has earned 7 best paper awards. For his innovative techniques and device physics insight, Bill was recently inducted into the Oregon State University Academy of Distinguished Engineers. Bill has been invited to deliver tutorials at Portland State University, the Aerospace Corporation, JPL, NASA, and DARPA.

134: Understanding and Mitigating the
Effects of Radiation in Advanced CMOS Technologies

Ronald Lacoe, The Aerospace Corporation
PO Box 92957 M2-244, Los Angeles, CA
ronald.c.lacoe@aero.org

There is a need to operate in severe radiation requirements for some applications. These include aviation and space applications, medical instrumentation, nuclear power technology and high-energy accelerators. This tutorial will discuss the effects of radiation on advanced CMOS technologies, as well as design approaches to mitigate these effects. This will include a discussion of the effects of total-dose ionizing radiation on such parameters as threshold voltage, off-state current and transconductance. Recent data will be presented that indicates there is a trend toward advanced total dose hardness as CMOS continues to scale. Radiation effects that produce bit-flips will be discussed. This will include soft error rate SER, single-event transients (SETs), and single-event latchup (SEL). Mitigation techniques will be discussed in depth, including edge-less and enclosed transistors to mitigate total-dose-induced edge leakage and approaches to harden the field-oxide/STI to prevent inter-device leakage. Similarly, mitigation techniques for SER,SET, and SEL will be presented. Finally, these hardening techniques will be discussed in terms of area, power and performance penalties.

Ronald Lacoe

Ronald Lacoe received his B.S., M.S., and Ph.D. in Physics from the University of California, Los Angeles in 1974, 1977, and 1983, respectively. He attended graduate school as a Hughes Aircraft Fellow and worked at the Hughes Research Laboratory in Malibu, California while earning his Ph.D. degree. After receiving his Ph.D., Dr. Lacoe was a joint NSF/CNRS Fellow at the University of Paris-South from 1984-1986, where he worked on reduced-dimensional systems and organic superconductivity. Dr. Lacoe joined The Aerospace Corporation in 1987 as Member of the Technical Staff and is currently a Senior Scientist in the Microelectronics Technology Department, Laboratory Operations. He is responsible for research in the areas of microelectronics reliability and radiation hardness for microelectronics that will be employed in Air Force space programs. Dr. Lacoe has published extensively on the use of commercial microelectronics processes for fabricating radiation-hardened components for space and is also an expert on microelectronic reliability issues. Dr. Lacoe has published over one hundred twenty papers, and was the recipient of the 1997 IEEE International Reliability Physics Symposium’s Best Paper Award, the 1997 NSREC Meritorious Paper Award and the 1998 NSREC Outstanding Paper Award. Dr. Lacoe was the Technical Program Chair for the 2007 International Reliability Physics Symposium and will be the General Chair in 2009.

140: FA AND PACKAGING SESSION

141: Defect Localization Developments: Science and Impact

Edward I. Cole Jr., Sandia National Laboratories

This tutorial will review the development and applications of various failure analysis tools that have made and are still making significant impact. In particular, the tutorial concentrates on: 1) optical beam tools, 2) photo-emission technologies, and 3) magnetic field analyses. Included in the discussions will be defect localization, including so-called "soft" defects, with a few comments on future developments. Best practices and limitations will also be discussed.

The tutorial's goal is to provide beneficial information to both novice and experienced failure analysts. Specific techniques to be covered include: reflected light imaging, Optical Beam Induced Current (OBIC), Light-Induced Voltage Alteration (LIVA), Thermally-Induced Voltage Alteration/Optical Beam Induced Resistance Change (TIVA/OBIRCH), Seebeck Effect Imaging (SEI), Soft Defect Localization (SDL), Light Alteration Defect Analysis (LADA), conventional light emission as well as Picosecond Imaging Circuit Analysis (PICA), and magnetic field imaging. Additionally, developments in solid immersion lens technology for improving backside optical spatial resolution will be addressed. For each technique the physics used for defect detection and examples illustrating the tool's application and importance will be presented.

Ed Cole

Edward Cole, Jr. received the B.A. (1981), M.S. (1985), and Ph.D. (1987) in physics from the University of North Carolina. He joined the Failure Analysis Department of Sandia National Laboratories in 1987. His research interests are in the development and improvement of non-destructive IC failure analysis tools, with emphasis on electron and optical beam techniques and he has published frequently in the field of failure analysis. Two failure analysis techniques developed by teams Dr. Cole led won R&D 100 awards in 1995 (CIVA) and 1998 (LIVA). In 1995 Dr. Cole was named a Distinguished Member of the Technical Staff at Sandia National Laboratories and in 2005 a Sandia Senior Scientist. He has served on the executive and management committees of the ISTFA and IRPS conferences, chairing the ISTFA'96 event and the IRPS'07 symposium. He is a past president of the Electronic Device Failure Analysis Society (EDFAS), chairman of the IRPS Board of Directors, and the EDFA magazine immediate past editor.

142: Packaging Reliability: Roadmap to Future

Rich Blish, Spasion

This tutorial will cover issues with which semiconductor packaging engineers need to become familiar. This material is an elaboration of the 2007 IRPS Year in Review for Packaging, but with additional material on the challenges of rf (radio frequency) issues (analog and mobile devices) and 3-d packaging concepts, beyond stacked chips with wire bonds. Key topics will be spot cooling using thermoelectric devices, superlattice refrigerators, interfacial adhesion, impact testing with nano-precipitates and wire bonding over fragile low dielectric constant materials.

Rich Blish

Rich Blish is a Spansion Fellow- for Reliability Modeling in Customer Quality Engineering. He is responsible for making failure rate projections and developing failure rate models as documented in JEDEC JEP 122D, for which Rich was Editor. Rich's primary focus is mentoring and training of new engineers, especially for their initial forays into the publishing realm. Other responsibilities include representing Spansion on the IRPS Technical Program Committee and acting as 2007 Chair for the Sematech ISMI Reliability Council. Rich was a founding Editor, and is frequent author/reviewer, for the all-electronic journal IEEE Transactions of Device, Materials and Reliability. Rich joined Spansion in 2007 after long service at AMD starting in 1995 as a Senior MTS for Reliability Modeling in Corporate Quality Division. Rich was the Editor for JEDEC JEP 122-A, which describes how IC failure rate projections (rate & distribution in time) are computed by all IC manufacturers and users (worldwide, Rev D is ready to submit to JEDEC ballot). Rich also used voltage stress & monitor data to develop model for Early Life and Intrinsic Life Failure Rate, such that a perfectly effective gate oxide defect screen could be implemented for programmable logic devices, reducing FIT rate >20X, protecting revenue of ~$150 million/yr. Rich produced $10 million/annum saving for a microprocessor system level screen. More recently Rich was responsible for improving Flash memory soft error rate by ~10-fold. Rich developed package reliability and failure analysis courses and taught both courses at domestic and international sites, IRPS and as a University of New Mexico/NTU video course, EECE 595 & NTU 506. Rich holds ~40 US patents (more pending) and has ~50 publications (many invited). Rich holds a B.S. in Physics, a M.S. and Ph.D in Materials Science, all from Caltech.

150: ESD AND LATCH-UP SESSION

151: ESD components in sub-100nm CMOS technologies

Gianluca Boselli, TI

In this tutorial, the physics of CMOS components under high current conditions to derive ESD protection design for sub-100 technologies will be discussed. Special emphasis will be devoted to the process aspects in an effort to confidently predict high current behavior and scaling properties. This is essential to understand the protection devices behavior and to optimize protection circuit networks.

Gianluca Boselli

Gianluca Boselli (M '99) completed his master's studies in electrical engineering at the University of Parma, Italy, in 1996. In 2001 he completed his doctoral studies at the University of Twente, The Netherlands, where he worked on high current phenomena in CMOS components. In February 2001, he joined the Silicon Technology Development group of Texas Instruments, Dallas, Texas, USA. Since joining Texas Instruments, his work focused on ESD and Latch-up development for advanced CMOS technologies with special emphasis on process and modeling aspects. He authored and co-authored several papers in the area of ESD and Latch-up. He presented his work at major conferences, including IEDM, IRPS and EOS/ESD Symposium. He also presented invited papers and/or tutorials at the EOS/ESD Symposium, IRPS, IEDM, ESREF and RCJ. Dr. Boselli has been the recipient of the "Best Paper Award" on behalf of Microelectronics Reliability Journal in 2000. He received "The Best Paper Award" at the EOS/ESD Symposium 2002. He also received the "The Best Presentation Award" at the EOS/ESD Symposium in 2002 and in 2006. Dr. Boselli is a senior member of IEEE and a member of ESD Association. Dr. Boselli serves on the Technical Program Committee of the EOS/ESD Symposium, IRPS and ESREF. Dr. Boselli has served as Technical Program Chair at the EOS/ESD Symposium 2006 and as Vice-General Chair in 2007. He will serve as General Chair at the EOS/ESD Symposium 2008.

152: Latch-up: Design, Modeling, Testing, Circuits and Computer Aided Design Methodology

Steven Voldman, Qimonda

CMOS latch-up continues to be of interest today in advanced CMOS, BiCMOS to smart power applications. In the design of ASICs, system on chip (SOC) and network on chip (NOC) applications, new latchup issues are occurring. Whereas last year, the focus of the latchup tutorial was placed on semiconductor technology, this years' latchup tutorial will provide a discussion on physical bipolar device models, simulation, design criteria, latch-up test structures, test methods, latch-up measurement techniques, circuit design techniques, latchup ground rules, and computer aided design methodologies. The tutorial will end with a discuss state-of-the-art latch-up issues, characterization techniques and tools. More focus will be placed on the design, design synthesis, integration, circuit solutions, latchup ground rules and CAD methods being proposed today and for the future.

Those attending this course will understand the practical issues that are needed to be addressed in semiconductor chip design needed for a circuit designers, layout engineers, test engineers, and quality and reliability teams. The course will focus on implementation, test structures, application, simulation, ground rules, and CAD design systems. Those attending will also understand the impact of design, semiconductor process and circuits on CMOS latch-up to produce latchup-free designs in future scaled technologies and semiconductor chips.

Steven H. Voldman

Steven H. Voldman is the first IEEE Fellow in ESD phenomenon field for "contributions to electrostatic discharge protection in CMOS, SOI and SiGe technologies" awarded at the IRPS 2003 in Dallas, Texas. He has received the Outstanding Achievement Award from the ESD Association in 2007. Voldman received his B.S. in Eng. Science from the Univ. of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from MIT; MS Eng. Physics (1986) and Ph.D EE (1991) from the Univ. of Vermont under IBM's Resident Study Fellow program.  He is presently working on ESD  in Qimonda on 300 mm advanced CMOS technologies and 58 nm product chips. As a reliability/device engineer since 1982, his work involved Bipolar SRAM and CMOS SRAM SER, MOSFET GIDL, hot electron, epitaxy/well design, CMOS latchup, and ESD. Voldman served as SEMATECH ESD Chair (1996-2000), EOS/ESD TPC, Vice Chair, and General Chair (1999-2002), IRPS ESD/Latchup Chairman (2003, 2004), EOS/ESD 2003 Past General Chairman, ESD Assoc. Board of Directors, ESD TLP and VF-TLP Work Group Standards Chairman, ESD Education Committee, IPFA Tech. Program Steering Committee, ISQED Committee,  Taiwan ESD Conference Technical Program Committee, International ESD Workshop (IEW) as well as providing ESD and latchup tutorials for the IRPS, IPFA and ESD Symposium and external courses internationally.  He is also a member of the ESDA and JEDEC 14 standards committees on ESD.  Voldman initiated and presently the chairman of the "ESD on Campus" program that has brought ESD and latchup lectures to over 23 top universities in the US, Singapore, Malaysia, Thailand, Taiwan and China.  Voldman is author of the first ESD book series, whose texts are  ESD: Physics and Devices,  ESD: Circuits and Devices, and ESD: RF Technology and Circuits, and a companion text, Latchup, released in December 2007.  He presently has 60 IBM Achievement Award plateau levels, Master Inventor Award, and has 162 issued U.S. patents.

210: CIRCUIT RELIABILITY SESSION

211: Variation Impacts on Circuit Design and Analytical Techniques for Optimization

Norman Rohrer, IBM

Transistor and interconnect variation is a reality in nanometer semiconductor processes. This tutorial will cover the sources of systematic and random variation of the transistor and the surrounding interconnect. Circuit sensitivities will include static and dynamic circuits, SRAMs and latches. Analytical techniques for optimizing these circuits will include Monte Carlo analysis, vector analysis and variation aware timing. In addition, across-chip variability and across-wafer variability has an impact on product level leakage power and AC power. Voltage and speed sorting techniques will be shown.

Norman Rohrer

Norman Rohrer is a Distinguished Engineer in the Systems and Technology Group of IBM located at Essex Junction, VT. Norman received his Bachelor's Degree in physics and mathematics from Manchester College, North Manchester, IN in 1987. He received his Master's Degree and Doctor of Philosophy degree in electrical engineering from The Ohio State University, Columbus, OH in 1990 and 1992, respectively. Norman has been a lead designer on PowerPC 750 and 970 products for Apple's G3 and G5 chips and Nintendo's GameCube. His interests lie in the area of high-speed circuit optimization for future technologies. Norman holds 24 patents and is a co-author on two books. He has been a Senior Member of IEEE since 2003.

212: Circuit Reliability

James H. Stathis, IBM

As MOSFET devices have scaled to nanometer dimensions, two dominant gate oxide failure mechanisms, dielectric breakdown and the negative bias instability, remain as a central focus of fundamental research and reliability engineering studies.  Ultimately, the relevance of these mechanisms depends on their impact on chip functionality and performance. An oxide breakdown event may or may not be destructive, depending on the particular circuit; the impact of NBTI also depends on the circuit architecture. This tutorial will teach the reliability engineer some basic circuit concepts necessary to understand the impact of breakdown and NBTI on circuit functionality and will give specific examples of the effects of oxide breakdown and NBTI on circuits.

James H. Stathis

Jim Stathis received the bachelors in physics from Washington University in St. Louis (1980), and the Ph.D. in physics from the Massachusetts Institute of Technology (1986), joining the IBM Research Division the same year. He is the author or co-author of more than 100 research papers and over 60 invited talks. From November 2005 to February 2007 he served as Technical Assistant to the Vice President for Science and Technology, IBM Research Division. In February 2007 he became manager of High-k/Metal-Gate Characterization and Reliability, IBM Research. Jim has served on technical program committees for SISC, INFOS, IRPS, ESREF, IPFA, and other conferences, served as Chair of the dielectrics sub-committee for the 2003 IRPS in Dallas, and is on the IRPS management committee. He has presented tutorials on CMOS reliability at IRPS, ESREF, and IPFA and is an Associate Editor of the journal Microelectronics Reliability.  He is a Senior Member of IEEE and a Fellow of the American Physical Society.

213: Reliability Modeling and Simulation for Sub-45nm Design

Yu (Kevin) Cao, Arizona State University

The scaling of CMOS technology to sub-45nm nodes inevitability leads to multiple reliability concerns, such as negative-bias-temperature-instability (NBTI) and time-dependent-dielectric-breakdown (TDDB). These effects manifest themselves as the temporal degradation of transistor parameters, profoundly affecting all aspects of circuit performance. While traditional research in this area has focused only on technology improvement, ignoring these effects in the design process causes an excessive amount of over-margining. As the reliability concerns become more severe with continuous scaling, it is critical to understand, simulate, and mitigate their impact during the design stage.

Design for reliability requires predictive design tools that can integrate the key degradation mechanisms, diagnose their impact on both dynamic and static operation, identify critical functional units, and evaluate the tradeoff among different performance metrics. The simulation and analysis of circuit aging are fundamentally difficult, since the degradation rate depends on both process and operation conditions, such as supply voltage, temperature, duty cycle, and input patterns. These conditions change significantly from gate to gate and from time to time, posing a dramatic challenge to efficient and accurate reliability analysis.

To improve circuit reliability and design predictability in the sub-45nm regime, this tutorial will present basic and more advanced topics on reliability modeling and simulation, including: the underlying reliability physics, compact modeling of leading reliability mechanisms, predictive models of short-term and long-term circuit aging, aging effect in various circuit units, simulation methods for hierarchical reliability analysis, tool development, and design practices for reliability. This tutorial will end with a discussion on future reliability challenges, helping shed light on the need of resilient design techniques and tools.

Yu (Kevin) Cao

Yu (Kevin) Cao received the B.S. degree in physics from Peking University in 1996. He received the M.A. degree in biophysics and the Ph.D. degree in electrical engineering from University of California, Berkeley, in 1999 and 2002, respectively. After working as a post-doctoral researcher at the Berkeley Wireless Research Center (BWRC), he is now an Assistant Professor of Electrical Engineering at Arizona State University, Tempe, Arizona. He has published numerous articles and coauthored one book on nano-CMOS physical and circuit design. His research interests include modeling and analysis of nanoscale CMOS circuits, physical-level design and tools for variability and reliability, and reliable integration of post-silicon technologies. Dr. Cao was a recipient of the 2007 Best Paper Award at International Symposium on Low Power Electronics and Design, the 2006 National Science Foundation CAREER Award, the 2006 and 2007 IBM Faculty Award, the 2004 Best Paper Award at International Symposium on Quality Electronic Design, and the 2000 Beatrice Winner Award at International Solid-State Circuits Conference. He currently serves on the technical program committee of numerous design automation and circuit design conferences.

220: MEMORY SESSION

221: Physical mechanisms and modelling of Flash and
post-Flash reliability

Daniele Ielmini, Politecnico di Milano

As the Flash memory reliability approaches its ultimate physical limitations, emerging technologies based on new materials and/or storage concepts are introduced. The reliability assessment and prediction of non volatile memories in such a transition scenario urges the engineer to handle complicated and distant physics and material issues, where the support of experimental observation, physical interpretation and numerical modelling play an unprecedented role.

Aim of this tutorial is to review the main reliability issues of Flash and post-Flash non volatile memories, discussing the phenomenology, interpretation and proposed modeling from a physical standpoint. The tutorial will cover the main reliability issues of Flash memories, including anomalous data-retention behaviors due to stress-induced leakage current, instability of threshold voltage due to detrapping effects and random-telegraph signal noise. The main roadblocks for Flash scaling will be underlined, and promising technologies for the post-Flash scenario will be discussed. Among the emerging-memory reliability issues, electron-hole leakage/redistribution in SONOS and NROM devices will be reviewed and discussed. Open issues and fundamental challenges will finally be outlined.

Daniele Ielmini

Daniele Ielmini received the Laurea (cum laude) and the Ph.D. degrees in nuclear engineering from the Politecnico di Milano, Milano, Italy in 1995 and 1999, respectively. In 1999, he joined the Dipartimento di Elettronica e Informazione, Politecnico di Milano, where he became an Assistant Professor in 2002. In 2006 he was a Visiting Scientist at Intel Co., Santa Clara and the Center for Integrated Systems, Stanford University, Stanford, USA. His main research interest are non volatile memory characterization and modelling, particularly in terms of leakage/switching phenomena, reliability and scaling projections. He has been working on several non volatile technologies, spanning from Flash to nitride- and nanocrystal-based charge-trap memories, and, most recently, to chalcogenide-based phase-change memories (PCM) and resistive-switching memories (RRAM). He is author/coauthor of more than 90 papers published in international journals and presented in international conferences, and of 3 patents in the field of non volatile memories. He is a member of IEEE and MRS. He has been serving as a sub-committee member for IEEE-International Reliability Physics Symposium (IRPS) since 2005.

222: Flash memory reliability and its management from system perspective

Young-Joon Choi, Samsung

Today Flash memory technology is rapidly changing portable systems. Rapid drop in Flash bit-cost and its high performance make possible giga-byte Flash storage for various consumer products. While the technology continues to move to lower bit cost, the endurance reliability, especially the number of re-write cycles, is getting degraded over scaling. In this tutorial, Flash memory technology, the failure modes, and system-level approach to manage them will be discussed. The practical requirements on the reliability of Flash depending on the types of systems will be discussed. System software driver and file-system for Flash can affect the performance and endurance of Flash. Basic architecture of Flash software, the behavior and the right management of it will be presented, too.

Young-Joon Choi

Young-Joon Choi has twenty-one years of experience in nonvolatile memory development with the memory division of Samsung Electronics, especially on NAND Flash for circuit-design, device-engineering and testing. Since 1997, he has been working on system-level application engineering, overseeing Flash software and file-system development in Samsung. He has more than thirty US patents on Flash memory design, system architecture and Flash software. Presently he is leading Application and Solution-Enabling of Flash memory in Samsung memory division.

223: Logic SER characterization

Xiaowei(Vivian) Zhu, TI

As technology scaling reduces dimensions and voltages to provide higher density and lower power functionality, the system sensitivity to radiation-induced soft errors (SER) increases. Soft errors, also known as single event upset, on ground level, is caused by alpha particles from packaging material and nuclear reaction product of terrestrial neutron and semiconductor material. Soft error can manifest in unpredictable system behavior, thus represent considerable risk for high reliability applications. This tutorial covers various aspects and some practical considerations in the characterization of logic SER at the accelerated conditions.

Xiaowei(Vivian) Zhu

Xiaowei(Vivian) Zhu (M'98) received the B.S. (1994) and M.S. (1997) in Applied Physics from South China University of Technology, Guangzhou, China, and the M.S. (2000), Ph.D (2002) in Electrical Engineering from Vanderbilt University, Nashville, TN. She joined Texas Instruments, Inc. in 2002. Her research interests include the characterization and modeling of radiation induced soft error rates in advanced CMOS technologies. Dr. Zhu has published several papers in the field of radiation induced single event upset, served as a technical session chair for IEEE Nuclear Science Radiation Effect Conference and International Conference on the Application of Accelerators in Research and Industry, she has also served as a board director of Association of Chinese Professionals foundation.

230: TECHNOLOGY, CIRCUIT AND CHIP RELIABILITY SESSION

231: Reliability Challenges of High-K and Metal Gate Transistor Technology

Sangwoo Pae, Intel

Leakage associated with the scaling of SiO₂ below 1.2nm thickness and the performance impact of carrier depletion in the Polysilicon gate are two critical limiters to transistor performance scaling. High-K dielectrics with Metal Gates (HK+MG) have been proposed to overcome these difficulties, but significant integration and reliability concerns have been reported as a result of the use of novel materials and complex integration schemes. This change is perhaps the most significant to MOS transistor architecture in 30 years and carries with it enormous difficulties and challenges associated with integration and reliability.

In this tutorial, reliability characterization and learning on 45nm HK-MG transistors as well as today's learning on HK reliability issues on literature reports are discussed.

Bias-temperature instability (BTI) and gate dielectric breakdown (TDDB) have been identified as the key reliability mechanisms on both NMOS and PMOS transistors. Accurate extrapolation of reliability data to the use condition in order to ensure safe product operating voltage involves insight into the tunneling mechanisms and the HK dielectric stack properties. Intrinsic reliability degradation mechanisms based on optimized HK process are discussed based on extensive experimental observations. Today and future challenges to the HK technology will be discussed.

Sangwoo Pae

Sangwoo Pae received the BSEE from the Chung-Ang University in Seoul, Korea (1994) and MS (1996) and Ph.D. degree (1999) in electrical and computer engineering from the Purdue University in West Lafayette, IN, USA. His Ph.D. thesis was on the multiple layers of SOI device islands fabrication for 3D integration of circuits. He joined Intel in 2000 and has been since working in the Logic Technology Development Q&R group in Hillsboro, OR, USA. He has been involved on FE reliability for the Intel's 130nm, 90nm, and 45nm logic process technology nodes. He has received two Intel Achievement Awards for his contribution on Intel's gate oxide reliability improvement on the 130nm node for CPU performance gain and resolving Intel's high-K/metal-gate transistor reliability issues at the 45nm node. Recently, he was responsible for the path finding FE reliability. His research interests include emerging reliability issues, novel devices, high-k dielectrics & metal gate transistors, and circuit reliability. He is author of more than 20 publications and holds 2 patents with 8 more pending in the semiconductor process, circuits, and reliability field.

232: Impact of back-end on circuit reliability

Tony Oates, TSMC

233: Electrically Programmed Fuse element:
Design, Characterization, Integration,
Reliability and Applications

Bill Tonti, IBM

Programmable eFuse designs present an integration challenge in modern CMOS processing. The power level to program a fuse, and the programming methodologies leverage reliability mechanisms which all other elements in a design avoid. A high degree of eFuse process control and circuit design is required in order to guarantee operation. Almost all eFuse types are one time programmable and are limited to "one chance" programmable. This tutorial will discuss selected eFuse technologies describing the design philosophy, electrical programming and characterization, the physics of failure, and some of the many applications an on chip programmable element provides.

William R. Tonti

William R. Tonti received the B.S.E.E. with honor (1978) from Northeastern Univ. He then joined IBM in Essex Jct., VT. He has previously held positions in the development of PowerPC microprocessor technology and reliability strategies, as well as a program manager in the wired communication space. Dr Tonti has also contributed to the giga-bit vertical cell DRAM technology development. He received the M.S.E.E. (1982) from the Univ. of VT, the M.B.A. (1983) from St. Michael’s College, and the Ph.D. in electrical engineering (1988) from the Univ. of VT under the auspices of the IBM resident study program. Dr. Tonti was the 2002 IRPS General Chairman, and the 2000 Integrated Reliability Workshop General Chairman, presently serving as the Chairman of the IRPS Board of Directors. He has authored numerous contributed and invited papers, and holds over 100 U.S. patents. Dr. Tonti is a member of tau beta pi, eta kappa nu, a senior member of the IEEE, an advisory board member of the IEEE Transactions on Device and Material Reliability, a recipient of the IEEE 3rd millennium medal, and an ABET engineering curriculum evaluator. Dr. Tonti served as President of the Reliability Society ADCOM.

240: PROCESS RELIABILITY SESSION

241: Plasma Process Induced Damage

Kin P. Cheung, NIST

Plasma is a harsh environment into which we repeatedly send our highly delicate wafers during manufacturing. Plasma is both an enabling technology and a source of problems. The management of the adverse effects while maximizing the benefit is a constant struggle that never ends. In this tutorial, we use the basic plasma property to understand how damage to the device occurs. The emphasis will be on charging damage. We will cover the basic mechanisms of plasma charging damage and will examine how oxide leakage affects both the extent of damage as well as damage detection. The impact on yield and reliability will be discussed. The issue of how to establish antenna design rule will be discussed and finally, how to minimize the impact of antenna rules on the design process.

Kin P. Cheung

Dr. Kin P. Cheung, obtained his Ph.D. degree in physical chemistry from New York University in 1983. From 83 to 85 he was a post doc at Bell Laboratories during which he pioneered Terahertz Spectroscopy. From 1985 to 2001 he was a member of technical staff in Bell Laboratories at Murray Hill. During this period, his research covers many new processing technologies, including plasma etching and deposition. He founded the plasma process damage conference and written the only book on the subject. Dr. Cheung also directly involve in technology integration during this period. He was also very active in device reliability research. From 2001 to 2007, He was an associate professor at Rutgers University. Currently, he is a project leader at Novel Device & Reliability Group, Semiconductor Electronics Division, NIST. Dr. Cheung published over 110 refereed journal and conference papers. He served as committee member in a number of international conferences and has been invited to give tutorial in 9 international conferences.

242: Wafer Level Reliability—Challenges of fast Wafer Level Reliability (fWLR) Monitoring

Andreas Martin, Infineon Technologies

Todays state of the art technologies introduce new materials into the process line. This emphasizes the importance of a process reliability monitoring tool. But also for well-understood technologies with larger minimum feature sizes a continuous fWLR Monitoring is essential especially for stringent product reliability specifications of automotive, medical or space applications. After process reliability qualification some tool is needed which indicates the stability of the reliability throughout mass production. "Zero defect" programs are well known and highlight the need for continuous reliability monitoring on product wafers. However, often used quarterly reliability re-qualification cannot achieve this task and is inappropriate. Therefore, fWLR Monitoring must be employed, covering reliability topics such as dielectric quality, plasma induced damage, device degradation and metallisation reliability.

In this tutorial an overview will be given including the discussion on test structures, stress measurements, data analysis and sampling. Further, the challenges will be pointed out which pop up during the implementation phase of fWLR monitoring on a parametric test station to perform in-line measurements. Limitations of the fWLR methodology as well as benefits will be highlighted based on a large number of references from journals and conferences. The topics of scrapping wafers with fWLR and defect density monitoring will be addressed.

This tutorial is suited for engineers and scientists who start in the area of fWLR Monitoring. But also colleagues who already work on the topic will benefit since different approaches are compared and discussed. Valuable details and literature citations can be picked up. Additionally, questions and any discussion are welcome during the tutorial.

Andreas Martin

Andreas Martin received his M.Eng.Sc. in Electrical and Electronic Engineering from the Technical University of Darmstadt, Germany, in 1992. He joined the silicon technology characterisation group of the Tyndall Institute (former National Microelectronics Research Centre - NMRC), Cork, Ireland in 1992 and worked on dielectric reliability assessment and reliability simulation. Since 1998 he works for the central Reliability Methodology department of Infineon Technologies AG in Munich, Germany in the field of fast productive WLR Monitoring. He is involved in advanced test structure design, development of new stress and measurement methodologies and data analysis techniques on the topics: dielectrics, plasma induced damage, metallisation and device topics. He manages fWLR Monitoring projects covering processes from 0.25µm down to 45nm for all Infineon processes worldwide. He has published and co-authored numerous papers, given tutorials and invited talks at conferences and served frequently in the management and / or technical committees of the IEEE IRW, IEEE IRPS and of the Workshop on Dielectrics in Microelectronics (WoDiM) for many years. He is a senior member of the IEEE, an alternate of the JEDEC subcommittee 14.2 and member of the ITG group 8.5.6 on WLR and reliability simulations. His current task in the JEDEC subcommitte 14.2 is the development of a guideline for fast Wafer Level Reliability Monitoring.