ERRATA: (pen or pencil corrections)
SESSION 1: DEVICE AND PROCESS
Co-Chairs: William R. Tonti, IBM Microelectronics and William R. Hunter, Texas Instruments, Inc.
96001=1.1 Cosmic Ray Neutron-Induced Upsets as a Major Contributor to the Soft Error Rate of Current and Future Generation DRAMs--W.R. McKee, H.P. McAdams, E.B. Smith, J.W. McPherson, J.W. Janzen, J.C. Ondrusek, A.E. Hyslop, D.E. Russell, R.A. Coy, D.W. Bergman, N.Q. Nguyen, T.J. Aton, L.W. Block, and V.C. Huynh, Texas Instruments, Inc., Dallas, TX
Cosmic ray neutrons are a significant source of errors in electronic devices at aircraft flight altitudes. Modelling and quantification of SSER (system soft error rate) is very important for future technologies. In this paper a simple model based on neutron-induced burst generation rates in silicon and a depletion layer charge collection volume is shown to be in very good agreement with SSER and n-ASER (neutron accelerated soft error rate) results. Effect of cosmic ray neutrons will become an important reliability issue at the 64Mb generation and beyond.
96007=1.2 Comparison of Charge Collection from Energetic Ions Typical of Neutron-Recoil Events with Charge Collection from Alpha Particle Strikes--T.J. Aton, J.A. Seitchik, and H. Shichijo, Texas Instruments, Inc., Dallas, TX
Alpha particles and cosmic-ray-generated neutrons are both important sources of soft errors in semiconductor memories. Fluorine ions are investigated as a means to better understand the effect of neutron generated charge on soft errors. It is observed that a fluorine ion can more readily induce a soft error in silicon as it generates about ten times as much charge as an alpha particle.
96012=1.3 The Effect of the Floating Gate/Tunnel SiO2 Interface on Flash Memory Data Retention Reliability--T. Kubota, K. Ando, and S. Muramatsu, NEC Corporation, Kanagawa, Japan
Data retention is an important reliability problem in Flash EEPROM memories. It is demonstrated that the presence of phosphorous at the floating gate/tunnel oxide interface plays an important role in the Flash EEPROM retention and in the generation of stress induced leakage current. This is caused by charge traps that are generated by the presence of phosphorous in the interfacial oxide layer. Amorphous silicon as floating gate material improves the retention characteristics.
96017=1.4 Relation Between Yield and Reliability of Integrated Circuits: Experimental Results and Application to Continuous Early Failure Rate Reduction Programs-- F. Kuper, J. van der Pol, E. Ooms, T. Johnson*, R. Wijburg, W. Koster, and D. Johnston, Philips Semiconductor, Nijmegen, The Netherlands
*Philips Semiconductors, Southampton, UK,
The correlation between yield and early field failures was investigated with several high volume IC's. The oxide degradation results obey a simple model involving the batch yield Y and the ratio a of reliabilty to yield defects. Approaches for increased reliability by improving either Y or a are discussed.
96022=1.5 Time Dependent Reliability of the Programmed Metal Electrode Antifuse--R.J.Wong, K.E.Gordon, and A.K.Chan, QuickLogic Corporation, Santa Clara, CA
Read disturb of programmed antifuses results in an increase of resistance, leading to degraded performance. This paper shows that mean cycles-to-disturb for ac operation depends on the peak current density, rather than a critical threshold value of the current density. Reliability criteria based on this behavior enable design of reliable FPGA product.
96027=1.6 Suppressing the Parasitic Bipolar Action of Ultra-Thin SOI MOSFETs Using Back-Side-Bias-Temperature Treatment--H.Koizumi, M.Shimaya, and T. Tsuchiya, NTT LSI Laboratories, Kanagawa, Japan
Fully depleted SOI n-channel MOSFETs exhibit an undesirable parasitic bipolar transistor operation resulting in a reduced drain to source breakdown voltage and degraded hot-carrier reliability. Bipolar suppression is achieved through a back side elevated temperature bias stress. This behavior may be explained by interface trap generation at the buried oxide/silicon interface acting as a recombination center.
96033=1.7 Investigation of Charge Damage Induced Vt Mismatch for Submicron Mixed-Signal Technology--J. Zhao, H.S. Chen, and C.S. Teng, National Semiconductor, Santa Clara, CA
The impact of process-induced charging damage on transistor parameters, whose precision control is critical in analog and mixed-signal circuitry, is investigated. Variations in threshold voltage and resulting Vt mismatch, arising from poly and metal antenna ratios for implant, etch and ashing processes, are controlled both by process optimization and a transmission gate circuit protection scheme.
SESSION 2: DIELECTRICS I
Co-Chairs: John S. Suehle, NIST and Bradley T. Moore, AMD
96037=2.1 A Failure Rate Based Methodology for Determining the Maximum Operating Gate Electric Field, Comprehending Defect Density and Burn-In-- W.R. Hunter, Texas Instruments, Inc., Dallas ,TX
A new and accurate methodology for determining the maximum allowed operating gate electric field Emax is developed. The method is based on assuring that a failure rate requirement is achieved for all times less than a required product lifetime. It is general and rigorously comprehends both an arbitrary defect density tail and burn-in.
96044=2.2 On the Field Dependence of Intrinsic and Extrinsic Time-Dependent Dielectric Breakdown--R. Degraeve, J.L. Ogier, R. Bellens, P. Roussel, G. Groeseneken, and H.E. Maes, IMEC, Leuven, Belgium
A new model is introduced describing the field dependence of intrinsic and extrinsic dielectric breakdown. Intrinsic breakdown is modeled as a statistical property of the oxide degradation process, while extrinsic breakdown is characterized by a local field enhancement. Competing bimodal Weibull distributions produce an excellent fit and allow extrapolations.
96055=2.3 Highly Reliable Furnace-Grown N2O Tunnel Oxide For Microcontrollerwith Embedded Flash EEPROM-- B. Maiti, D. Shum, W.M. Paulson, K-M. Chang, P.J. Tobin, M. Weidner, and C. Kuo, Motorola , Austin, TX
The superior characteristics of furnace-grown N2O oxynitrided tunnel oxide for microcontroller with embedded flash EEPROM applications are reported. These devices demonstrated excellent write and erase (W/E) endurance with small window closure when compared to thermal oxides. Improved read disturb lifetime and good drain disturb characteristics were obtained with N2O tunnel oxide after extended endurance stress.
96061=2.4 Electric Field Dependent Dielectric Breakdown oF Intrinsic SiO2 Films Under Dynamic Stress--P. Chaparala, J.S. Suehle*, C.R. Messick+, and M. Roush, University of Maryland, College Park, MD
* NIST, Gaithersburg, MD
+ National Semiconductor, West Jordan, UT
Time-dependent dielectric breakdown characteristics are reported for 9, 15, and 22-nm SiO2 films stressed under dc, unipolar pulsed, and bipolar pulsed bias conditions. The results indicate that the increased lifetime observed under bipolar and unipolar pulsed stress conditions diminshes as the stress electric field and oxide thickness are reduced. Increased pulsed lifetime are shown to correlate well with positive charge trapping.
96067=2.5 A New Oxide Degradation Mechanism for Stress in the Fowler-Nordheim Tunneling Regime--A. Martin, J.S. Suehle*, P. Chaparala+, P. O'Sullivan, and A. Mathewson, University College Cork, Ireland
* NIST, Gaithersburg, MD
+ University of Maryland, College Park, MD
Oxide Breakdown has been commonly related to a fixed amount of trapped oxide charge. In this work, gate oxide (6.6 nm-28 nm) stress measurements indicate that a pre-stress prior to the constant stress can increase the tBD. The trapping rate during the constant stress is a key factor for oxide breakdown.
96077=2.6 Ultra Thin Gate Oxide Reliability: Effects of Gate Doping Concentration and Gate-Electrode/SiO2 Interface Stress Relaxation--D. Wristers, H.H. Wang, L.K. Han, D.-L. Kwong, University of Texas, Austin, TX, and J. Fulford, AMD, Austin, TX
The impact of gate doping concentration on gate oxide reliability was investigated for 45Å to 85Å oxides. QBD for substrate injection shows dramatic improvement as doping reaches some threshold, while QBD for gate injection is unaffected. Material analysis suggests that doping-related stress/strain may play a critical role.
96084=2.7 A New Physics-Based Model for Time-Dependent Dielectric Breakdown--B. Schlund, Motorola, Inc., Scottsdale, AZ, C.R. Messick, National Semiconductor, West Jordan, UT, J.S. Suehle, NIST, Gaithersburg, MD, P. Chaparala, University of Maryland, College Park, MD
A new physics based model for time-dependent dielectric breakdown has been developed and is presented with test data for 15 and 22.5 nm oxides. The physics, mathematical model, and test data all confirm a linear field dependence, and the primary influence on oxide breakdown was determined to be due to the dipole interaction energy of the field and the orientation of the molecular dipoles in the dielectric.
SESSION 3A: DIELECTRICS II (Parallel Session A)
Co-Chairs: Joseph B. Bernstein, University of Maryland and Klaus F. Schuegraf, Micron
96093=3A.1 Limitations on Oxide Thickness in Flash EEPROM Applications-- E.F. Runnion, S.M. Gladstone, Texas Instruments, Inc., Lubbock, TX, R.S. Scott, Texas Instruments, Inc., Houston, TX, D.J. Dumin, Clemson University, Clemson, SC, L. Lie, LSI Logic Corp., Santa Clara, CA, and J. Mitros, National Semiconductor Corp., West Jordan, UT
The low-level leakage currents, flatband voltages, interface trap densities, and bulk trap densities were measured in oxides 4 nm and 11 nm thick before and after high-voltage stressing. The rise in the low-level leakage current in the thinner oxides places fundamental limits on oxide thickness for use in reliable FLASH EEPROMs.
96100=3A.2 A Quantitative Analysis of Stress Induced Excess Current (SIEC) in SiO2 Films--K. Sakakibara, N. Ajika, M. Hatanaka, and H. Miyoshi, Mitsubishi Electric Corp., Hyogo, Japan
By precisely modeling the tunneling process and quantitatively analyzing the transient current behavior, the distribution of the neutral traps, related to SIEC, increases towards the SiO2 interface. The generated neutral trap density remains constant under the same injected hole fluence regardless of electric field strength during stress.
96108=3A.3 Non-Uniform Current Flow through Thin Oxide After Fowler-Nordheim Current Stress--S. Yamada, K. Amemiya, T. Yamane, H. Hazama, and K. Hashimoto, Toshiba Corp., Kawasaki, Japan
An Array of EPROM bits demonstrates local effects in a large thin oxide area. While typical bits age uniformly, random bits show a cycle of increasing and decreasing leakage due to electron and hole trapping. As P/E cycling continues, additional bits will start the cycle, maintaining a continuous distribution of leakage.
96113=3A.4 Excess Current Induced by Hot-Hole Injection and F-N Stress in Thin SiO2 FILMS--A. Teramoto, K. Kobayashi, Y. Matsui, M. Hiraya, and A. Yasuoka, Mitsubishi Electric Corp., Hyogo, Japan
The excess current induced by hot-hole injection has been studied and compared to the excess current induced by F-N stress. Since the hole-trapping and Jg-Eg characteristics caused by the F-N stress correlate with those of hot-hole injection, the excess current induced by F-N stress is caused by injected holes
96117=3A.5 Trapped Hole Enhanced Stress Induced Leakage Currents in NAND EEPROM Tunnel Oxides--G.J. Hemink, K. Shimizu, S. Aritome, and R. Shirota, Toshiba Corp., Kawasaki, Japan
The stress-induced oxide leakage current of NAND EEPROM memory cells is investigated for different stress conditions. The leakage current strongly depends on the type of W/E stress, explained by a model where the interaction between holes and neutral traps results in stress-induced leakage current.
96122=3A.6 Field Enhanced Oxide Charge Detrapping in nMOSFETs--T. Wang, T.-E. Chang, and L.-P. Chiang, National Chiao-Tung University, Hsin-Chu, Taiwan, and C. Huang, Macronix International, Hsin-Chu, Taiwan
Field dependence of oxide trap discharging times in a 0.6 µm MOSFET after hot electron stress was characterized and modeled. The GIDL current was used to monitor the oxide charge detrapping-induced transient characteristics directly. Quantitative agreement between measured and calculated oxide trap time constants was obtained.
96126=3A.7 Thickness Mapping of Thin Dielectrics with Emission- and Conductive Force Microscopy for Assessment of Dielectrics Reliability--B. Ebersberger, and C. Boit, Siemens AG, Munich, Germany, H. Benzinger, Siemens AG, Dresden, Germany, E. Gunther, Siemens AG, Erlangen, Germany
An atomic force microscope equipped with a conductive tip was used to detect thickness variations of thin dielectrics by measuring highly localized Fowler-Nordheim tunneling current profiles as well as surface topology. Local oxide thinning with a lateral extent of several nm was observed at the boundary between gate and field oxides. This method promises to extend dielectric in-line monitoring.
SESSION 3B: METALLIZATION (Parallel Session B)
Co-Chairs: Carole Graas, Texas Instruments, Inc., and James R. Lloyd, Lloyd and Thompson Assoc.
96131=3B.1 Stress Relaxation and Microstructural Change in Passivated Al(Cu) Lines during Isothermal Annealing--I.-S. Yeo, C.-N. Liao, and P.S. Ho, University of Texas, Austin, TX
Relaxation of stresses in passivated Al lines can lead to void formation. In this paper bending beam techniques were used to study the stress-relaxation behavior of passivated Al-1%Cu lines (widths 3, 1, & 0.5 µm). Stress relaxation in Al(Cu) lines depends on line geometry and can be correlated with stress-induced voiding.
96139=3B.2 Effects of Insulator Surface Roughness on Al-Alloy Film Properties and Crystallographic Orientation in Al-Alloy/Ti/Insulator Structure--H. Onoda, T. Narita, K. Touchi, and K. Hashimoto, Oki Electric Industry Co., Ltd., Tokyo, Japan
The crystallographic orientation and surface roughness of high-temperature sputtered Al-alloys are both drastically affected by the surface roughness of the underlying insulator. This effect was thoroughly studied using various insulators and layered interconnects. Optimized EM performance and Al characteristics were obtained by combining a smooth-surface insulator with the use of Ti underlayers.
96148=3B.3 Short loop monitoring of metal step-coverage by simple electrical measurements--J. van der Pol, E.R. Ooms, and H.T. Brugman, Philips Semiconductors, Nijmegen, Netherlands
A metal step-coverage monitoring method using simple electrical measurements has been developed to overcome drawbacks of the standard cross sectioning method. Application to BiCMOS and bipolar processes show that a) step-coverage related design rules can be easily verified, b) step-coverage depends strongly on metal sputter target lifetime and c) step-coverage can vary significantly across the wafer, demonstrating the importance of wafer-map data.
96156=3B.4 Reliability and Electrical Properties of New Low Dielectric Constant Interlevel Dielectrics for High Performance ULSI Interconnect--B. Zhao, S. Wang, M. Fiebig, P. Vasudev, and T. Seidel, SEMATECH, Austin, TX
High performance ULSI interconnects require new low-k interlevel dielectric (ILD) materials. This paper presents reliability and electrical data for several ILDs under development. It is shown that interconnect reliability can be impacted by the choice of the ILD material.
96164=3B.5 Modeling of EM Failure Distributions of Al Alloy Contacts and Vias in Submicron IC Technologies--A.S. Oates, AT&T Bell Laboratories, Orlando, FL
An adequate description of EM failure at contacts/vias requires an understanding of MTF and s (sigma). This paper compares s (sigma) values measured experimentally and calculated from a void growth model. It is shown that s (sigma) varies with accelerated test conditions, and the implications of this observation on reliability engineering of contact/via processes are discussed.
96172=3B.6 iTEM: A Chip-Level Electromigration Reliability Diagnosis Tool Using Electrothermal Timing Simulation--C.-C. Teng. Y.-K. Cheng, E. Rosenbaum, S.-M. Kang, University of Illinois , Urbana-Champaign, Urbana, IL
This paper presents a new tool for the design of EM resistant interconnect systems: iTEM. iTEM takes into account current density and line geometry as well as steady-state temperature. This provides much more accurate simulation results than existing EM diagnosis tools, and was applied to large circuit layouts.
96180=3B.7 Modeling Electromigration Failures Under Bidirectional Current Stress--J. Tao, Siliconix, Santa Clara, CA, J.F. Chen, N.W. Cheung, and C. Hu, University of California, Berkeley, CA
Various metallizations were studied under bidirectional current stress of wide frequency range (mHz to 200 MHz). At low frequency, the damage healing factor and lifetime increase with frequency. At very high frequency, the lifetime was determined by thermal effects instead of EM. These observations are in agreement with an average current model.
SESSION 4A: OPTOELECTRONICS AND COMPOUND SEMICONDUCTORS (Parallel Session A)
Co-Chairs: Daniel L. Barton, Sandia National Laboratories and Sammy A. Kayali, Jet Propulsion Laboratory
96188=4A.1 A Degradation Monitor for the Light Output of LEDs based on Cathodoluminescence Signals and Junction Ideality Factor--V. Wittpahl, Y.Y. Liu, D.S.H. Chan, W.K. Chim, J.C.H. Phang, National University of Singapore, Singapore, L.J. Balk, Wuppertal University, Wuppertal, Germany, and K.P. Yan, Siemens Components, Melaka, West Malaysia
Light output (LOP) degradation monitors for light emitting diodes based on the differential cathodoluminescence signal and changes in the junction ideality factor are described. These monitors are applied to screen for devices likely to have significant long term LOP degradation.
96195=4A.2 Degradation Models and Lifetime Projections of InGaAs/InP MQW-DFB Laser Diodes for High-Speed Optical Communication Systems--N. Hwang, S.-G. Kang, H.-T. Lee, M.-K. Song, and K.-E. Pyun, Electronics and Telecommunications Research Institute, Taejon, Korea
Laser diode (LD) lifetime is usually characterized at constant current while actual operation is under constant optical power. Such an approach leads to invalid lifetime predictions. The LD parameters Ith, h, Iop, and Pop, of 1.55 µm InGaAs/InP MQW-DFB LDs in combination are shown to better project reliability.
96199=4A.3 Reliability Tests and Failure Analysis for Quality Improvement in 1.5 µm Fabry-Perot Lasers--P. Montangero, G.A. Azzini, R. Crovato, L. Ricci, L. Serra, CSELT, Torino, Italy
Life tests and failure analysis on two groups of buried structure laser diodes (buried mushroom - BMS and buried ridge - BRS) have been used to improve quality. A comparison of the degradation levels and failure mechanisms suggested the choice of the BRS structure with the application of several technological improvements. A new group of BRS devices showed fewer defects and good stability during life testing.
96203=4A.4 Reliability Study of 850 nm VCSELs for Data Communications--R.A. Hawthorne, J.K. Guenter, D.N. Granville, Honeywell Micro Switch, Richardson, TX, and M.K. Hibbs-Brenner and R.A. Morgan, Honeywell Technology Center, Plymouth, MN
This paper presents the reliability results for 850 nm vertical cavity surface emitting lasers (VCSEL). Hundreds of parts from multiple wafer lots and package styles were subjected to burn-in for thousands of hours at various temperatures and currents, yielding more than one million device-hours of data. Possible failure mechanisms will be discussed.
96211=4A.5 Degradation Mechanisms of Vertical Cavity Surface Emitting Lasers--R.W. Herrick,Y.M. Cheng, P.M. Petroff, University of California, Santa Barbara, CA, and M.K. Hibbs-Brenner, R.A. Morgan, Honeywell Technology Center, Plymouth, MN
The results of studies of failure modes of vertical cavity surface emitting lasers (VCSELs) are discussed. Degradation of the VCSEL mirror layers is shown to be more important than declining active region efficiency. The mechanism responsible for the mirror degradation is discussed.
96214=4A.6 Degradation Mechanism in Carbon-doped GaAs Minority-carrier Injection Devices--H. Fushimi and K. Wada, NTT LSI Laboratories, Kanagawa, Japan
GaAs/AlGaAs heterojunction bipolar transistors (HBTs) with carbon-doped bases have displayed serious degradation during long term operation; i.e., decreased current gain and increased low bias leakage current. It has been suggested that hydrogen which is unintentionally incorporated into the carbon-doped base layer causes this degradation. This paper shows that carbon-hydrogen (C-H) complexes are easily decomposed under minority carrier injection and cause the device degradation.
96221=4A.7 Modeling the Abnormal Base Current in Post-Burn-in AlGaAs/GaAs Heterojunction Bipolar Transistors--S. Sheu, J.J. Liou, University of Central Florida, Orlando, FL, and C.I. Huang, Wright Laboratory, Wright-Patterson AFB, OH
Base current of AlGaAs/GaAs heterojunction bipolar transistor (HBT) subjected to a long burn-in test often exhibits an abnormal characteristic with an ideality factor of approximately three (3) in the mid-voltage range. This paper develops an analytical model to investigate the physical mechanisms underlying such a characteristic. Post-burn-in data measured from two different HBTs are also included in support of the model.
SESSION 4B: ESD/PACKAGING (Parallel Session B)
Co-Chairs: Carlos H. Diaz, Hewlett-Packard and Marc A. Manheimer, Laboratory for Physical Sciences
96227=4B.1 Design and Layout of a High ESD performance n-p-n Structure for Submicron BiCMOS/Bipolar Circuits--J.Z. Chen, X.Y. Zhang*, A. Amerasekera, and T. Vrotsos, Texas Instruments, Inc., Dallas, TX
*Stanford University, Palo Alto, CA
Design and Layout Issues for obtaining a high ESD performance n-p-n protection structure in advanced submicron Bipolar/BiCMOS processes are discussed. Using a Zener trigger circuit and a specific multi-emitter layout technique, this paper demonstrates an optimal protection structure for advanced submicron circuit applications. This protection circuit has a low trigger voltage and a low capacitance load with no series resistance.
96233=4B.2 Process and Design for ESD Robustness in Deep Submicron CMOS Technology--C. Jiang, E. Nowak, and M. Manley, VLSI Technology, San Jose, CA
The impact of process variation and physical design on the NMOSFET ESD performance of a 0.35 micron CMOS technology is investigated using TLP techniques. This study shows that It2 increases with increases in the number of S/D contacts, and increases in drain contact to gate spacing.
962237=4B.3 Characterization of VLSI Circuit Interconnect Heating and Failure Under ESD Conditions--K. Banerjee, University of California, Berkeley, CA, A. Amerasekera, Texas Instruments,Inc., Dallas, TX, and C. Hu, University of California, Berkeley, CA
Thin AlCu interconnect heating and failure under ESD stresses in a quadruple level metallization (QLM) system was studied. We have determined a relation between critical current, pulse width and line geometry that can be used to design ESD protection circuit interconnects. We have also identified a potential reliability hazard in the form of "latent ESD damage" that can degrade metal lifetime.
96246=4B.4 Investigation of Stress Singularity Fields and Stress Intensity Factors for Package Cracking--M. Amagai, Texas Instruments Japan, Oita, Japan
Package cracks induced by interfacial delamination are a major failure mode in lead-on-chip (LOC) packages. In this study, stress singularity fields at the tip of interfacial delamination between dissimilar materials are investigated. It is found that stress intensity obtained by resolving stress singularity is a very important factor in predicting package cracking.
4B.5 Failure Analysis of Cathode Filament Formation in Multilayer PWBs Using Combined Electron Spin Resonance and Micro-FTIR Techniques--P. Yalamanchili, M. Al-Sheikhly, and A. Christou, University of Maryland, College Park, MD
Electron spin resonance and infrared techniques are utilized to study conductive filament formation failures in printed wiring boards. Complementary techniques are necessitated by the presence on boards of both non-conductive fibers and conductive plated through-holes. It is found that copper particles trapped in the epoxy during board manufacture contribute to these failures.
96258=4B.6 Conductive Anodic Filament Enhancement in the Presence of Certain Polyglycol-Containing Fluxes--W.J. Ready, L.J. Turbini, and S.R. Stock, Georgia Institute of Technology, Atlanta, GA
The dimensions and growth patterns of conductive anodic filaments (CAF) have been determined by serial sectioning of printed wiring boards, in conjunction with scanning electron microscopy and energy dispersive x-ray analysis. Results show that use of polyglycol-containing fluxes enhances the susceptibility of boards to CAF. The polyglycols decrease the critical relative humidity of the board and increase water absorbtion.
4B.7 Stress in High Rate Deposited Silicon Dioxide Films for MCM Applications--M.S. Haque, H.A. Naseem, and W.D. Brown, University of Arkansas, Fayetteville, AR
Thick PECVD SiO2 films were deposited at 1000 Å/min in the 250-350°C range for MCM applications. A considerable change in stress has been observed during annealing in the 250-400°C range. Stress of the as-deposited and annealed films was monitored for two months in a clean room environment. The moisture absorption and diffusion coefficients of these high rate deposited films were found to be high.
SESSION 5: HOT-CARRIERS
Co-Chairs: Faran Nouri, Technology Modeling Associates and Kaizad R. Mistry, Digital Equipment Corp.
96281=5.1 A New Algorithm for NMOS ac Hot-Carrier Lifetime Prediction Based on the Dominant Degradation Asymptote--S.W.A. Kim, B. Menberu, and J.E. Chung, MIT, Cambridge, MA
This study presents an algorithm for improved prediction of ac hot-carrier lifetime. The algorithm is based on identifying and projecting the dominant degradation asymptote and accounts for both the stress-bias-dependent degradation rate, n, and the non-linearity of the degradation time-dependence. Over a wide range of CMOS inverter designs, significant differences in the predicted ac lifetime are found between the existing and the new algorithms.
96289=5.2 Unified Model for n-Channel Hot-Carrier Degradation Under Different Degradation Mechanisms--M. Pagey, R. Milanowski, E.S. Snyder*, N. Bui, B. Deem, B. Bhuva, and S. Kerns,Vanderbilt University, Nashville, TN,
*Sandia National Laboratories, Albuquerque, NM
A new unified model incorporating the coupled effects of three dominant degradation mechanisms is developed and experimentally compared with conventional models. We show that this coupling is essential for accurate prediction of time dependence of hot-carrier degradation in LDD NMOSFETs. Since the model includes the effect of three dominant degradation mechanisms under circuit operation of the device, it is particularly suitable for accurate circuit simulations.
96294=5.3 The Effects of Reverse-Bias Emitter-Base Stress on the Cryogenic Operation of Advanced UHV/CVD Si- and SiGe-base Bipolar Transistors--J.A. Babcock, Motorola, Mesa, AZ, A.J. Joseph and J.D. Cressler, Auburn University, Auburn, AL, and D.L. Harame, IBM Microelectronics, Hopewell Junction, NY
This paper demonstrates, for the first time, that hot-carrier injection resulting from reverse-bias emitter-base stress at 300K can result in significant shifts in the low-temperature electrical characteristics of epitaxially grown Si- and SiGe-base bipolar transistors. Temperature dependent base current leakage is attributed to a Poole-Frenkel field-enhanced tunneling mechanism.
96300=5.4 Gate Oxide Thickness Dependence of RIE-Induced Damage on n-Channel MOSFET Reliability--A.B. Joshi, L. Chung, B.W. Min, L.K. Han, Rockwell Telecommunications, Newport Beach, CA, and D.L. Kwong, University of Texas, Austin, TX
We have investigated the gate oxide thickness dependence of RIE-induced damage on nMOSFETs. Results show that devices with thinner gate oxide show smaller degradation under both hot-carrier and F-N stressing compared to thicker gate oxide devices for a given antenna ratio and type of RIE-induced damage. A model is proposed to explain these observations.
96305=5.5 On the Hot-Hole-Induced Post-Stress Interface Trap Generation in MOSFETs--I.S. Al-kofahi and J.F. Zhang, Liverpool John Moores University, Liverpool, UK, and G. Groeseneken, IMEC, Leuven, Belgium
The enhanced degradation of MOSFETs post stress has been reported in recent IRPS and this paper presents new results and findings. It is found that the interface traps generated during and post stress originate from different kinds of defects and that the results can not be satisfactorily explained by theories available.
96311=5.6 A New Purely Experimental Method for Extracting the Spatial Distribution of Hot-Carrier Induced Interface States and Trapped Charges in MOSFETs--S.E. Leang, D.S.H. Chan, and W.K. Chim, National University of Singapore, Singapore
A new method to extract the spatial distribution of hot-carrier induced interface state and trapped charge density is proposed. This method is purely experimental, does not require simulation, and therefore does not require detailed knowledge of the device structure. With this new method, one is able to gain better understanding of the degradation mechanisms which take place during hot-carrier stressing.
96318=5.7 Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulation--A. Amerasekera, S. Ramaswamy*, M.-C. Chang, and C.A. Duvvury, Texas Instruments, Inc., Dallas, TX
* University of Illinois, Urbana Champaign, Urbana, IL
A circuit-level model equation set for the avalanche and snapback regions of the MOS high current I-V curves has been developed and implemented. A practical parameter extraction methodology is presented which requires a single set of high current I-V curves and builds on the existing MOS SPICE parameter set. The models extend the capability of circuit-level simulators to the ESD and EOS regions of transistor operation.
SESSION 6: FAILURE ANALYSIS
Co-Chairs: Ronald E. Pyle, Motorola, and Edward I. Cole, Jr., Sandia National Laboratories
96327=6.1 Hydrogen Passivation of Boron Acceptors and Long-Term Breakdown Voltage Instability in n+/p Surface Avalanche Diodes--M. Ciappa, P. Malberti, and A. Birolini, Swiss Federal Institute of Technology, Zurich, Switzerland
A large drift in the breakdown voltages of n+/p surface avalanche diodes has been observed after 20,000 hours of operation. This paper explains the instability in terms of boron acceptor passivation by hydrogen from the silicon nitride passivation. The main symptoms and detection techniques for this failure mechanism are reported.
96332=6.2 Novel MCM Interconnection Analysis Using Capacitive Charge Generation (CCG)--E.I. Cole, Jr., K.A. Peterson, and D.L. Barton, Sandia National Laboratories, Albuquerque, NM
A new SEM technique, Capacitive Charge Generation (CCG), has been developed to rapidly image MCM interconnection continuity. The technique uses low primary electron beam energies and has been applied to conductors covered by 60 µm of dielectric. The physics of CCG signal generation and applications to MCM failure analysis are described.
96342=6.3 Failure Analysis of Sub-Micrometer Devices and Structures by Scanning Thermal Microscopy--J. Lai, K. Luo, A. Majumdar, and Z. Shi, University of California, Santa Barbara, CA
We have developed a new scanning thermal microscopy (SThM) technique to simultaneously measure surface morphology and temperature gradients. SThM is used to detect ESD and electromigration defects in transistors, metal lines, and vias with 0.05 µm spatial resolution. SThM is an ideal tool for examining existing and new failure mechanisms.
96346=6.4 New Laser Beam Heating Methods Applicable to Fault Localization and Defect Detection in Actual VLSI Devices--K. Nikawa and S. Inoue, NEC Corporation, Kanagawa, Japan
Two optical beam induced resistance change (OBIRCH) based methods have been developed: infrared and selected area OBIRCH. These methods have been applied to fault localization and defect detection in VLSI devices. The infrared OBIRCH is demonstrated to localize the current paths in IDDQ failures.
96355=6.5 High Temperature IDDQ Drift Testing for Detection of Sodium and Potassium--E. Sabin, Silicon Systems, Santa Cruz, CA
Silicon Systems has instituted an IDDQ drift test performed at 175°C on a BiCMOS device. Large drifts in IDDQ have been observed from ionic contamination in and around the field oxide. IDDQ drift testing can be used as an alternative to standard Vt shift testing for mobile ion detection.
96360=6.6 A High-Sensitivity Photo-Emission Microscope System with Continuous Wavelength Spectroscopic Capability--J.M. Tao, W.K. Chim, D.S.H. Chan, J.C.H. Phang, and Y.Y. Liu, National University of Singapore, Singapore
A new photo-emission microscope system with high-sensitivity, continuous wavelength spectroscopic capability is presented. The light collection and transmission optics permit acquisition of high-resolution spectral characteristics from very low intensity emissions. The potential use of spectral characteristics to identify failure mechanisms is also discussed.
96366=6.7 Nanoscopic EBIC Technique in a hybrid SEM/SFM System--R. Heiderhoff, R.M. Cramer, and L.J. Balk, Wuppertal University, Wuppertal, Germany
High resolution electron beam induced current (EBIC) analyses were carried out in a scanning electron (SEM) and scanning force microscope (SFM) hybrid system. The method allowed simultaneous measurement of morphological and electrical properties of polycrystalline diamond with an obtainable spatial resolution in the nm region. The extension of the approach to IC analysis is discussed.